static int iphone_wm8991_link_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; int ret; ret = snd_soc_dai_set_clkdiv(codec_dai, WM8991_MCLK_DIV, WM8991_MCLK_DIV_2); if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(codec_dai, WM8991_BCLK_DIV, WM8991_BCLK_DIV_8); if (ret < 0) return ret; // this forces N = 7, K = 0x85FC for wm8991. ret = snd_soc_dai_set_pll(codec_dai, 0, 0, 0x0785FC); if (ret < 0) return ret; ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM); if (ret < 0) return ret; ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM); if (ret < 0) return ret; return 0; }
static int sdp4430_dmic_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; int ret = 0; if (!rtd->dai_link->no_pcm) ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS, 24000000, SND_SOC_CLOCK_IN); else ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_DMIC_SYSCLK_PAD_CLKS, 19200000, SND_SOC_CLOCK_IN); if (ret < 0) { printk(KERN_ERR "can't set DMIC cpu system clock\n"); return ret; } if (!rtd->dai_link->no_pcm) ret = snd_soc_dai_set_clkdiv(cpu_dai, OMAP_DMIC_CLKDIV, 10); else ret = snd_soc_dai_set_clkdiv(cpu_dai, OMAP_DMIC_CLKDIV, 8); if (ret < 0) { printk(KERN_ERR "can't set DMIC cpu clock divider\n"); return ret; } return 0; }
static int smdk_wm8580_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; int rfs, ret; switch (params_rate(params)) { case 8000: break; default: printk(KERN_ERR "%s:%d Sampling Rate %u not supported!\n", __func__, __LINE__, params_rate(params)); return -EINVAL; } rfs = mclk_freq / params_rate(params) / 2; if (mclk_freq == xtal_freq) { ret = snd_soc_dai_set_sysclk(codec_dai, WM8580_CLKSRC_MCLK, mclk_freq, SND_SOC_CLOCK_IN); if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_MCLK, WM8580_CLKSRC_MCLK); if (ret < 0) return ret; } else { ret = snd_soc_dai_set_sysclk(codec_dai, WM8580_CLKSRC_PLLA, mclk_freq, SND_SOC_CLOCK_IN); if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_MCLK, WM8580_CLKSRC_PLLA); if (ret < 0) return ret; ret = snd_soc_dai_set_pll(codec_dai, WM8580_PLLA, 0, xtal_freq, mclk_freq); if (ret < 0) return ret; } /* Set PCM source clock on CPU */ ret = snd_soc_dai_set_sysclk(cpu_dai, S3C_PCM_CLKSRC_MUX, mclk_freq, SND_SOC_CLOCK_IN); if (ret < 0) return ret; /* Set SCLK_DIV for making bclk */ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_PCM_SCLK_PER_FS, rfs); if (ret < 0) return ret; return 0; }
static int init_dais(struct snd_soc_dai *cpu_dai, struct snd_soc_dai *codec_dai) { int ret; /* Set the Codec DAI configuration */ #ifdef CONFIG_SND_WM8580_MASTER ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); #else ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); #endif if (ret < 0) return ret; /* Set the AP DAI configuration */ #ifdef CONFIG_SND_WM8580_MASTER ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); #else ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); #endif if (ret < 0) return ret; /* Select the AP Sysclk */ #ifdef CONFIG_SND_WM8580_MASTER ret = snd_soc_dai_set_sysclk(cpu_dai, S3C_CDCLKSRC_EXT, 0, SND_SOC_CLOCK_IN); #else ret = snd_soc_dai_set_sysclk(cpu_dai, S3C_CDCLKSRC_INT, 0, SND_SOC_CLOCK_OUT); #endif if (ret < 0) return ret; #ifdef CONFIG_SND_WM8580_MASTER ret = snd_soc_dai_set_sysclk(cpu_dai, S3C_CLKSRC_SLVPCLK, 0, SND_SOC_CLOCK_IN); #else #ifdef CONFIG_S5P_USE_CLKAUDIO ret = snd_soc_dai_set_sysclk(cpu_dai, S3C_CLKSRC_CLKAUDIO, 44100, SND_SOC_CLOCK_OUT); #else ret = snd_soc_dai_set_sysclk(cpu_dai, S3C_CLKSRC_PCLK, 0, SND_SOC_CLOCK_OUT); #endif #endif if (ret < 0) return ret; /* Set the Codec BCLK(no option to set the MCLK) */ /* See page 2 and 53 of Wm8580 Manual */ #ifdef CONFIG_SND_WM8580_MASTER ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_MCLK, WM8580_CLKSRC_PLLA); /* Use PLLACLK in AP-Slave Mode */ #else ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_MCLK, WM8580_CLKSRC_MCLK); /* Use MCLK provided by CPU i/f */ #endif if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_CLKOUTSRC, WM8580_CLKSRC_NONE); /* Pg-58 */ if (ret < 0) return ret; return 0; }
static int jive_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; struct s3c_i2sv2_rate_calc div; unsigned int clk = 0; int ret = 0; switch (params_rate(params)) { case 8000: case 16000: case 48000: case 96000: clk = 12288000; break; case 11025: case 22050: case 44100: clk = 11289600; break; } s3c_i2sv2_iis_calc_rate(&div, NULL, params_rate(params), s3c_i2sv2_get_clock(cpu_dai)); /* set codec DAI configuration */ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); if (ret < 0) return ret; /* set cpu DAI configuration */ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); if (ret < 0) return ret; /* set the codec system clock for DAC and ADC */ ret = snd_soc_dai_set_sysclk(codec_dai, WM8750_SYSCLK, clk, SND_SOC_CLOCK_IN); if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C2412_DIV_RCLK, div.fs_div); if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C2412_DIV_PRESCALER, div.clk_div - 1); if (ret < 0) return ret; return 0; }
static int hdmi_i2s_hifi_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; unsigned int pll_out = 0, dai_fmt = rtd->dai_link->dai_fmt; int div_bclk,div_mclk; int ret; DBG("Enter::%s----%d\n", __FUNCTION__, __LINE__); /* set cpu DAI configuration */ ret = snd_soc_dai_set_fmt(cpu_dai, dai_fmt); if (ret < 0) { printk("%s():failed to set the format for cpu side\n", __FUNCTION__); return ret; } switch(params_rate(params)) { case 8000: case 16000: case 24000: case 32000: case 48000: case 96000: pll_out = 12288000; break; case 11025: case 22050: case 44100: case 88200: pll_out = 11289600; break; case 176400: pll_out = 11289600*2; break; case 192000: pll_out = 12288000*2; break; default: printk("Enter:%s, %d, Error rate=%d\n", __FUNCTION__, __LINE__, params_rate(params)); return -EINVAL; break; } DBG("Enter:%s, %d, rate=%d\n", __FUNCTION__, __LINE__, params_rate(params)); div_bclk = 63; div_mclk = pll_out/(params_rate(params)*64) - 1; snd_soc_dai_set_sysclk(cpu_dai, 0, pll_out, 0); snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_BCLK,div_bclk); snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_MCLK, div_mclk); DBG("Enter:%s, %d, pll_out/4/params_rate(params) = %d , div_mclk:%d\n", __FUNCTION__, __LINE__, (pll_out/4)/params_rate(params), div_mclk); return 0; }
static int rx1950_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; int div; int ret; unsigned int rate = params_rate(params); int clk_source, fs_mode; switch (rate) { case 16000: case 48000: clk_source = S3C24XX_CLKSRC_PCLK; fs_mode = S3C2410_IISMOD_256FS; div = s3c24xx_i2s_get_clockrate() / (256 * rate); if (s3c24xx_i2s_get_clockrate() % (256 * rate) > (128 * rate)) div++; break; case 44100: case 88200: clk_source = S3C24XX_CLKSRC_MPLL; fs_mode = S3C2410_IISMOD_384FS; div = 1; break; default: printk(KERN_ERR "%s: rate %d is not supported\n", __func__, rate); return -EINVAL; } /* select clock source */ ret = snd_soc_dai_set_sysclk(cpu_dai, clk_source, rate, SND_SOC_CLOCK_OUT); if (ret < 0) return ret; /* set MCLK division for sample rate */ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C24XX_DIV_MCLK, fs_mode); if (ret < 0) return ret; /* set BCLK division for sample rate */ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C24XX_DIV_BCLK, S3C2410_IISMOD_32FS); if (ret < 0) return ret; /* set prescaler division for sample rate */ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER, S3C24XX_PRESCALE(div, div)); if (ret < 0) return ret; return 0; }
static int rt3261_voice_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; unsigned int pll_out = 0; int ret; DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBS_CFS ); switch(params_rate(params)) { case 8000: case 16000: case 24000: case 32000: case 48000: pll_out = 12288000; break; case 11025: case 22050: case 44100: pll_out = 11289600; break; default: DBG("Enter:%s, %d, Error rate=%d\n", __FUNCTION__, __LINE__, params_rate(params)); return -EINVAL; break; } DBG("Enter:%s, %d, rate=%d\n", __FUNCTION__, __LINE__, params_rate(params)); /*Set the system clk for codec*/ snd_soc_dai_set_pll(codec_dai, 0, RT3261_PLL1_S_MCLK, pll_out, 24576000); ret = snd_soc_dai_set_sysclk(codec_dai, RT3261_SCLK_S_PLL1, 24576000, SND_SOC_CLOCK_IN); if (ret < 0) { printk("rk29_hw_params_rt3261:failed to set the sysclk for codec side\n"); return ret; } snd_soc_dai_set_sysclk(cpu_dai, 0, pll_out, 0); snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_BCLK, (pll_out/4)/params_rate(params)-1); snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_MCLK, 3); DBG("Enter:%s, %d, pll_out/4/params_rate(params) = %d \n", __FUNCTION__, __LINE__, (pll_out/4)/params_rate(params)); return 0; }
static int rk29_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; unsigned int pll_out = 0, dai_fmt = rtd->card->dai_link->dai_fmt; int ret; DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); /* set codec DAI configuration */ ret = snd_soc_dai_set_fmt(codec_dai, dai_fmt); if (ret < 0) { printk("%s():failed to set the format for codec side\n", __FUNCTION__); return ret; } /* set cpu DAI configuration */ ret = snd_soc_dai_set_fmt(cpu_dai, dai_fmt); if (ret < 0) { printk("%s():failed to set the format for cpu side\n", __FUNCTION__); return ret; } switch(params_rate(params)) { case 8000: case 16000: case 24000: case 32000: case 48000: pll_out = 12288000; break; case 11025: case 22050: case 44100: pll_out = 11289600; break; default: DBG("Enter:%s, %d, Error rate=%d\n",__FUNCTION__,__LINE__,params_rate(params)); return -EINVAL; break; } DBG("Enter:%s, %d, rate=%d\n",__FUNCTION__,__LINE__,params_rate(params)); if ((dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBS_CFS) { snd_soc_dai_set_sysclk(cpu_dai, 0, pll_out, 0); snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_BCLK, (pll_out/4)/params_rate(params)-1); snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_MCLK, 3); } DBG("Enter:%s, %d, LRCK=%d\n",__FUNCTION__,__LINE__,(pll_out/4)/params_rate(params)); return 0; }
static int zylonite_voice_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; unsigned int pll_out = 0; unsigned int wm9713_div = 0; int ret = 0; int rate = params_rate(params); int width = snd_pcm_format_physical_width(params_format(params)); /* Only support ratios that we can generate neatly from the AC97 * based master clock - in particular, this excludes 44.1kHz. * In most applications the voice DAC will be used for telephony * data so multiples of 8kHz will be the common case. */ switch (rate) { case 8000: wm9713_div = 12; break; case 16000: wm9713_div = 6; break; case 48000: wm9713_div = 2; break; default: /* Don't support OSS emulation */ return -EINVAL; } /* Add 1 to the width for the leading clock cycle */ pll_out = rate * (width + 1) * 8; ret = snd_soc_dai_set_sysclk(cpu_dai, PXA_SSP_CLK_AUDIO, 0, 1); if (ret < 0) return ret; ret = snd_soc_dai_set_pll(cpu_dai, 0, 0, 0, pll_out); if (ret < 0) return ret; if (clk_pout) ret = snd_soc_dai_set_clkdiv(codec_dai, WM9713_PCMCLK_PLL_DIV, WM9713_PCMDIV(wm9713_div)); else ret = snd_soc_dai_set_clkdiv(codec_dai, WM9713_PCMCLK_DIV, WM9713_PCMDIV(wm9713_div)); if (ret < 0) return ret; return 0; }
static int h1940_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; int div; int ret; unsigned int rate = params_rate(params); switch (rate) { case 11025: case 22050: case 44100: div = s3c24xx_i2s_get_clockrate() / (384 * rate); if (s3c24xx_i2s_get_clockrate() % (384 * rate) > (192 * rate)) div++; break; default: dev_err(rtd->dev, "%s: rate %d is not supported\n", __func__, rate); return -EINVAL; } /* select clock source */ ret = snd_soc_dai_set_sysclk(cpu_dai, S3C24XX_CLKSRC_PCLK, rate, SND_SOC_CLOCK_OUT); if (ret < 0) return ret; /* set MCLK division for sample rate */ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C24XX_DIV_MCLK, S3C2410_IISMOD_384FS); if (ret < 0) return ret; /* set BCLK division for sample rate */ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C24XX_DIV_BCLK, S3C2410_IISMOD_32FS); if (ret < 0) return ret; /* set prescaler division for sample rate */ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER, S3C24XX_PRESCALE(div, div)); if (ret < 0) return ret; return 0; }
static int smdk64xx_wm8580_init_paiftx(struct snd_soc_codec *codec) { int ret; /* Add smdk64xx specific Capture widgets */ snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets_cpt, ARRAY_SIZE(wm8580_dapm_widgets_cpt)); /* Set up PAIFTX audio path */ snd_soc_dapm_add_routes(codec, audio_map_tx, ARRAY_SIZE(audio_map_tx)); /* Enabling the microphone requires the fitting of a 0R * resistor to connect the line from the microphone jack. */ snd_soc_dapm_disable_pin(codec, "MicIn"); /* signal a DAPM event */ snd_soc_dapm_sync(codec); /* Set the Codec DAI configuration */ #if 0 ret = snd_soc_dai_set_fmt(&wm8580_dai[WM8580_DAI_PAIFTX], SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); if (ret < 0) return ret; #endif /* Set the AP DAI configuration */ ret = snd_soc_dai_set_fmt(&s3c64xx_i2s_dai[I2S_NUM], SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); if (ret < 0) return ret; /* Set WM8580 to drive MCLK from its PLLA */ ret = snd_soc_dai_set_clkdiv(&wm8580_dai[WM8580_DAI_PAIFTX], WM8580_MCLK, WM8580_CLKSRC_PLLA); if (ret < 0) return ret; /* Explicitly set WM8580-ADC to source from MCLK */ ret = snd_soc_dai_set_clkdiv(&wm8580_dai[WM8580_DAI_PAIFTX], WM8580_ADC_CLKSEL, WM8580_CLKSRC_MCLK); if (ret < 0) return ret; return 0; }
static int omap3pandora_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; int ret; /* Set the codec system clock for DAC and ADC */ ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000, SND_SOC_CLOCK_IN); if (ret < 0) { pr_err(PREFIX "can't set codec system clock\n"); return ret; } /* Set McBSP clock to external */ ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_SYSCLK_CLKS_EXT, 256 * params_rate(params), SND_SOC_CLOCK_IN); if (ret < 0) { pr_err(PREFIX "can't set cpu system clock\n"); return ret; } ret = snd_soc_dai_set_clkdiv(cpu_dai, OMAP_MCBSP_CLKGDV, 8); if (ret < 0) { pr_err(PREFIX "can't set SRG clock divider\n"); return ret; } return 0; }
static int playpaq_wm8510_init(struct snd_soc_codec *codec) { int i; /* * Add DAPM widgets */ for (i = 0; i < ARRAY_SIZE(playpaq_dapm_widgets); i++) snd_soc_dapm_new_control(codec, &playpaq_dapm_widgets[i]); /* * Setup audio path interconnects */ for (i = 0; intercon[i][0] != NULL; i++) { snd_soc_dapm_connect_input(codec, intercon[i][0], intercon[i][1], intercon[i][2]); } /* always connected pins */ snd_soc_dapm_enable_pin(codec, "Int Mic"); snd_soc_dapm_enable_pin(codec, "Ext Spk"); snd_soc_dapm_sync(codec); /* Make CSB show PLL rate */ snd_soc_dai_set_clkdiv(codec->dai, WM8510_OPCLKDIV, WM8510_OPCLKDIV_1 | 4); return 0; }
//set mclk and bclk division static int sun7i_sndpcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { int ret = 0; u32 freq = 22579200; struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; unsigned long sample_rate = params_rate(params); switch (sample_rate) { case 8000: case 16000: case 32000: case 64000: case 128000: case 12000: case 24000: case 48000: case 96000: case 192000: freq = 24576000; break; } ret = snd_soc_dai_set_sysclk(cpu_dai, 0 , freq, i2s_pcm_select); if (ret < 0) { return ret; } ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBM_CFM); if (ret < 0) return ret; /* * codec clk & FRM master. AP as slave */ ret = snd_soc_dai_set_fmt(cpu_dai, (audio_format | (signal_inversion<<8) | (pcm_master<<12))); if (ret < 0) { return ret; } ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, sample_rate); if (ret < 0) { return ret; } /* * audio_format == SND_SOC_DAIFMT_DSP_A * signal_inversion<<8 == SND_SOC_DAIFMT_IB_NF * i2s_master<<12 == SND_SOC_DAIFMT_CBM_CFM */ I2S_DBG("%s,line:%d,audio_format:%d,SND_SOC_DAIFMT_DSP_A:%d\n",\ __func__, __LINE__, audio_format, SND_SOC_DAIFMT_DSP_A); I2S_DBG("%s,line:%d,signal_inversion:%d,signal_inversion<<8:%d,SND_SOC_DAIFMT_IB_NF:%d\n",\ __func__, __LINE__, signal_inversion, signal_inversion<<8, SND_SOC_DAIFMT_IB_NF); I2S_DBG("%s,line:%d,i2s_master:%d,i2s_master<<12:%d,SND_SOC_DAIFMT_CBM_CFM:%d\n",\ __func__, __LINE__, pcm_master, pcm_master<<12, SND_SOC_DAIFMT_CBM_CFM); return 0; }
static int sdp4430_dmic_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; int ret = 0; ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_DMIC_SYSCLK_PAD_CLKS, 19200000, SND_SOC_CLOCK_IN); if (ret < 0) { printk(KERN_ERR "can't set DMIC cpu system clock\n"); return ret; } ret = snd_soc_dai_set_clkdiv(cpu_dai, OMAP_DMIC_CLKDIV, 8); if (ret < 0) { printk(KERN_ERR "can't set DMIC cpu clock divider\n"); return ret; } if (rtd->current_fe == ABE_FRONTEND_DAI_MODEM) { /* set Modem McBSP configuration */ ret = sdp4430_modem_mcbsp_configure(substream, params, 1); } return ret; }
static int playpaq_wm8510_init(struct snd_soc_pcm_runtime *rtd) { struct snd_soc_codec *codec = rtd->codec; struct snd_soc_dapm_context *dapm = &codec->dapm; int i; /* * Add DAPM widgets */ for (i = 0; i < ARRAY_SIZE(playpaq_dapm_widgets); i++) snd_soc_dapm_new_control(dapm, &playpaq_dapm_widgets[i]); /* * Setup audio path interconnects */ snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); /* always connected pins */ snd_soc_dapm_enable_pin(dapm, "Int Mic"); snd_soc_dapm_enable_pin(dapm, "Ext Spk"); snd_soc_dapm_sync(dapm); /* Make CSB show PLL rate */ snd_soc_dai_set_clkdiv(rtd->codec_dai, WM8510_OPCLKDIV, WM8510_OPCLKDIV_1 | 4); return 0; }
static int sunxi_snddaudio_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { int ret = 0; u32 freq_in = 24000000; u32 freq_out = 22579200; struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; int sample_rate = params_rate(params); switch (sample_rate) { case 8000: case 16000: case 32000: case 64000: case 128000: case 12000: case 24000: case 48000: case 96000: case 192000: freq_out = 24576000; break; } pr_debug("%s,line:%d,freq_in:%d,daudio_pcm_select:%d,audio_format:%d,signal_inversion:%d\n",__func__,__LINE__, freq_in,daudio_pcm_select,audio_format,signal_inversion); /* set the codec FLL */ ret = snd_soc_dai_set_pll(codec_dai, AC100_MCLK1, 0, freq_in, freq_out); if (ret < 0) { return ret; } /*set cpu_dai clk*/ ret = snd_soc_dai_set_sysclk(cpu_dai, 0 , freq_out, daudio_pcm_select); if (ret < 0) { return ret; } /*set codec_dai clk*/ ret = snd_soc_dai_set_sysclk(codec_dai, AIF1_CLK , freq_out, daudio_pcm_select); if (ret < 0) { return ret; } /* * ac100: master. AP: slave */ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); if (ret < 0) { return ret; } ret = snd_soc_dai_set_fmt(cpu_dai, (audio_format | (signal_inversion<<8) | SND_SOC_DAIFMT_CBM_CFM)); if (ret < 0) { return ret; } ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, sample_rate); if (ret < 0) { return ret; } return 0; }
static int adonisuniv_hifi_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; struct snd_soc_dai *codec_dai = rtd->codec_dai; int ret; /* Set the codec DAI configuration */ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); if (ret < 0) return ret; /* Set the cpu DAI configuration */ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(codec_dai, MC_ASOC_BCLK_MULT, MC_ASOC_LRCK_X32); if (ret < 0) return ret; return 0; }
static int init_link(int dai) { struct snd_soc_dai_link *dl = &smdks5p_dai[dai]; struct snd_soc_dai *cpu_dai = dl->cpu_dai; struct snd_soc_dai *codec_dai = dl->codec_dai; int ret; if (dai == DAI_I2S_PBK) ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_DAC_CLKSEL, WM8580_CLKSRC_MCLK); /* Fig-26 Pg-43 */ else ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_ADC_CLKSEL, WM8580_CLKSRC_MCLK); /* Fig-26 Pg-43 */ if (ret < 0) return ret; return 0; }
static int smdk64xx_wm8580_init_paifrx(struct snd_soc_codec *codec) { int ret; /* Add smdk64xx specific Playback widgets */ snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets_pbk, ARRAY_SIZE(wm8580_dapm_widgets_pbk)); /* add iDMA controls */ ret = snd_soc_add_controls(codec, &s5p_idma_control, 1); if (ret < 0) return ret; /* Set up PAIFRX audio path */ snd_soc_dapm_add_routes(codec, audio_map_rx, ARRAY_SIZE(audio_map_rx)); /* signal a DAPM event */ snd_soc_dapm_sync(codec); /* Set the Codec DAI configuration */ ret = snd_soc_dai_set_fmt(&wm8580_dai[WM8580_DAI_PAIFRX], SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); if (ret < 0) return ret; /* Set the AP DAI configuration */ ret = snd_soc_dai_set_fmt(&s3c64xx_i2s_dai[I2S_NUM], SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); if (ret < 0) return ret; /* Set WM8580 to drive MCLK from its PLLA */ ret = snd_soc_dai_set_clkdiv(&wm8580_dai[WM8580_DAI_PAIFRX], WM8580_MCLK, WM8580_CLKSRC_PLLA); if (ret < 0) return ret; /* Explicitly set WM8580-DAC to source from MCLK */ ret = snd_soc_dai_set_clkdiv(&wm8580_dai[WM8580_DAI_PAIFRX], WM8580_DAC_CLKSEL, WM8580_CLKSRC_MCLK); if (ret < 0) return ret; return 0; }
static int map_fe_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; u32 freq_in, freq_out, sspa_mclk, sysclk, sspa_div; u32 srate = params_rate(params); codec_dai->stream = substream->stream; cpu_dai->stream = substream->stream; freq_in = 26000000; if (params_rate(params) > 11025) { freq_out = params_rate(params) * 512; sysclk = 11289600; sspa_mclk = params_rate(params) * 64; } else { freq_out = params_rate(params) * 1024; sysclk = 11289600; sspa_mclk = params_rate(params) * 64; } sspa_div = freq_out; do_div(sspa_div, sspa_mclk); #if 1 /* For i2s2(voice call) and i2s3(bt-audio), the dai format is pcm */ if (codec_dai->id == 2) { snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); } else if (codec_dai->id == 5) { snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_NB_IF | SND_SOC_DAIFMT_CBM_CFM); snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_NB_IF | SND_SOC_DAIFMT_CBM_CFM); } else { snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_IF | SND_SOC_DAIFMT_CBM_CFM); snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_IF | SND_SOC_DAIFMT_CBM_CFM); } #else snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); #endif /* SSPA clock ctrl register changes, and can't use previous API */ snd_soc_dai_set_sysclk(cpu_dai, AUDIO_PLL, freq_out, 0); snd_soc_dai_set_clkdiv(cpu_dai, 0, 0); /* set i2s1/2/3/4 sysclk */ snd_soc_dai_set_sysclk(codec_dai, APLL_32K, srate, 0); return 0; }
static int sdp4430_mcbsp_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; int ret = 0, channels = 0; unsigned int be_id, fmt; be_id = rtd->dai_link->be_id; if (be_id == OMAP_ABE_DAI_BT_VX) { if (machine_is_tuna()) fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM; else fmt = SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_NB_IF | SND_SOC_DAIFMT_CBM_CFM; } else { fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM; } ret = snd_soc_dai_set_fmt(cpu_dai, fmt); if (ret < 0) { printk(KERN_ERR "can't set cpu DAI configuration\n"); return ret; } /* * TODO: where does this clock come from (external source??) - * do we need to enable it. */ /* Set McBSP clock to external */ ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_SYSCLK_CLKS_FCLK, 32 * 96 * params_rate(params), SND_SOC_CLOCK_IN); if (ret < 0) printk(KERN_ERR "can't set cpu system clock\n"); ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, 96); if (ret < 0) printk(KERN_ERR "can't set McBSP cpu DAI clkdiv\n"); /* * Configure McBSP internal buffer threshold * for playback/record */ channels = params_channels(params); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) omap_mcbsp_set_tx_threshold(cpu_dai->id, channels); else omap_mcbsp_set_rx_threshold(cpu_dai->id, channels); return ret; }
static int smdk_wm8994_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; unsigned long mclk_freq; int rfs, ret; switch(params_rate(params)) { case 8000: rfs = 512; break; default: dev_err(cpu_dai->dev, "%s:%d Sampling Rate %u not supported!\n", __func__, __LINE__, params_rate(params)); return -EINVAL; } mclk_freq = params_rate(params) * rfs; /* */ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBS_CFS); if (ret < 0) return ret; /* */ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBS_CFS); if (ret < 0) return ret; ret = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_FLL1, mclk_freq, SND_SOC_CLOCK_IN); if (ret < 0) return ret; ret = snd_soc_dai_set_pll(codec_dai, WM8994_FLL1, WM8994_FLL_SRC_MCLK1, SMDK_WM8994_FREQ, mclk_freq); if (ret < 0) return ret; /* */ ret = snd_soc_dai_set_sysclk(cpu_dai, S3C_PCM_CLKSRC_MUX, mclk_freq, SND_SOC_CLOCK_IN); if (ret < 0) return ret; /* */ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_PCM_SCLK_PER_FS, rfs); if (ret < 0) return ret; return 0; }
static int daudio0_set_clk(void) { int ret = 0; u32 freq = 22579200; unsigned int pll_out = 11289600; struct snd_soc_pcm_runtime *rtd = runtime; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; unsigned long sample_rate = 44100; switch (sample_rate) { case 8000: case 16000: case 32000: case 64000: case 128000: case 12000: case 24000: case 48000: case 96000: case 192000: freq = 24576000; pll_out = 12288000; break; } /*set system clock source freq and set the mode as daudio or pcm*/ ret = snd_soc_dai_set_sysclk(cpu_dai, 0 , freq, daudio_pcm_select); if (ret < 0) { return ret; } ret = codec_dai->driver->ops->set_sysclk(codec_dai, 0, pll_out, SND_SOC_CLOCK_IN); if (ret < 0) return ret; ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); if (ret < 0) { pr_err("%s, line:%d\n", __func__, __LINE__); return ret; } /* * codec clk & FRM master. AP as slave */ ret = snd_soc_dai_set_fmt(cpu_dai, (audio_format | (signal_inversion<<8) | (daudio_master<<12))); if (ret < 0) { return ret; } ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, sample_rate); if (ret < 0) { return ret; } return 0; }
static int mehmet_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; unsigned long epll_out_rate; int rfs, ret; switch (params_rate(params)) { case 8000: case 16000: epll_out_rate = 49152000; break; default: printk(KERN_ERR "%s:%d Sampling Rate %u not supported!\n", __func__, __LINE__, params_rate(params)); return -EINVAL; } switch (params_rate(params)) { case 16000: rfs = 128; break; case 8000: rfs = 256; break; break; default: printk(KERN_ERR "%s:%d Sampling Rate %u not supported!\n", __func__, __LINE__, params_rate(params)); return -EINVAL; } /* Set the cpu DAI configuration */ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBS_CFS); if (ret < 0) return ret; /* Set EPLL clock rate */ ret = set_epll_rate(epll_out_rate); if (ret < 0) return ret; /* 8kHz * 256(16bits * 16slots, frame sync) = 2048kHz Clock Out */ ret = snd_soc_dai_set_sysclk(cpu_dai, S3C_PCM_CLKSRC_MUX, params_rate(params)*rfs, SND_SOC_CLOCK_OUT); /* Set SCLK_DIV for making bclk */ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_PCM_SCLK_PER_FS, rfs); if (ret < 0) return ret; return 0; }
static int sun6i_sndspdif_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; int ret = 0; unsigned long rate = params_rate(params); unsigned int fmt = 0; u32 mclk_div=0, mpll=0, bclk_div=0, mult_fs=0; get_clock_divder(rate, 32, &mclk_div, &mpll, &bclk_div, &mult_fs); if (ret < 0) return ret; /*add the pcm and raw data select interface*/ switch(params_channels(params)) { case 1:/*pcm mode*/ case 2: fmt = 0; break; case 4:/*raw data mode*/ fmt = 1; break; default: return -EINVAL; } ret = snd_soc_dai_set_fmt(cpu_dai, fmt);//0:pcm,1:raw data if (ret < 0) return ret; ret = snd_soc_dai_set_sysclk(cpu_dai, 0 , mpll, 0); if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(cpu_dai, SUN6I_DIV_MCLK, mclk_div); if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(cpu_dai, SUN6I_DIV_BCLK, bclk_div); if (ret < 0) return ret; return 0; }
static int sun5i_sndi2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; int ret = 0; unsigned long rate = params_rate(params); u32 mclk_div=0, mpll=0, bclk_div=0, mult_fs=0; get_clock_divder(rate, 32, &mclk_div, &mpll, &bclk_div, &mult_fs); ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); if (ret < 0) return ret; ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); if (ret < 0) return ret; ret = snd_soc_dai_set_sysclk(cpu_dai, 0 , mpll, 0); if (ret < 0) return ret; ret = snd_soc_dai_set_sysclk(codec_dai, 0 , mpll, 0); if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(cpu_dai, SUN5I_DIV_MCLK, mclk_div); if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(cpu_dai, SUN5I_DIV_BCLK, bclk_div); if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(codec_dai, 0, mult_fs); if (ret < 0) return ret; return 0; }
static int mapasoc_fe_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; int freq_in, freq_out, sspa_mclk, sysclk, sspa_div; freq_in = 26000000; if (params_rate(params) > 11025) { freq_out = params_rate(params) * 512; sysclk = 11289600; sspa_mclk = params_rate(params) * 64; } else { freq_out = params_rate(params) * 1024; sysclk = 11289600; sspa_mclk = params_rate(params) * 64; } sspa_div = freq_out; do_div(sspa_div, sspa_mclk); #if 1 snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); #else snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); #endif /* SSPA clock ctrl register changes, and can't use previous API */ snd_soc_dai_set_sysclk(cpu_dai, AUDIO_PLL, freq_out, 0); snd_soc_dai_set_clkdiv(cpu_dai, 0, 0); /* set i2s1/2/3/4 sysclk */ snd_soc_dai_set_sysclk(codec_dai, AUDIO_PLL, freq_out, 0); /* set the interface to 44.1k sample rate */ snd_soc_dai_set_clkdiv(codec_dai, 0, 0x13721fbd); return 0; }
/** * simtec_hw_params - update hardware parameters * @substream: The audio substream instance. * @params: The parameters requested. * * Update the codec data routing and configuration settings * from the supplied data. */ static int simtec_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; int ret; /* Set the CODEC as the bus clock master, I2S */ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); if (ret) { pr_err("%s: failed set cpu dai format\n", __func__); return ret; } /* Set the CODEC as the bus clock master */ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); if (ret) { pr_err("%s: failed set codec dai format\n", __func__); return ret; } ret = snd_soc_dai_set_sysclk(codec_dai, 0, CODEC_CLOCK, SND_SOC_CLOCK_IN); if (ret) { pr_err( "%s: failed setting codec sysclk\n", __func__); return ret; } if (pdata->use_mpllin) { ret = snd_soc_dai_set_sysclk(cpu_dai, S3C24XX_CLKSRC_MPLL, 0, SND_SOC_CLOCK_OUT); if (ret) { pr_err("%s: failed to set MPLLin as clksrc\n", __func__); return ret; } } if (pdata->output_cdclk) { int cdclk_scale; cdclk_scale = clk_get_rate(xtal_clk) / CODEC_CLOCK; cdclk_scale--; ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER, cdclk_scale); } return 0; }