/**
* \brief Initialize USART in RS232 mode.
*
* This function initializes the USART module in RS232 mode using the
* usart_rs232_options_t configuration structure and CPU frequency.
*
* \param usart The USART module.
* \param opt The RS232 configuration option.
*/
void usart_init_rs232(USART_t *usart, const usart_rs232_options_t *opt)
{
usart_enable_module_clock(usart);
usart_set_mode(usart, USART_CMODE_ASYNCHRONOUS_gc);
usart_format_set(usart, opt->charlength, opt->paritytype,
opt->stopbits);
usart_set_baudrate(usart, opt->baudrate, sysclk_get_per_hz());
usart_tx_enable(usart);
usart_rx_enable(usart);
}
/**
* \brief Initialize USART in RS232 mode.
*
* This function initializes the USART module in RS232 mode using the
* usart_rs232_options_t configuration structure and CPU frequency.
*
* \param usart The USART module.
* \param opt The RS232 configuration option.
*
* \retval true if the initialization was successfull
* \retval false if the initialization failed (error in baud rate calculation)
*/
bool usart_init_rs232(USART_t *usart, const usart_rs232_options_t *opt)
{
bool result;
sysclk_enable_peripheral_clock(usart);
usart_set_mode(usart, USART_CMODE_ASYNCHRONOUS_gc);
usart_format_set(usart, opt->charlength, opt->paritytype,
opt->stopbits);
result = usart_set_baudrate(usart, opt->baudrate, sysclk_get_per_hz());
usart_tx_enable(usart);
usart_rx_enable(usart);
return result;
}
int main(void)
{
struct dac_config conf;
uint8_t i = 0;
board_init();
sysclk_init();
// Initialize the dac configuration.
dac_read_configuration(&SPEAKER_DAC, &conf);
/* Create configuration:
* - 1V from bandgap as reference, left adjusted channel value
* - one active DAC channel, no internal output
* - conversions triggered by event channel 0
* - 1 us conversion intervals
*/
dac_set_conversion_parameters(&conf, DAC_REF_BANDGAP, DAC_ADJ_LEFT);
dac_set_active_channel(&conf, SPEAKER_DAC_CHANNEL, 0);
dac_set_conversion_trigger(&conf, SPEAKER_DAC_CHANNEL, 0);
#if XMEGA_DAC_VERSION_1
dac_set_conversion_interval(&conf, 1);
#endif
dac_write_configuration(&SPEAKER_DAC, &conf);
dac_enable(&SPEAKER_DAC);
#if XMEGA_E
// Configure timer/counter to generate events at sample rate.
sysclk_enable_module(SYSCLK_PORT_C, SYSCLK_TC4);
TCC4.PER = (sysclk_get_per_hz() / RATE_OF_CONVERSION) - 1;
// Configure event channel 0 to generate events upon T/C overflow.
sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_EVSYS);
EVSYS.CH0MUX = EVSYS_CHMUX_TCC4_OVF_gc;
// Start the timer/counter.
TCC4.CTRLA = TC45_CLKSEL_DIV1_gc;
#else
// Configure timer/counter to generate events at sample rate.
sysclk_enable_module(SYSCLK_PORT_C, SYSCLK_TC0);
TCC0.PER = (sysclk_get_per_hz() / RATE_OF_CONVERSION) - 1;
// Configure event channel 0 to generate events upon T/C overflow.
sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_EVSYS);
EVSYS.CH0MUX = EVSYS_CHMUX_TCC0_OVF_gc;
// Start the timer/counter.
TCC0.CTRLA = TC_CLKSEL_DIV1_gc;
#endif
/* Write samples to the DAC channel every time it is ready for new
* data, i.e., when it is done converting. Conversions are triggered by
* the timer/counter.
*/
do {
dac_wait_for_channel_ready(&SPEAKER_DAC, SPEAKER_DAC_CHANNEL);
dac_set_channel_value(&SPEAKER_DAC, SPEAKER_DAC_CHANNEL, sine[i]);
i++;
i %= NR_OF_SAMPLES;
} while (1);
}
/**
* \brief Initialize USART in SPI master mode.
*
* This function initializes the USART module in SPI master mode using the
* usart_spi_options_t configuration structure and CPU frequency.
*
* \param usart The USART module.
* \param opt The RS232 configuration option.
*/
void usart_init_spi(USART_t *usart, const usart_spi_options_t *opt)
{
ioport_pin_t sck_pin;
bool invert_sck;
sysclk_enable_peripheral_clock(usart);
usart_rx_disable(usart);
/* configure Clock polarity using INVEN bit of the correct SCK I/O port **/
invert_sck = (opt->spimode == 2) || (opt->spimode == 3);
UNUSED(invert_sck);
#ifdef USARTC0
if ((uint16_t)usart == (uint16_t)&USARTC0) {
sck_pin = IOPORT_CREATE_PIN(PORTC, 1);
}
#endif
#ifdef USARTC1
if ((uint16_t)usart == (uint16_t)&USARTC1) {
sck_pin = IOPORT_CREATE_PIN(PORTC, 5);
}
#endif
#ifdef USARTD0
if ((uint16_t)usart == (uint16_t)&USARTD0) {
sck_pin = IOPORT_CREATE_PIN(PORTD, 1);
}
#endif
#ifdef USARTD1
if ((uint16_t)usart == (uint16_t)&USARTD1) {
sck_pin = IOPORT_CREATE_PIN(PORTD, 5);
}
#endif
#ifdef USARTE0
if ((uint16_t)usart == (uint16_t)&USARTE0) {
sck_pin = IOPORT_CREATE_PIN(PORTE, 1);
}
#endif
#ifdef USARTE1
if ((uint16_t)usart == (uint16_t)&USARTE1) {
sck_pin = IOPORT_CREATE_PIN(PORTE, 5);
}
#endif
#ifdef USARTF0
if ((uint16_t)usart == (uint16_t)&USARTF0) {
sck_pin = IOPORT_CREATE_PIN(PORTF, 1);
}
#endif
#ifdef USARTF1
if ((uint16_t)usart == (uint16_t)&USARTF1) {
sck_pin = IOPORT_CREATE_PIN(PORTF, 5);
}
#endif
/* Configure the USART output pin */
ioport_set_pin_dir(sck_pin, IOPORT_DIR_OUTPUT);
ioport_set_pin_mode(sck_pin,
IOPORT_MODE_TOTEM | (invert_sck? IOPORT_MODE_INVERT_PIN : 0));
ioport_set_pin_level(sck_pin, IOPORT_PIN_LEVEL_HIGH);
usart_set_mode(usart, USART_CMODE_MSPI_gc);
if (opt->spimode == 1 || opt->spimode == 3) {
usart->CTRLC |= USART_UCPHA_bm;
} else {
usart->CTRLC &= ~USART_UCPHA_bm;
}
if (opt->data_order) {
(usart)->CTRLC |= USART_DORD_bm;
} else {
(usart)->CTRLC &= ~USART_DORD_bm;
}
usart_spi_set_baudrate(usart, opt->baudrate, sysclk_get_per_hz());
usart_tx_enable(usart);
usart_rx_enable(usart);
}
int
owluart_init(void *uart,
uint32_t baudrate, enum uart_databits databits,
enum uart_parity parity, enum uart_stopbits stopbits,
int rtscts)
{
USART_t *port = uart;
uint8_t ctrlc = 0;
uint8_t ctrlb = 0;
uint16_t bsel;
#if BOARD == XPLAIN
/* usb-to-serial on xplain seems broken for other configurations */
if (port == &USARTC0) {
if (baudrate != 9600 ||
databits != 8 ||
stopbits != 1 ||
parity != UART_PARITY_NONE ||
rtscts)
return OWL_ERR_NOTSUPP;
}
#endif
if (rtscts)
return OWL_ERR_NOTSUPP;
switch(databits) {
case UART_DATABITS_5:
ctrlc |= USART_CHSIZE_5BIT_gc;
break;
case UART_DATABITS_6:
ctrlc |= USART_CHSIZE_6BIT_gc;
break;
case UART_DATABITS_7:
ctrlc |= USART_CHSIZE_7BIT_gc;
break;
case UART_DATABITS_8:
ctrlc |= USART_CHSIZE_8BIT_gc;
break;
case UART_DATABITS_9:
ctrlc |= USART_CHSIZE_9BIT_gc;
break;
};
switch (parity) {
case UART_PARITY_NONE:
ctrlc |= USART_PMODE_DISABLED_gc;
break;
case UART_PARITY_EVEN:
ctrlc |= USART_PMODE_EVEN_gc;
break;
case UART_PARITY_ODD:
ctrlc |= USART_PMODE_ODD_gc;
break;
default:
return OWL_ERR_NOTSUPP;
}
switch (stopbits) {
case UART_STOPBITS_1:
break;
case UART_STOPBITS_2:
ctrlc |= USART_SBMODE_bm;
break;
};
ctrlb = USART_TXEN_bm | USART_RXEN_bm;
if (sysclk_get_per_hz() < (16UL * baudrate)) {
/* need double transmission speed */
ctrlb |= USART_CLK2X_bm;
bsel = sysclk_get_per_hz() / (16UL * baudrate) - 1;
} else {
bsel = sysclk_get_per_hz() / (16UL * baudrate) - 1;
}
port->CTRLB = 0; /* disable transceiver while confiuring */
port->CTRLC = ctrlc;
port->BAUDCTRLA = bsel & 0xff;
port->BAUDCTRLB = bsel >> 8;
port->CTRLB = ctrlb;
return 0;
}
static void qdec_enabled_evsys(qdec_config_t *config)
{
volatile uint8_t *evsys_chctrl;
uint32_t nb_filter_cycle;
/* Configure event channel for quadrature decoding of pins */
sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_EVSYS);
/* Initialize CHMUX register */
qdec_evsys_pin_2_chmux(config->port, config->pins_base,
config->event_channel);
/* In event channel enable Quadrature Decode with digital
* filter and Rotary filter
* (Rotary filter is only for XMEGA-E devices)
*/
evsys_chctrl = &EVSYS.CH0CTRL + config->event_channel;
if (config->pins_filter_us > 1000) {
nb_filter_cycle = (config->pins_filter_us / 1000)
* (sysclk_get_per_hz() / 1000);
} else {
nb_filter_cycle = config->pins_filter_us
* (sysclk_get_per_hz() / 1000000);
}
#if XMEGA_E
if (nb_filter_cycle > 7) {
/* Compute prescaler need */
uint8_t presc;
for (presc = 0; presc < 4; presc++) {
nb_filter_cycle /= 8;
if (nb_filter_cycle < 8) {
break;
}
}
if (nb_filter_cycle > 7) {
nb_filter_cycle = 7;
}
/* Enable prescaler of filter */
EVSYS.DFCTRL = EVSYS_PRESCFILT_CH04_gc
| (config->index.enabled ? EVSYS_PRESCFILT_CH15_gc : 0)
| presc;
}
*evsys_chctrl = EVSYS_QDEN_bm | nb_filter_cycle
| (config->rotary ? EVSYS_ROTARY_bm : 0);
#else
if (nb_filter_cycle > 7) {
nb_filter_cycle = 7;
}
*evsys_chctrl = EVSYS_QDEN_bm | nb_filter_cycle;
#endif
if (config->index.enabled) {
/* Configure event channel as index channel. When
* enabling index,in event channel n,event channel n+1
* should be used for index signal.
* And port pin-n+2 should be used for index
* signal input
*/
/* Enable quadrature decode index for event channel-0 */
*evsys_chctrl |= ((uint8_t)config->index.rec_state
<< EVSYS_QDIRM_gp)
| EVSYS_QDIEN_bm;
/* Initialize CHMUX register */
qdec_evsys_pin_2_chmux(config->port, config->pins_base + 2,
config->event_channel + 1);
/* Enable digital filter*/
evsys_chctrl++;
*evsys_chctrl = nb_filter_cycle;
}
}
/**
* \brief Initialize USART in SPI master mode.
*
* This function initializes the USART module in SPI master mode using the
* usart_spi_options_t configuration structure and CPU frequency.
*
* \param usart The USART module.
* \param opt The RS232 configuration option.
*/
void usart_init_spi(USART_t *usart, const usart_spi_options_t *opt)
{
usart_enable_module_clock(usart);
usart_set_mode(usart, USART_CMODE_MSPI_gc);
port_pin_t sck_pin;
if (opt->spimode == 1 || opt->spimode == 3) {
//! \todo Fix when UCPHA_bm is added to header file.
usart->CTRLC |= 0x02;
} else {
//! \todo Fix when UCPHA_bm is added to header file.
usart->CTRLC &= ~0x02;
}
// configure Clock polarity using INVEN bit of the correct SCK I/O port
if (opt->spimode == 2 || opt->spimode == 3) {
#ifdef USARTC0
if ((uint16_t)usart == (uint16_t)&USARTC0) {
sck_pin = IOPORT_CREATE_PIN(PORTC, 1);
ioport_configure_port_pin(ioport_pin_to_port(sck_pin),
ioport_pin_to_mask(sck_pin),
IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED);
}
#endif
#ifdef USARTC1
if ((uint16_t)usart == (uint16_t)&USARTC1) {
sck_pin = IOPORT_CREATE_PIN(PORTC, 5);
ioport_configure_port_pin(ioport_pin_to_port(sck_pin),
ioport_pin_to_mask(sck_pin),
IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED);
}
#endif
#ifdef USARTD0
if ((uint16_t)usart == (uint16_t)&USARTD0) {
sck_pin = IOPORT_CREATE_PIN(PORTD, 1);
ioport_configure_port_pin(ioport_pin_to_port(sck_pin),
ioport_pin_to_mask(sck_pin),
IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED);
}
#endif
#ifdef USARTD1
if ((uint16_t)usart == (uint16_t)&USARTD1) {
sck_pin = IOPORT_CREATE_PIN(PORTD, 5);
ioport_configure_port_pin(ioport_pin_to_port(sck_pin),
ioport_pin_to_mask(sck_pin),
IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED);
}
#endif
#ifdef USARTE0
if ((uint16_t)usart == (uint16_t)&USARTE0) {
sck_pin = IOPORT_CREATE_PIN(PORTE, 1);
ioport_configure_port_pin(ioport_pin_to_port(sck_pin),
ioport_pin_to_mask(sck_pin),
IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED);
}
#endif
#ifdef USARTE1
if ((uint16_t)usart == (uint16_t)&USARTE1) {
sck_pin = IOPORT_CREATE_PIN(PORTE, 5);
ioport_configure_port_pin(ioport_pin_to_port(sck_pin),
ioport_pin_to_mask(sck_pin),
IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED);
}
#endif
#ifdef USARTF0
if ((uint16_t)usart == (uint16_t)&USARTF0) {
sck_pin = IOPORT_CREATE_PIN(PORTF, 1);
ioport_configure_port_pin(ioport_pin_to_port(sck_pin),
ioport_pin_to_mask(sck_pin),
IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED);
}
#endif
#ifdef USARTF1
if ((uint16_t)usart == (uint16_t)&USARTF1) {
sck_pin = IOPORT_CREATE_PIN(PORTF, 5);
ioport_configure_port_pin(ioport_pin_to_port(sck_pin),
ioport_pin_to_mask(sck_pin),
IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED);
}
#endif
}
usart_spi_set_baudrate(usart, opt->baudrate, sysclk_get_per_hz());
usart_tx_enable(usart);
usart_rx_enable(usart);
}
int main(void)
{
struct dac_config conf;
board_init();
sysclk_init();
// Initialize the dac configuration.
dac_read_configuration(&OUTPUT_DAC, &conf);
/* Create configuration:
* - AVCC as reference, right adjusted channel value
* - both DAC channels active, no internal output
* - manually triggered conversions on both channels
* - 2 us conversion intervals
* - 10 us refresh intervals
*/
dac_set_conversion_parameters(&conf, DAC_REF_AVCC, DAC_ADJ_RIGHT);
dac_set_active_channel(&conf, DAC_CH0 | DAC_CH1, 0);
dac_set_conversion_trigger(&conf, 0, 0);
#if XMEGA_DAC_VERSION_1
dac_set_conversion_interval(&conf, 10);
dac_set_refresh_interval(&conf, 20);
#endif
dac_write_configuration(&OUTPUT_DAC, &conf);
dac_enable(&OUTPUT_DAC);
dac_wait_for_channel_ready(&OUTPUT_DAC, DAC_CH0 | DAC_CH1);
dac_set_channel_value(&OUTPUT_DAC, DAC_CH0, 0);
dac_set_channel_value(&OUTPUT_DAC, DAC_CH1, 0);
dac_wait_for_channel_ready(&OUTPUT_DAC, DAC_CH0 | DAC_CH1);
#if !XMEGA_E
// Configure timer/counter to generate events at conversion rate.
sysclk_enable_module(SYSCLK_PORT_C, SYSCLK_TC0);
TCC0.PER = (sysclk_get_per_hz() / RATE_OF_CONVERSION) - 1;
// Configure event channel 0 to generate events upon T/C overflow.
sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_EVSYS);
EVSYS.CH0MUX = EVSYS_CHMUX_TCC0_OVF_gc;
// Start the timer/counter.
TCC0.CTRLA = TC_CLKSEL_DIV1_gc;
#else
// Configure timer/counter to generate events at conversion rate.
sysclk_enable_module(SYSCLK_PORT_C, SYSCLK_TC4);
TCC4.PER = (sysclk_get_per_hz() / RATE_OF_CONVERSION) - 1;
// Configure event channel 0 to generate events upon T/C overflow.
sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_EVSYS);
EVSYS.CH0MUX = EVSYS_CHMUX_TCC4_OVF_gc;
// Start the timer/counter.
TCC4.CTRLA = TC45_CLKSEL_DIV1_gc;
#endif
/* Write samples to the DAC channel every time it is ready.
* Conversions are triggered by the timer/counter.
*/
do {
/* Wait for channels to get ready for new values, then set the
* value of one to 10% and the other to 90% of maximum.
*/
wait_for_timer();
dac_set_channel_value(&OUTPUT_DAC, DAC_CH0, 410);
dac_set_channel_value(&OUTPUT_DAC, DAC_CH1, 3686);
wait_for_timer();
dac_set_channel_value(&OUTPUT_DAC, DAC_CH0, 3686);
dac_set_channel_value(&OUTPUT_DAC, DAC_CH1, 410);
} while (1);
}