int16_t test_vduph_lane_s16(int16x4_t src) { return vduph_lane_s16(src, 2); // CHECK-LABEL: @test_vduph_lane_s16 // CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %src to [[TYPE:.*]] // CHECK: [[TMP2:%.*]] = bitcast [[TYPE]] [[TMP1]] to <4 x i16> // CHECK: extractelement <4 x i16> [[TMP2]], i32 2 // CHECK-BE-LABEL: @test_vduph_lane_s16 // CHECK-BE: [[REV:%.*]] = shufflevector <4 x i16> {{.*}}, <4 x i32> <i32 3, i32 2, i32 1, i32 0> // CHECK-BE: [[TMP1:%.*]] = bitcast <4 x i16> [[REV]] to [[TYPE:.*]] // CHECK-BE: [[TMP2:%.*]] = bitcast [[TYPE]] [[TMP1]] to <4 x i16> // CHECK-BE: extractelement <4 x i16> [[TMP2]], i32 2 }
wrap_vduph_lane_s16_1 (int16x4_t a) { int16_t result = vduph_lane_s16 (a, 1); force_simd (result); return result; }
wrap_vduph_lane_s16_0 (int16x4_t dummy, int16x4_t a) { int16_t result = vduph_lane_s16 (a, 0); force_simd (result); return result; }
// CHECK-LABEL: @test_vduph_lane_s16 int16_t test_vduph_lane_s16(int16x4_t src) { return vduph_lane_s16(src, 2); // CHECK: extractelement <4 x i16> %src, i32 2 // CHECK-BE: extractelement <4 x i16> %src, i32 1 }
// CHECK-LABEL: test_vduph_lane_s16 int16_t test_vduph_lane_s16(int16x4_t a) { return vduph_lane_s16(a, 3); // CHECK: {{umov|smov}} {{w[0-9]+}}, {{v[0-9]+}}.h[3] }
// CHECK-LABEL: define i16 @test_vduph_lane_s16(<4 x i16> %a) #0 { // CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> // CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[TMP1]], i32 3 // CHECK: ret i16 [[VGET_LANE]] int16_t test_vduph_lane_s16(int16x4_t a) { return vduph_lane_s16(a, 3); }
int16x1_t test_vduph_lane_s16 (int16x8_t a) { return vduph_lane_s16 (a, 2); }