void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) { used = RegsAvailable; used.flip(); if (includeReserved) used |= MRI->getReservedRegs(); else used.reset(MRI->getReservedRegs()); }
void RegDefsUses::setUnallocatableRegs(const MachineFunction &MF) { BitVector AllocSet = TRI.getAllocatableSet(MF); for (int R = AllocSet.find_first(); R != -1; R = AllocSet.find_next(R)) for (MCRegAliasIterator AI(R, &TRI, false); AI.isValid(); ++AI) AllocSet.set(*AI); AllocSet.set(Mips::ZERO); AllocSet.set(Mips::ZERO_64); Defs |= AllocSet.flip(); }
static std::vector<InstructionTemplate> generateSnippetUsingStaticRenaming( const LLVMState &State, const InstructionTemplate &IT, const ArrayRef<const Variable *> TiedVariables, const BitVector *ScratchSpaceAliasedRegs) { std::vector<InstructionTemplate> Instructions; // Assign registers to variables in a round-robin manner. This is simple but // ensures that the most register-constrained variable does not get starved. std::vector<BitVector> PossibleRegsForVar; for (const Variable *Var : TiedVariables) { assert(Var); const Operand &Op = IT.Instr.getPrimaryOperand(*Var); assert(Op.isReg()); BitVector PossibleRegs = State.getRATC().emptyRegisters(); if (ScratchSpaceAliasedRegs) { PossibleRegs |= *ScratchSpaceAliasedRegs; } PossibleRegs.flip(); PossibleRegs &= Op.getRegisterAliasing().sourceBits(); PossibleRegsForVar.push_back(std::move(PossibleRegs)); } SmallVector<int, 2> Iterators(TiedVariables.size(), 0); while (true) { InstructionTemplate TmpIT = IT; // Find a possible register for each variable in turn, marking the // register as taken. for (size_t VarId = 0; VarId < TiedVariables.size(); ++VarId) { const int NextPossibleReg = PossibleRegsForVar[VarId].find_next(Iterators[VarId]); if (NextPossibleReg <= 0) { return Instructions; } TmpIT.getValueFor(*TiedVariables[VarId]) = llvm::MCOperand::createReg(NextPossibleReg); // Bump iterator. Iterators[VarId] = NextPossibleReg; // Prevent other variables from using the register. for (BitVector &OtherPossibleRegs : PossibleRegsForVar) { OtherPossibleRegs.reset(NextPossibleReg); } } Instructions.push_back(std::move(TmpIT)); } }
BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC) const { BitVector Allocatable(getNumRegs()); if (RC) { // A register class with no allocatable subclass returns an empty set. const TargetRegisterClass *SubClass = getAllocatableClass(RC); if (SubClass) getAllocatableSetForRC(MF, SubClass, Allocatable); } else { for (const TargetRegisterClass *C : regclasses()) if (C->isAllocatable()) getAllocatableSetForRC(MF, C, Allocatable); } // Mask out the reserved registers BitVector Reserved = getReservedRegs(MF); Allocatable &= Reserved.flip(); return Allocatable; }
BitVector* BitVector::copyflip() { BitVector *res = new BitVector(); res->copy(*this); res->flip(); return res; }