a course project of COMPUTER ARCHITECTURE

In Project1, we are required to implement a simple un-pipelined MIPS simulator. Given a plain sample file with the 0-1 string in every line, we need first to output the corresponding assembly code and then simulate the execution of the code with every step.

Instead, an MIPS simulator with pipeline support need to be implemented in Project2. Please note Project2 requires that simulation finishes when the BREAK instruction is fetched which is strange because the pipelined instructions may not be flushed. But I just implement a simulator as the requirement asked.

The specific requirements of both projects are also included. All the basic and extra tests provided by the teacher have been passed.