GitHub - hemanthtulimilli/Cache-Sim: 32 bit computer with byte addressable; L1 Data cache with 1024 sets and 4 way set associative with 32 Bytes line size implemented with LRU algorithm and Write-back.

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32 bit computer with byte addressable; L1 Data cache with 1024 sets and 4 way set associative with 32 Bytes line size implemented with LRU algorithm and Write-back.

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
CacheSimulatorDocumentation.pdf		CacheSimulatorDocumentation.pdf
Cache_Sim.c		Cache_Sim.c
Output.txt		Output.txt
object		object
test.c		test.c
trace1.txt		trace1.txt
trace2.txt		trace2.txt
trace3.txt		trace3.txt

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32 bit computer with byte addressable; L1 Data cache with 1024 sets and 4 way set associative with 32 Bytes line size implemented with LRU algorithm and Write-back.

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