Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
_ngo		_ngo
_xmsgs		_xmsgs
iseconfig		iseconfig
isim		isim
netgen/synthesis		netgen/synthesis
xlnx_auto_0_xdb		xlnx_auto_0_xdb
xst/work		xst/work
.lso		.lso
MEM.mem		MEM.mem
MEMORY.bld		MEMORY.bld
MEMORY.cmd_log		MEMORY.cmd_log
MEMORY.lso		MEMORY.lso
MEMORY.ngc		MEMORY.ngc
MEMORY.ngr		MEMORY.ngr
MEMORY.prj		MEMORY.prj
MEMORY.stx		MEMORY.stx
MEMORY.syr		MEMORY.syr
MEMORY.v		MEMORY.v
MEMORY.xst		MEMORY.xst
MEMORY_beh.prj		MEMORY_beh.prj
MEMORY_isim_beh.exe		MEMORY_isim_beh.exe
MEMORY_ngdbuild.xrpt		MEMORY_ngdbuild.xrpt
MEMORY_xst.xrpt		MEMORY_xst.xrpt
Memorynew_summary.html		Memorynew_summary.html
MyCPU.gise		MyCPU.gise
MyCPU.xise		MyCPU.xise
README.md		README.md
Reg_envsettings.html		Reg_envsettings.html
Reg_summary.html		Reg_summary.html
STAGES.prj		STAGES.prj
STAGES.stx		STAGES.stx
STAGES.v		STAGES.v
STAGES.xst		STAGES.xst
STAGES_isim_beh.exe		STAGES_isim_beh.exe
STAGES_isim_beh1.wdb		STAGES_isim_beh1.wdb
STAGES_summary.html		STAGES_summary.html
alu.v		alu.v
anvyl.ucf		anvyl.ucf
basys.ucf		basys.ucf
compxlib.cfg		compxlib.cfg
compxlib.log		compxlib.log
constant.v		constant.v
convert.v		convert.v
fuse.log		fuse.log
fuse.xmsgs		fuse.xmsgs
fuseRelaunch.cmd		fuseRelaunch.cmd
isim.cmd		isim.cmd
isim.log		isim.log
kbctrl.v		kbctrl.v
kcode_ascii.v		kcode_ascii.v
mycpu.bgn		mycpu.bgn
mycpu.bit		mycpu.bit
mycpu.bld		mycpu.bld
mycpu.cmd_log		mycpu.cmd_log
mycpu.drc		mycpu.drc
mycpu.lso		mycpu.lso
mycpu.ncd		mycpu.ncd
mycpu.ngc		mycpu.ngc
mycpu.ngd		mycpu.ngd
mycpu.ngr		mycpu.ngr
mycpu.pad		mycpu.pad
mycpu.par		mycpu.par
mycpu.pcf		mycpu.pcf
mycpu.prj		mycpu.prj
mycpu.ptwx		mycpu.ptwx
mycpu.stx		mycpu.stx
mycpu.syr		mycpu.syr
mycpu.twr		mycpu.twr
mycpu.twx		mycpu.twx
mycpu.unroutes		mycpu.unroutes
mycpu.ut		mycpu.ut
mycpu.v		mycpu.v
mycpu.xpi		mycpu.xpi
mycpu.xst		mycpu.xst
mycpu_bitgen.xwbt		mycpu_bitgen.xwbt
mycpu_envsettings.html		mycpu_envsettings.html
mycpu_guide.ncd		mycpu_guide.ncd
mycpu_isim_beh.exe		mycpu_isim_beh.exe
mycpu_isim_beh1.wdb		mycpu_isim_beh1.wdb
mycpu_map.map		mycpu_map.map
mycpu_map.mrp		mycpu_map.mrp
mycpu_map.ncd		mycpu_map.ncd
mycpu_map.ngm		mycpu_map.ngm
mycpu_map.xrpt		mycpu_map.xrpt
mycpu_ngdbuild.xrpt		mycpu_ngdbuild.xrpt
mycpu_pad.csv		mycpu_pad.csv
mycpu_pad.txt		mycpu_pad.txt
mycpu_par.xrpt		mycpu_par.xrpt
mycpu_stx_beh.prj		mycpu_stx_beh.prj
mycpu_summary.html		mycpu_summary.html
mycpu_summary.xml		mycpu_summary.xml
mycpu_usage.xml		mycpu_usage.xml
mycpu_xst.xrpt		mycpu_xst.xrpt
newmemory.v		newmemory.v
pc.v		pc.v
reg.v		reg.v
screen_memory.v		screen_memory.v
test.ucf		test.ucf
test.v		test.v
test_beh.prj		test_beh.prj

Repository files navigation

组成原理课设

华中科技大学2011级组成原理课设，希望看到的同级同学和学弟不要照抄。

利用verilog语言在FPGA开发板上编写一个简单的cpu，实现cpu各种功能。

sdlu1992/MyCPU

Folders and files

Latest commit

History