unsigned int pin_mux_spi1_d0(unsigned int PinNr) { switch(PinNr) { case Spi1_D0_PinMux_H17: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_CRS) = (CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_PUTYPESEL | CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RXACTIVE | CONTROL_CONF_MUXMODE(2)); break; case Spi1_D0_PinMux_B13: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_FSX) = (CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_PUTYPESEL | CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_RXACTIVE | CONTROL_CONF_MUXMODE(2)); break; case Spi1_D0_PinMux_E18: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_CTSN(0)) = (CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_PUTYPESEL | CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_RXACTIVE | CONTROL_CONF_MUXMODE(4)); break; default: return 0; } return 0; }
unsigned int pin_mux_spi1_d1(unsigned int PinNr) { switch(PinNr) { case Spi1_D1_PinMux_J15: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXERR) = (CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_PUTYPESEL | CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE | CONTROL_CONF_MUXMODE(2)); break; case Spi1_D1_PinMux_D12: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_AXR0) = (CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_PUTYPESEL | CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_RXACTIVE | CONTROL_CONF_MUXMODE(2)); break; case Spi1_D1_PinMux_E17: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_RTSN(0)) = (CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_PUTYPESEL | CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_RXACTIVE | CONTROL_CONF_MUXMODE(4)); break; default: return 0; } return 0; }
void modulo3(int nGpio){ switch(nGpio){ case GPIO_0 ... GPIO_4: selectMII1(nGpio); break; case GPIO_5 ... GPIO_6: selectI2C0(nGpio); break; case GPIO_7 ... GPIO_8: GPIOPinMuxSetup(CONTROL_CONF_EMU(0), CONTROL_CONF_MUXMODE(7)); break; case GPIO_9 ... GPIO_10: selectMII1(nGpio); break; case GPIO_13: GPIOPinMuxSetup(CONTROL_CONF_USB_DRVVBUS(1), CONTROL_CONF_MUXMODE(7)); break; case GPIO_14 ... GPIO_21: selectMCASPO(nGpio); break; } }
unsigned int pin_mux_spi1_sclk(unsigned int PinNr) { switch(PinNr) { case Spi1_Sclk_PinMux_H16: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL) = (CONTROL_CONF_MII1_COL_CONF_MII1_COL_PUTYPESEL | CONTROL_CONF_MII1_COL_CONF_MII1_COL_RXACTIVE | CONTROL_CONF_MUXMODE(2)); break; case Spi1_Sclk_PinMux_A13: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_ACLKX) = (CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_PUTYPESEL | CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_RXACTIVE | CONTROL_CONF_MUXMODE(2)); break; case Spi1_Sclk_PinMux_C18: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_ECAP0_IN_PWM0_OUT) = (CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_PUTYPESEL | CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_RXACTIVE | CONTROL_CONF_MUXMODE(4)); break; default: return 0; } return 0; }
void modulo1(int nGpio){ int num; switch(nGpio){ case GPIO_0 ... GPIO_7: GPIOPinMuxSetup(CONTROL_CONF_GPMC_AD(nGpio), CONTROL_CONF_MUXMODE(7)); break; case GPIO_12 ... GPIO_15: GPIOPinMuxSetup(CONTROL_CONF_GPMC_A(7), CONTROL_CONF_MUXMODE(7)); break; case GPIO_8 ... GPIO_11: selectUART(nGpio); break; case GPIO_16 ... GPIO_27: num = nGpio - 16; GPIOPinMuxSetup(CONTROL_CONF_GPMC_A(num), CONTROL_CONF_MUXMODE(7)); break; case GPIO_28: GPIOPinMuxSetup(CONTROL_CONF_GPMC_BE1N, CONTROL_CONF_MUXMODE(7)); break; case GPIO_29 ... GPIO_31: selectCSN(nGpio); break; } }
unsigned int pin_mux_spi1_cs1(unsigned int PinNr) { switch(PinNr) { case Spi1_CS1_PinMux_E16: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_TXD(0)) = (CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_PUTYPESEL | CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_RXACTIVE | CONTROL_CONF_MUXMODE(1)); break; case Spi1_CS1_PinMux_D17: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_RTSN(1)) = (CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_PUTYPESEL | CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_RXACTIVE | CONTROL_CONF_MUXMODE(4)); break; case Spi1_CS1_PinMux_C18: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_ECAP0_IN_PWM0_OUT) = (CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_PUTYPESEL | CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_RXACTIVE | CONTROL_CONF_MUXMODE(2)); break; case Spi1_CS1_PinMux_A15: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_XDMA_EVENT_INTR(0)) = (CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_PUTYPESEL | CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_RXACTIVE | CONTROL_CONF_MUXMODE(3)); break; default: return 0; } return 0; }
void I2CPinMuxSetup(unsigned int instance) { if(instance == 0) { HWREG(SOC_CONTROL_REGS + CONTROL_CONF_I2C0_SDA) = (CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_RXACTIVE | CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_SLEWCTRL | CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_PUTYPESEL ); HWREG(SOC_CONTROL_REGS + CONTROL_CONF_I2C0_SCL) = (CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_RXACTIVE | CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_SLEWCTRL | CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_PUTYPESEL ); } else if(instance == 1) { /* I2C_SCLK */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_D1) = (CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_PUTYPESEL | CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_RXACTIVE | CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_SLEWCTRL | CONTROL_CONF_MUXMODE(2)); /* I2C_SDA */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_CS0) = (CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_PUTYPESEL | CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_RXACTIVE | CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_SLEWCTRL | CONTROL_CONF_MUXMODE(2)); } }
void HSMMCSDPinMuxSetup(void) { // SD-Card HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MMC0_DAT3) = (0 << CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_MMODE_SHIFT) | (0 << CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_PUDEN_SHIFT) | (1 << CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_PUTYPESEL_SHIFT)| (1 << CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_RXACTIVE_SHIFT); HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MMC0_DAT2) = (0 << CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_MMODE_SHIFT) | (0 << CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_PUDEN_SHIFT) | (1 << CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_PUTYPESEL_SHIFT)| (1 << CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_RXACTIVE_SHIFT); HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MMC0_DAT1) = (0 << CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_MMODE_SHIFT) | (0 << CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_PUDEN_SHIFT) | (1 << CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_PUTYPESEL_SHIFT)| (1 << CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_RXACTIVE_SHIFT); HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MMC0_DAT0) = (0 << CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_MMODE_SHIFT) | (0 << CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_PUDEN_SHIFT) | (1 << CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_PUTYPESEL_SHIFT)| (1 << CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_RXACTIVE_SHIFT); HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MMC0_CLK) = (0 << CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_MMODE_SHIFT) | (0 << CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_PUDEN_SHIFT) | (1 << CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_PUTYPESEL_SHIFT)| (1 << CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_RXACTIVE_SHIFT); HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MMC0_CMD) = (0 << CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_MMODE_SHIFT) | (0 << CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_PUDEN_SHIFT) | (1 << CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_PUTYPESEL_SHIFT)| (1 << CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_RXACTIVE_SHIFT); HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_CS1) = (5 << CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_MMODE_SHIFT) | (0 << CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_PUDEN_SHIFT) | (1 << CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_PUTYPESEL_SHIFT)| (1 << CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_RXACTIVE_SHIFT); //eMMC //P8 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_AD(0))=CONTROL_CONF_MUXMODE(1); //25 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_AD(1))=CONTROL_CONF_MUXMODE(1); //24 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_AD(2))=CONTROL_CONF_MUXMODE(1); // 5 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_AD(3))=CONTROL_CONF_MUXMODE(1); // 6 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_AD(4))=CONTROL_CONF_MUXMODE(1); //23 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_AD(5))=CONTROL_CONF_MUXMODE(1); //22 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_AD(6))=CONTROL_CONF_MUXMODE(1); // 3 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_AD(7))=CONTROL_CONF_MUXMODE(1); // 4 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_CSN(2))=CONTROL_CONF_MUXMODE(2); //20 HWREG(SOC_CONTROL_REGS+CONTROL_CONF_GPMC_CSN(1))=CONTROL_CONF_MUXMODE(2); //21 }
// TODO: need to init more pins here void gpioPinMux(void) { // gpio1 pin 23 HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(7)) = CONTROL_CONF_MUXMODE(7); // HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(2)) = CONTROL_CONF_MUXMODE(7); // HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_OEN_REN) = CONTROL_CONF_MUXMODE(7); }
static void GetGPIOPinName(){ if (GPIO_INSTANCE_PIN_NUMBER >= 0 || GPIO_INSTANCE_PIN_NUMBER <= 7){ GPIOPinMuxSetup(CONTROL_CONF_GPMC_AD(GPIO_INSTANCE_PIN_NUMBER), CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER)); }else if (GPIO_INSTANCE_PIN_NUMBER >= 8 || GPIO_INSTANCE_PIN_NUMBER <= 11){ switch(GPIO_INSTANCE_PIN_NUMBER){ case 8: GPIOPinMuxSetup(CONTROL_CONF_UART_RTSN(GPIO_INSTANCE_PIN_NUMBER), CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER)); break; case 9: GPIOPinMuxSetup(CONTROL_CONF_UART_CTSN(GPIO_INSTANCE_PIN_NUMBER), CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER)); break; case 10: GPIOPinMuxSetup(CONTROL_CONF_UART_RXD(GPIO_INSTANCE_PIN_NUMBER), CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER)); break; case 11: GPIOPinMuxSetup(CONTROL_CONF_UART_TXD(GPIO_INSTANCE_PIN_NUMBER), CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER)); break; } }else if (GPIO_INSTANCE_PIN_NUMBER >= 12 || GPIO_INSTANCE_PIN_NUMBER <= 14){ GPIOPinMuxSetup(CONTROL_CONF_GPMC_AD(GPIO_INSTANCE_PIN_NUMBER), CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER)); }else if (GPIO_INSTANCE_PIN_NUMBER >= 16 || GPIO_INSTANCE_PIN_NUMBER <= 27){ int PIN_REFERENCE = GPIO_INSTANCE_PIN_NUMBER - 16; GPIOPinMuxSetup(CONTROL_CONF_GPMC_A(PIN_REFERENCE), CONTROL_CONF_MUXMODE(PIN_REFERENCE)); }else if (GPIO_INSTANCE_PIN_NUMBER == 28) { GPIOPinMuxSetup(CONTROL_CONF_GPMC_BE1N , CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER)); }else if (GPIO_INSTANCE_PIN_NUMBER >= 29 || GPIO_INSTANCE_PIN_NUMBER <= 31){ } }
void modulo2(int nGpio){ int num; switch(nGpio){ case GPIO_0 ... GPIO_5: selectGPMC(nGpio); break; case GPIO_6 ... GPIO_17: num = nGpio - 6; GPIOPinMuxSetup(CONTROL_CONF_LCD_DATA(num), CONTROL_CONF_MUXMODE(7)); break; case GPIO_18 ... GPIO_21: num = nGpio - 18; selectMII1RXD(nGpio); break; case GPIO_22 ... GPIO_25: selectLCD(nGpio); break; case GPIO_26 ... GPIO_31: selectMMC0(nGpio); break; } }
unsigned int GPIO2Pin24PinMuxSetup(void) { unsigned int profile = 0; unsigned int status = FALSE; profile = EVMProfileGet(); switch(profile) { case 3: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_PCLK) = CONTROL_CONF_MUXMODE(7); status = TRUE; break; /* Fall through for cases 0, 1, 2, 4, 5, 6 and 7. */ case 0: case 1: case 2: case 4: case 5: case 6: case 7: default: break; } return status; }
unsigned int GPIO1Pin2PinMuxSetup(void) { unsigned int profile = 7; unsigned int status = FALSE; profile = EVMProfileGet(); switch(profile) { case 0: case 3: //HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_D0) = HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(2)) = ((CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_RXACTIVE | CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUDEN | CONTROL_CONF_MUXMODE(7)) & (~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL)); status = TRUE; break; case 1: case 2: case 4: case 5: case 6: case 7: default: break; } return status; }
unsigned int GPIO1Pin20PinMuxSetup(void) { unsigned int profile = 0; unsigned int status = FALSE; profile = EVMProfileGet(); switch(profile) { /* Fall through for cases 0, 1, 2, 4, 5 and 6. */ case 0: case 1: case 2: case 4: case 5: case 6: case 7: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(4)) = CONTROL_CONF_MUXMODE(7); status = TRUE; break; case 3: default: break; } return status; }
unsigned int GPIO1Pin28PinMuxSetup(void) { unsigned int profile = 1; unsigned int status = FALSE; profile = EVMProfileGet(); switch(profile) { /* Fall through for cases 1, 2, 4 and 6. */ case 1: case 2: case 4: case 6: case 7: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_BE1N) = (CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_RXACTIVE | CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_PUTYPESEL | CONTROL_CONF_MUXMODE(7)); status = TRUE; break; /* Fall through for cases 0, 3, and 5. */ case 0: case 3: case 5: default: break; } return status; }
unsigned int GPIO0Pin7PinMuxSetup(void) { unsigned int profile = 0; unsigned int status = FALSE; profile = EVMProfileGet(); switch(profile) { /* Fall through for cases 0, 1, and 2. */ case 0: case 1: case 2: case 7: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_ECAP0_IN_PWM0_OUT) = (CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_RXACTIVE | CONTROL_CONF_MUXMODE(7)); status = TRUE; break; /* Fall through for cases 3, 4, 5 and 6. */ case 3: case 4: case 5: case 6: default: break; } return status; }
unsigned int GPIO0Pin6PinMuxSetup(void) { unsigned int profile = 0; unsigned int status = FALSE; profile = EVMProfileGet(); switch(profile) { /* Fall through for cases 0, 1, 2, 3, 4, and 6. */ case 0: case 1: case 2: case 3: case 4: case 6: case 7: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_CS1) = (CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_RXACTIVE | CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_PUTYPESEL | CONTROL_CONF_MUXMODE(7)); status = TRUE; break; /* Fall through for case 5. */ case 5: default: break; } return status; }
unsigned int GPIO1Pin16PinMuxSetup(void) { unsigned int profile = 0; unsigned int status = FALSE; profile = EVMProfileGet(); switch(profile) { /* Fall through for cases 0 and 3. */ case 0: case 3: case 5: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(0)) = (CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_RXACTIVE | CONTROL_CONF_MUXMODE(7)); status = TRUE; break; /* Fall through for cases 1, 2, 4, 6 and 7. */ case 1: case 2: case 4: case 6: case 7: default: break; } return status; }
/** * \brief This function does the Pin Multiplexing and selects GPIO pin * GPIO1[4] for use. GPIO1[4] means 4th pin of GPIO1 instance. * This pin can be used to toggle User Led 4. * * \param None * */ void GPIO1Pin4PinMuxSetup(void) { HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(4)) = (CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RXACTIVE | CONTROL_CONF_MUXMODE(7)); }
void gpio_dir_2_setup (void) { /* Selecting GPIO1[7] pin for use. */ GpioPinMuxSetup(GPIO_1_3, CONTROL_CONF_MUXMODE(7)); /* Setting the GPIO pin as an output pin. */ GPIODirModeSet(SOC_GPIO_1_REGS, 3, GPIO_DIR_OUTPUT); }
/** * \brief This function does the Pin Multiplexing and selects GPIO1[2] * for use. By GPIO1[2], we mean 2nd pin of GPIO1 instance. * * \param None * * \return none */ void GPIO1Pin2PinMuxSetup(void) { HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(2)) = ((CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_RXACTIVE | CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUDEN | CONTROL_CONF_MUXMODE(7)) & (~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL)); }
/** * \brief This function does the Pin Multiplexing and selects GPIO0[2] * for use. By GPIO0[2], we mean 2nd pin of GPIO0 instance. * * \param None * * \return none */ void GPIO0Pin2PinMuxSetup(void) { HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_SCLK) = ((CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE | CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUDEN | CONTROL_CONF_MUXMODE(7)) & (~CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL)); }
/* ** This function enables GPIO1 pins */ void GPIO1PinMuxSetup(unsigned int pinNo) { HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(pinNo)) = (CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_SLEWCTRL | /* Slew rate slow */ CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_RXACTIVE | /* Receiver enabled */ (CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUDEN & (~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUDEN)) | /* PU_PD enabled */ (CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL & (~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL)) | /* PD */ (CONTROL_CONF_MUXMODE(7)) /* Select mode 7 */ ); }
/*#####################################################*/ unsigned int pin_mux_spi_sclk_beaglebone(unsigned int SpiNr) { switch(SpiNr) { case 0: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_SCLK) = (CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL | CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE | CONTROL_CONF_MUXMODE(0)); break; case 1: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_ACLKX) = (CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_PUTYPESEL | CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_RXACTIVE | CONTROL_CONF_MUXMODE(2)); break; default: return 0; } return 1; }
unsigned int pin_mux_spi_cs0_beaglebone(unsigned int SpiNr) { switch(SpiNr) { case 0: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_CS0) = (CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_PUTYPESEL | CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_RXACTIVE | CONTROL_CONF_MUXMODE(0)); break; case 1: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_AHCLKR) = (CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_PUTYPESEL | CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_RXACTIVE | CONTROL_CONF_MUXMODE(2)); break; default: return 0; } return 1; }
unsigned int pin_mux_spi1_cs0(unsigned int PinNr) { switch(PinNr) { case Spi1_CS0_PinMux_E15: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_RXD(0)) = (CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_PUTYPESEL | CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_RXACTIVE | CONTROL_CONF_MUXMODE(1)); break; case Spi1_CS0_PinMux_E17: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_RTSN(0)) = (CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_PUTYPESEL | CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_RXACTIVE | CONTROL_CONF_MUXMODE(5)); break; case Spi1_CS0_PinMux_H18: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_RMII1_REFCLK) = (CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_PUTYPESEL | CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE | CONTROL_CONF_MUXMODE(2)); break; case Spi1_CS0_PinMux_D18: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_CTSN(1)) = (CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_PUTYPESEL | CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_RXACTIVE | CONTROL_CONF_MUXMODE(4)); break; case Spi1_CS0_PinMux_C12: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_AHCLKR) = (CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_PUTYPESEL | CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_RXACTIVE | CONTROL_CONF_MUXMODE(3)); break; default: return 0; } return 0; }
unsigned int pin_mux_spi0_sclk(unsigned int PinNr) { switch(PinNr) { case Spi0_Sclk_PinMux_A17: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_SCLK) = (CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL | CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE | CONTROL_CONF_MUXMODE(0)); break; default: return 0; } return 0; }
unsigned int pin_mux_spi0_cs1(unsigned int PinNr) { switch(PinNr) { case Spi0_CS1_PinMux_C15: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_CS1) = (CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_PUTYPESEL | CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_RXACTIVE | CONTROL_CONF_MUXMODE(0)); break; default: return 0; } return 0; }
unsigned int pin_mux_spi_cs1_beaglebone(unsigned int SpiNr) { switch(SpiNr) { case 0: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_CS1) = (CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_PUTYPESEL | CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_RXACTIVE | CONTROL_CONF_MUXMODE(0)); break; default: return 0; } return 1; }
/* init_ecap * Initialize an eCAP module. This module will trigger on * every rising edge, and will store four captures. * */ void init_ecap( rtems_interrupt_handler handler, struct eCAP_data* arg) { uint32_t cm_per_clk_reg_offset; uint8_t ecap_intr_num; char ecap_intr_name[6]; uint8_t ecap_pin_mux_mode; uint32_t ecap_pin_reg_offset; struct eCAP_regs* ecap_regs; struct PWMSS_regs* pwmss_regs; uint8_t pwmss_tbclken_shift; rtems_event_set ecap_event_id; uint32_t util_val; /* used for clarity in register operations */ switch (arg->ecap_module) { case (0): cm_per_clk_reg_offset = CM_PER_EPWMSS0_CLKCTRL_OFFSET; ecap_intr_num = ECAP0_INT; strncpy(ecap_intr_name, "eCAP0", 6); ecap_pin_mux_mode = CONTROL_CONF_MUXMODE(0); ecap_pin_reg_offset = CONTROL_CONF_ECAP0_IN_PWM0_OUT_OFFSET; ecap_regs = (struct eCAP_regs*)ECAP0_REGS_BASE; pwmss_regs = (struct PWMSS_regs*)PWMSS0_MMIO_BASE; pwmss_tbclken_shift = PWMSS0_TBCLKEN; ecap_event_id = ECAP_0_EVENT; break; default: return; } /* Set up some generic data used by the ecap task and interrupt handler */ arg->num_intr = 0; arg->ecap_regs = ecap_regs; arg->ecap_event_id = ecap_event_id; /* Disable interrupts while we start up the eCAP module */ rtems_interrupt_level irqlvl; rtems_interrupt_disable(irqlvl); mmio_write(SOC_CONTROL_REGS + CONTROL_CONF_PWMSS_CTRL, (TBCLKEN_ENABLE << pwmss_tbclken_shift)); /* Enable the eCAP module in CM_PER_EPWMSS0_CLKCTRL (8.1.12.1.36) */ util_val = mmio_read(CM_PER_MMIO_BASE + cm_per_clk_reg_offset); util_val |= (MODULEMODE_ENABLE << MODULEMODE); mmio_write(CM_PER_MMIO_BASE + cm_per_clk_reg_offset, util_val); /* the following read _must_ happen or the ECCTL1 doesn't get set */ /* no, I don't know why. */ util_val = mmio_read(CM_PER_MMIO_BASE + cm_per_clk_reg_offset); RTEMS_COMPILER_MEMORY_BARRIER(); /* Configure the eCAP module to * trigger on rising pulses with no timer prescale * interrupt when the timer wraps * run in capture mode * wrap the timer * disable input and output synchronization */ ecap_regs->ECEINT = 0x0; RTEMS_COMPILER_MEMORY_BARRIER(); ecap_regs->ECCTL1 = (EC_RISING << CAP1POL) | (EC_RISING << CAP2POL) | (EC_RISING << CAP3POL) | (EC_RISING << CAP4POL) | (EC_ABS_MODE << CTRRST1) | (EC_ABS_MODE << CTRRST2) | (EC_ABS_MODE << CTRRST3) | (EC_ABS_MODE << CTRRST4) | (EC_ENABLE << CAPLDEN) | (EC_DIV1 << PRESCALE); RTEMS_COMPILER_MEMORY_BARRIER(); ecap_regs->ECCTL2 = (EC_CONTINUOUS << CONT_ONESHT) | (EC_EVENT4 << STOP_WRAP) | (EC_DISABLE << SYNCI_EN) | (EC_SYNCO_DIS << SYNCO_SEL) | (EC_CAP_MODE << CAP_APWM); /* Per the docs, clear all the interrupt flags and timer registers, and * then enable the interrupts (15.3.4.1.9) */ ecap_regs->ECCLR = BIT(CTR_EQ_CMP) | BIT(CTR_EQ_PRD) | BIT(CTROVF) | BIT(CEVT4) | BIT(CEVT3) | BIT(CEVT2) | BIT(CEVT1) | BIT(INT); ecap_regs->ECEINT = BIT(CTROVF) | BIT(CEVT4) | BIT(CEVT3) | BIT(CEVT2) | BIT(CEVT1); RTEMS_COMPILER_MEMORY_BARRIER(); /* Enable the eCAP 0 timer (it will start when the clock is enabled */ ecap_regs->ECCTL2 |= (EC_RUN << TSCTRSTOP); RTEMS_COMPILER_MEMORY_BARRIER(); /* Set the "smart" idle mode in register SYSCONFIG (15.1.3.2) */ util_val = (IDLEMODE_SMART << SYSCONFIG_IDLEMODE); pwmss_regs->SYSCONFIG = util_val; RTEMS_COMPILER_MEMORY_BARRIER(); /* Enable the clock in pwmss_ctrl (9.3.1.32) */ util_val = pwmss_regs->CLKCONFIG; util_val |= (CLKCONFIG_CLK_EN << eCAPCLK_EN); pwmss_regs->CLKCONFIG = util_val; RTEMS_COMPILER_MEMORY_BARRIER(); util_val = pwmss_regs->CLKSTATUS; if ( !(util_val & (1<<eCAP_CLK_EN_ACK)) ) { perror("Failed to start eCAP counter!\n"); } rtems_status_code have_isr = rtems_interrupt_handler_install( ecap_intr_num, ecap_intr_name, RTEMS_INTERRUPT_UNIQUE, handler, (void*)arg); if (have_isr != RTEMS_SUCCESSFUL) { printf("Failed to install eCAP0 ISR!\n"); } /* Re-enable interrupts, preserving cpsr */ rtems_interrupt_enable(irqlvl); /* Mux the ecap pin by setting the RXACTIVE bit and mode * in pin register (9.3.1.51) to enable external eCAP * triggering */ mux_pin(ecap_pin_reg_offset, ecap_pin_mux_mode); }