static void h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc) { unsigned int mask, irq; mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT); irq = IRQ_CHAINED_GPIOE(0); IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq); h720x_gpio_handler(mask, irq, desc); }
/* * Initialize IRQ's, mask all, enable multiplexed irq's */ void __init h720x_init_irq (void) { int irq; /* Mask global irq's */ CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0; /* Mask all multiplexed irq's */ CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0; CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0; CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0; CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0; /* Initialize global IRQ's, fast path */ for (irq = 0; irq < NR_GLBL_IRQS; irq++) { irq_set_chip_and_handler(irq, &h720x_global_chip, handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } /* Initialize multiplexed IRQ's, slow path */ for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) { irq_set_chip_and_handler(irq, &h720x_gpio_chip, handle_edge_irq); set_irq_flags(irq, IRQF_VALID ); } irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler); irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler); irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler); #ifdef CONFIG_CPU_H7202 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) { irq_set_chip_and_handler(irq, &h720x_gpio_chip, handle_edge_irq); set_irq_flags(irq, IRQF_VALID ); } irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); #endif /* Enable multiplexed irq's */ CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX; }
void __init h720x_init_irq (void) { int irq; CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0; CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0; CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0; CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0; CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0; for (irq = 0; irq < NR_GLBL_IRQS; irq++) { irq_set_chip_and_handler(irq, &h720x_global_chip, handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) { irq_set_chip_and_handler(irq, &h720x_gpio_chip, handle_edge_irq); set_irq_flags(irq, IRQF_VALID ); } irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler); irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler); irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler); #ifdef CONFIG_CPU_H7202 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) { irq_set_chip_and_handler(irq, &h720x_gpio_chip, handle_edge_irq); set_irq_flags(irq, IRQF_VALID ); } irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); #endif CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX; }