void ICACHE_FLASH_ATTR led_spi_master_init(uint8 spi_no)
{
uint32 regvalue;
if (spi_no > 1)
{
return;
}
WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105); //clear bit9
if (spi_no == SPI)
{
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, 1); //configure io to spi mode
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 1); //configure io to spi mode
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, 1); //configure io to spi mode
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, 1); //configure io to spi mode
}
else if (spi_no == HSPI)
{
//PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, 2); //configure io to spi mode
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 2); //configure io to spi mode //do
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, 2); //configure io to spi mode //clk
//PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, 2); //configure io to spi mode
}
regvalue = READ_PERI_REG(SPI_FLASH_USER(spi_no));
regvalue = regvalue | SPI_USR_COMMAND;
regvalue = regvalue & (~BIT2); //clear bit 2, undocumented
WRITE_PERI_REG(SPI_FLASH_USER(spi_no), regvalue);
WRITE_PERI_REG(SPI_FLASH_CTRL1(spi_no), 0); //reduces time between transmissions by 1us
//fastest: WRITE_PERI_REG(SPI_FLASH_CLOCK(spi_no), (0<<SPI_CLKDIV_PRE_S) | (5<<SPI_CLKCNT_N_S) | (0<<SPI_CLKCNT_H_S) | (4<<SPI_CLKCNT_L_S)); //clear bit 31,set SPI clock div
WRITE_PERI_REG(SPI_FLASH_CLOCK(spi_no), (0<<SPI_CLKDIV_PRE_S) | (10<<SPI_CLKCNT_N_S) | (0<<SPI_CLKCNT_H_S) | (5<<SPI_CLKCNT_L_S)); //clear bit 31,set SPI clock div
}
void hspi_init(void)
{
spi_fifo = (uint32_t*)SPI_FLASH_C0(HSPI);
WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105); //clear bit9
//PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, 2); // HSPIQ MISO GPIO12
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 2); // HSPID MOSI GPIO13
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, 2); // CLK GPIO14
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, 2); // CS GPIO15
// SPI clock = CPU clock / 10 / 4
// time length HIGHT level = (CPU clock / 10 / 2) ^ -1,
// time length LOW level = (CPU clock / 10 / 2) ^ -1
WRITE_PERI_REG(SPI_FLASH_CLOCK(HSPI),
(((HSPI_PRESCALER - 1) & SPI_CLKDIV_PRE) << SPI_CLKDIV_PRE_S) |
((1 & SPI_CLKCNT_N) << SPI_CLKCNT_N_S) |
((0 & SPI_CLKCNT_H) << SPI_CLKCNT_H_S) |
((1 & SPI_CLKCNT_L) << SPI_CLKCNT_L_S));
WRITE_PERI_REG(SPI_FLASH_CTRL1(HSPI), 0);
uint32_t regvalue = SPI_FLASH_DOUT;
regvalue &= ~(BIT2 | SPI_FLASH_USR_ADDR | SPI_FLASH_USR_DUMMY | SPI_FLASH_USR_DIN | SPI_USR_COMMAND | SPI_DOUTDIN); //clear bit 2 see example IoT_Demo
WRITE_PERI_REG(SPI_FLASH_USER(HSPI), regvalue);
}
/// @brief HSPI Configuration for tranasmit and receive
/// @param[in] configState: CONFIG_FOR_RX_TX or CONFIG_FOR_RX
/// @return void
static void hspi_config(int configState)
{
uint32_t valueOfRegisters = 0;
hspi_waitReady();
if (configState == CONFIG_FOR_TX)
{
valueOfRegisters |= SPI_FLASH_DOUT;
//clear bit 2 see example IoT_Demo
valueOfRegisters &= \
~(BIT2 | SPI_FLASH_USR_ADDR | SPI_FLASH_USR_DUMMY | \
SPI_FLASH_USR_DIN | SPI_USR_COMMAND | SPI_DOUTDIN);
}
else if (configState == CONFIG_FOR_RX_TX)
{
valueOfRegisters |= SPI_FLASH_DOUT | SPI_DOUTDIN | SPI_CK_I_EDGE;
//clear bit 2 see example IoT_Demo
valueOfRegisters &= \
~(BIT2 | SPI_FLASH_USR_ADDR | SPI_FLASH_USR_DUMMY | \
SPI_FLASH_USR_DIN | SPI_USR_COMMAND);
}
else
{
return; // Error
}
WRITE_PERI_REG(SPI_FLASH_USER(HSPI), valueOfRegisters);
}
void spi_reinit(spi_config *config)
{
current_spi_port = config->spi_port;
spi_fifo = (uint32_t*)SPI_FLASH_C0(current_spi_port);
uint32_t regvalue = SPI_FLASH_DOUT;
WRITE_PERI_REG(SPI_FLASH_CLOCK(current_spi_port), config->clock_reg_val);
WRITE_PERI_REG(SPI_FLASH_CTRL1(current_spi_port), 0);
switch(config->mode)
{
case spi_mode_tx:
regvalue &= ~(BIT2 | SPI_FLASH_USR_ADDR | SPI_FLASH_USR_DUMMY | SPI_FLASH_USR_DIN | SPI_USR_COMMAND | SPI_DOUTDIN);
break;
case spi_mode_txrx:
regvalue |= SPI_DOUTDIN | SPI_CK_I_EDGE;
regvalue &= ~(BIT2 | SPI_FLASH_USR_ADDR | SPI_FLASH_USR_DUMMY | SPI_FLASH_USR_DIN | SPI_USR_COMMAND);
break;
}
WRITE_PERI_REG(SPI_FLASH_USER(current_spi_port), regvalue);
}