static bool etna_resource_sampler_compatible(struct etna_resource *res) { if (util_format_is_compressed(res->base.format)) return true; struct etna_screen *screen = etna_screen(res->base.screen); /* This GPU supports texturing from supertiled textures? */ if (res->layout == ETNA_LAYOUT_SUPER_TILED && VIV_FEATURE(screen, chipMinorFeatures2, SUPERTILED_TEXTURE)) return true; /* TODO: LINEAR_TEXTURE_SUPPORT */ /* Otherwise, only support tiled layouts */ if (res->layout != ETNA_LAYOUT_TILED) return false; /* If we have HALIGN support, we can allow for the RS padding */ if (VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN)) return true; /* Non-HALIGN GPUs only accept 4x4 tile-aligned textures */ if (res->halign != TEXTURE_HALIGN_FOUR) return false; return true; }
static bool gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt) { if (fmt == TEXTURE_FORMAT_ETC1) return VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION); if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5) return VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION); return true; }
/* Is rs alignment needed? */ static bool is_rs_align(struct etna_screen *screen, const struct pipe_resource *tmpl) { return screen->specs.use_blt ? false : ( VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) || !etna_resource_sampler_only(tmpl)); }
/* Return true if the GPU can use sampler TS with this sampler view. * Sampler TS is an optimization used when rendering to textures, where * a resolve-in-place can be avoided when rendering has left a (valid) TS. */ static bool etna_can_use_sampler_ts(struct pipe_sampler_view *view, int num) { /* Can use sampler TS when: * - the hardware supports sampler TS. * - the sampler view will be bound to sampler <VIVS_TS_SAMPLER__LEN. * HALTI5 adds a mapping from sampler to sampler TS unit, but this is AFAIK * absent on earlier models. * - it is a texture, not a buffer. * - the sampler view has a supported format for sampler TS. * - the sampler will have one LOD, and it happens to be level 0. * (it is not sure if the hw supports it for other levels, but available * state strongly suggests only one at a time). * - the resource TS is valid for level 0. */ struct etna_resource *rsc = etna_resource(view->texture); struct etna_screen *screen = etna_screen(rsc->base.screen); return VIV_FEATURE(screen, chipMinorFeatures2, TEXTURE_TILED_READ) && num < VIVS_TS_SAMPLER__LEN && rsc->base.target != PIPE_BUFFER && translate_ts_sampler_format(rsc->base.format) != ETNA_NO_MATCH && view->u.tex.first_level == 0 && MIN2(view->u.tex.last_level, rsc->base.last_level) == 0 && rsc->levels[0].ts_valid; }
static bool gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt, enum pipe_format format) { bool supported = true; if (fmt == TEXTURE_FORMAT_ETC1) supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION); if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5) supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION); if (util_format_is_srgb(format)) supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); if (fmt & EXT_FORMAT) { supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); /* ETC1 is checked above, as it has its own feature bit. ETC2 is * supported with HALTI0, however that implementation is buggy in hardware. * The blob driver does per-block patching to work around this. As this * is currently not implemented by etnaviv, enable it for HALTI1 (GC3000) * only. */ if (util_format_is_etc(format)) supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1); } if (fmt & ASTC_FORMAT) { supported = screen->specs.tex_astc; } if (!supported) return false; if (texture_format_needs_swiz(format)) return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); return true; }
int main(int argc, char **argv) { int rv; int width = 256; int height = 256; int padded_width = etna_align_up(width, 64); int padded_height = etna_align_up(height, 64); printf("padded_width %i padded_height %i\n", padded_width, padded_height); rv = viv_open(); if(rv!=0) { fprintf(stderr, "Error opening device\n"); exit(1); } printf("Succesfully opened device\n"); bool supertiled = VIV_FEATURE(chipMinorFeatures0,SUPER_TILED); unsigned bits_per_tile = VIV_FEATURE(chipMinorFeatures0,2BITPERTILE)?2:4; printf("Supertile: %i, bits per tile: %i\n", supertiled, bits_per_tile); etna_vidmem *rt = 0; /* main render target */ etna_vidmem *rt_ts = 0; /* tile status for main render target */ etna_vidmem *z = 0; /* depth for main render target */ etna_vidmem *z_ts = 0; /* depth ts for main render target */ etna_vidmem *vtx = 0; /* vertex buffer */ etna_vidmem *aux_rt = 0; /* auxilary render target */ etna_vidmem *aux_rt_ts = 0; /* tile status for auxilary render target */ etna_vidmem *bmp = 0; /* bitmap */ size_t rt_size = padded_width * padded_height * 4; size_t rt_ts_size = etna_align_up((padded_width * padded_height * 4)*bits_per_tile/0x80, 0x100); size_t z_size = padded_width * padded_height * 2; size_t z_ts_size = etna_align_up((padded_width * padded_height * 2)*bits_per_tile/0x80, 0x100); size_t bmp_size = width * height * 4; if(etna_vidmem_alloc_linear(&rt, rt_size, gcvSURF_RENDER_TARGET, gcvPOOL_DEFAULT, true)!=ETNA_OK || etna_vidmem_alloc_linear(&rt_ts, rt_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK || etna_vidmem_alloc_linear(&z, z_size, gcvSURF_DEPTH, gcvPOOL_DEFAULT, true)!=ETNA_OK || etna_vidmem_alloc_linear(&z_ts, z_ts_size, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK || etna_vidmem_alloc_linear(&vtx, VERTEX_BUFFER_SIZE, gcvSURF_VERTEX, gcvPOOL_DEFAULT, true)!=ETNA_OK || etna_vidmem_alloc_linear(&aux_rt, 0x4000, gcvSURF_RENDER_TARGET, gcvPOOL_SYSTEM, true)!=ETNA_OK || etna_vidmem_alloc_linear(&aux_rt_ts, 0x80*bits_per_tile, gcvSURF_TILE_STATUS, gcvPOOL_DEFAULT, true)!=ETNA_OK || etna_vidmem_alloc_linear(&bmp, bmp_size, gcvSURF_BITMAP, gcvPOOL_DEFAULT, true)!=ETNA_OK ) { fprintf(stderr, "Error allocating video memory\n"); exit(1); } /* Phew, now we got all the memory we need. * Write interleaved attribute vertex stream. * Unlike the GL example we only do this once, not every time glDrawArrays is called, the same would be accomplished * from GL by using a vertex buffer object. */ for(int vert=0; vert<NUM_VERTICES; ++vert) { int src_idx = vert * COMPONENTS_PER_VERTEX; int dest_idx = vert * COMPONENTS_PER_VERTEX * 3; for(int comp=0; comp<COMPONENTS_PER_VERTEX; ++comp) { ((float*)vtx->logical)[dest_idx+comp+0] = vVertices[src_idx + comp]; /* 0 */ ((float*)vtx->logical)[dest_idx+comp+3] = vNormals[src_idx + comp]; /* 1 */ ((float*)vtx->logical)[dest_idx+comp+6] = vColors[src_idx + comp]; /* 2 */ } } etna_ctx *ctx = 0; if(etna_create(&ctx) != ETNA_OK) { printf("Unable to create context\n"); exit(1); } /* XXX how important is the ordering? I suppose we could group states (except the flushes, kickers, semaphores etc) * and simply submit them at once. Especially for consecutive states and masked stated this could be a big win * in DMA command buffer size. */ for(int frame=0; frame<1; ++frame) { printf("*** FRAME %i ****\n", frame); /* XXX part of this can be put outside the loop, but until we have usable context management * this is safest. */ etna_set_state(ctx, VIVS_GL_VERTEX_ELEMENT_CONFIG, 0x1); etna_set_state(ctx, VIVS_RA_CONTROL, 0x1); etna_set_state(ctx, VIVS_PA_W_CLIP_LIMIT, 0x34000001); etna_set_state(ctx, VIVS_PA_SYSTEM_MODE, 0x11); etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_UNK22, 0)); etna_set_state(ctx, VIVS_SE_CONFIG, 0x0); etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR); etna_set_state(ctx, VIVS_PE_COLOR_FORMAT, ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_PARTIAL, 0)); etna_set_state(ctx, VIVS_PE_ALPHA_CONFIG, ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR, 0) & ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_ALPHA, 0) & ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR, BLEND_FUNC_ONE) & ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA, BLEND_FUNC_ONE) & ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR, BLEND_FUNC_ZERO) & ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA, BLEND_FUNC_ZERO) & ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_EQ_COLOR, BLEND_EQ_ADD) & ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_EQ_ALPHA, BLEND_EQ_ADD)); etna_set_state(ctx, VIVS_PE_ALPHA_BLEND_COLOR, VIVS_PE_ALPHA_BLEND_COLOR_B(0) | VIVS_PE_ALPHA_BLEND_COLOR_G(0) | VIVS_PE_ALPHA_BLEND_COLOR_R(0) | VIVS_PE_ALPHA_BLEND_COLOR_A(0)); etna_set_state(ctx, VIVS_PE_ALPHA_OP, ETNA_MASKED_BIT(VIVS_PE_ALPHA_OP_ALPHA_TEST, 0)); etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_CULL_FACE_MODE, OFF)); etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 0)); etna_set_state(ctx, VIVS_PE_STENCIL_CONFIG, ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_REF_FRONT, 0) & ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_MASK_FRONT, 0xff) & ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_WRITE_MASK, 0xff) & ETNA_MASKED_INL(VIVS_PE_STENCIL_CONFIG_MODE, DISABLED)); etna_set_state(ctx, VIVS_PE_STENCIL_OP, ETNA_MASKED(VIVS_PE_STENCIL_OP_FUNC_FRONT, COMPARE_FUNC_ALWAYS) & ETNA_MASKED(VIVS_PE_STENCIL_OP_FUNC_BACK, COMPARE_FUNC_ALWAYS) & ETNA_MASKED(VIVS_PE_STENCIL_OP_FAIL_FRONT, STENCIL_OP_KEEP) & ETNA_MASKED(VIVS_PE_STENCIL_OP_FAIL_BACK, STENCIL_OP_KEEP) & ETNA_MASKED(VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT, STENCIL_OP_KEEP) & ETNA_MASKED(VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK, STENCIL_OP_KEEP) & ETNA_MASKED(VIVS_PE_STENCIL_OP_PASS_FRONT, STENCIL_OP_KEEP) & ETNA_MASKED(VIVS_PE_STENCIL_OP_PASS_BACK, STENCIL_OP_KEEP)); etna_set_state(ctx, VIVS_PE_COLOR_FORMAT, ETNA_MASKED(VIVS_PE_COLOR_FORMAT_COMPONENTS, 0xf)); etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_EARLY_Z, 0)); etna_set_state(ctx, VIVS_SE_DEPTH_SCALE, 0x0); etna_set_state(ctx, VIVS_SE_DEPTH_BIAS, 0x0); etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_FILL_MODE, SOLID)); etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_SHADE_MODEL, SMOOTH)); etna_set_state(ctx, VIVS_PE_COLOR_FORMAT, ETNA_MASKED(VIVS_PE_COLOR_FORMAT_FORMAT, RS_FORMAT_X8R8G8B8) & ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_SUPER_TILED, supertiled)); etna_set_state(ctx, VIVS_PE_COLOR_ADDR, rt->address); /* ADDR_A */ etna_set_state(ctx, VIVS_PE_COLOR_STRIDE, padded_width * 4); etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG, ETNA_MASKED_INL(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES, NONE) & ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES, 0xf) & ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12, 0x0) & ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16, 0x0) ); etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR); etna_set_state(ctx, VIVS_PE_COLOR_FORMAT, ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_PARTIAL, 1)); etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR); etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0); etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */ etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */ etna_set_state(ctx, VIVS_TS_MEM_CONFIG, VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR); etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT, D16) & ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_SUPER_TILED, supertiled) ); etna_set_state(ctx, VIVS_PE_DEPTH_ADDR, z->address); /* ADDR_C */ etna_set_state(ctx, VIVS_PE_DEPTH_STRIDE, padded_width * 2); etna_set_state(ctx, VIVS_PE_HDEPTH_CONTROL, VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED); etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0); etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_EARLY_Z, 0)); etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_DEPTH); etna_set_state(ctx, VIVS_TS_DEPTH_CLEAR_VALUE, 0xffffffff); etna_set_state(ctx, VIVS_TS_DEPTH_STATUS_BASE, z_ts->address); /* ADDR_D */ etna_set_state(ctx, VIVS_TS_DEPTH_SURFACE_BASE, z->address); /* ADDR_C */ etna_set_state(ctx, VIVS_TS_MEM_CONFIG, VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR | VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR | VIVS_TS_MEM_CONFIG_DEPTH_16BPP | VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION); etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_EARLY_Z, 1)); /* flip-flopping once again */ /* Warm up RS on aux render target */ etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH); etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address); etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */ etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */ etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH); etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address); etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */ etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */ etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH); etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH); etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address); etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */ etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */ etna_stall(ctx, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE); /* Set up the resolve to clear tile status for main render target * Regard the TS as an image of width 16 with 4 bytes per pixel (64 bytes per row) * XXX need to clear the depth ts too. * */ etna_set_state(ctx, VIVS_RS_CONFIG, (RS_FORMAT_X8R8G8B8 << VIVS_RS_CONFIG_SOURCE_FORMAT__SHIFT) | (RS_FORMAT_X8R8G8B8 << VIVS_RS_CONFIG_DEST_FORMAT__SHIFT) ); etna_set_state_multi(ctx, VIVS_RS_DITHER(0), 2, (uint32_t[]) { 0xffffffff, 0xffffffff }); etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt_ts->address); /* ADDR_B */ etna_set_state(ctx, VIVS_RS_DEST_STRIDE, 0x40); etna_set_state(ctx, VIVS_RS_WINDOW_SIZE, ((rt_ts_size/0x40) << VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT) | (16 << VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT)); etna_set_state(ctx, VIVS_RS_FILL_VALUE(0), (bits_per_tile==4)?0x11111111:0x55555555); etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1 | (0xffff << VIVS_RS_CLEAR_CONTROL_BITS__SHIFT)); etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0); /* no AA, no endian switch */ etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb); /** Done */ etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0xff7f7f7f); etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */ etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */ etna_set_state(ctx, VIVS_TS_MEM_CONFIG, VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR | VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR | VIVS_TS_MEM_CONFIG_DEPTH_16BPP | VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION); etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_CULL_FACE_MODE, CCW)); etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH); etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 0)); etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_MODE, NONE)); etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 0)); etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED(VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC, COMPARE_FUNC_ALWAYS)); etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_MODE, Z)); etna_set_state_f32(ctx, VIVS_PE_DEPTH_NEAR, 0.0); etna_set_state_f32(ctx, VIVS_PE_DEPTH_FAR, 1.0); etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0); /* set up primitive assembly */ etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_OFFSET_Z, 0.0); etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_SCALE_Z, 1.0); etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH, 0)); etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_X, width << 15); etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_Y, height << 15); etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_X, width << 15); etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_Y, height << 15); etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_LEFT, 0); etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_TOP, 0); etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_RIGHT, (width << 16) | 5); etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_BOTTOM, (height << 16) | 5); /* shader setup */ etna_set_state(ctx, VIVS_VS_END_PC, vs_size/16); etna_set_state_multi(ctx, VIVS_VS_INPUT_COUNT, 3, (uint32_t[]) { /* VIVS_VS_INPUT_COUNT */ (1<<8) | 3, /* VIVS_VS_TEMP_REGISTER_CONTROL */ 6 << VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT, /* VIVS_VS_OUTPUT(0) */ 4 }); etna_set_state(ctx, VIVS_VS_START_PC, 0x0); etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(45), 0.5); /* u11.y */ etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(44), 1.0); /* u11.x */ etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(27), 0.0); /* u6.w */ etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(23), 20.0); /* u5.w */ etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(19), 2.0); /* u4.w */ /* Now load the shader itself */ etna_set_state_multi(ctx, VIVS_VS_INST_MEM(0), vs_size/4, vs); etna_set_state(ctx, VIVS_RA_CONTROL, 0x1); etna_set_state_multi(ctx, VIVS_PS_END_PC, 2, (uint32_t[]) { /* VIVS_PS_END_PC */ ps_size/16, /* VIVS_PS_OUTPUT_REG */ 0x1 }); etna_set_state(ctx, VIVS_PS_START_PC, 0x0); etna_set_state(ctx, VIVS_PA_SHADER_ATTRIBUTES(0), 0x200); etna_set_state(ctx, VIVS_GL_VARYING_NUM_COMPONENTS, /* one varying, with four components */ (4 << VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__SHIFT) ); etna_set_state_multi(ctx, VIVS_GL_VARYING_COMPONENT_USE(0), 2, (uint32_t[]) { /* one varying, with four components */ (VARYING_COMPONENT_USE_USED << VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT) | (VARYING_COMPONENT_USE_USED << VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT) | (VARYING_COMPONENT_USE_USED << VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT) | (VARYING_COMPONENT_USE_USED << VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT) , 0 }); etna_set_state_multi(ctx, VIVS_PS_INST_MEM(0), ps_size/4, ps); etna_set_state(ctx, VIVS_PS_INPUT_COUNT, (31<<8)|2); etna_set_state(ctx, VIVS_PS_TEMP_REGISTER_CONTROL, (2 << VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT)); etna_set_state(ctx, VIVS_PS_CONTROL, VIVS_PS_CONTROL_UNK1 ); etna_set_state(ctx, VIVS_PA_ATTRIBUTE_ELEMENT_COUNT, 0x100); etna_set_state(ctx, VIVS_GL_VARYING_TOTAL_COMPONENTS, /* one varying, with four components */ VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(4) ); etna_set_state(ctx, VIVS_VS_LOAD_BALANCING, 0xf3f0582); etna_set_state(ctx, VIVS_VS_OUTPUT_COUNT, 2); etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_POINT_SIZE_ENABLE, 0)); /* Compute transform matrices in the same way as cube egl demo */ ESMatrix modelview; esMatrixLoadIdentity(&modelview); esTranslate(&modelview, 0.0f, 0.0f, -8.0f); esRotate(&modelview, 45.0f, 1.0f, 0.0f, 0.0f); esRotate(&modelview, 45.0f, 0.0f, 1.0f, 0.0f); esRotate(&modelview, frame*0.5f, 0.0f, 0.0f, 1.0f); GLfloat aspect = (GLfloat)(height) / (GLfloat)(width); ESMatrix projection; esMatrixLoadIdentity(&projection); esFrustum(&projection, -2.8f, +2.8f, -2.8f * aspect, +2.8f * aspect, 6.0f, 10.0f); ESMatrix modelviewprojection; esMatrixLoadIdentity(&modelviewprojection); esMatrixMultiply(&modelviewprojection, &modelview, &projection); ESMatrix inverse, normal; /* compute inverse transpose normal transformation matrix */ esMatrixInverse3x3(&inverse, &modelview); esMatrixTranspose(&normal, &inverse); etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(0), 16, (uint32_t*)&modelviewprojection.m[0][0]); etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(16), 3, (uint32_t*)&normal.m[0][0]); /* u4.xyz */ etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(20), 3, (uint32_t*)&normal.m[1][0]); /* u5.xyz */ etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(24), 3, (uint32_t*)&normal.m[2][0]); /* u6.xyz */ etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(28), 16, (uint32_t*)&modelview.m[0][0]); etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_BASE_ADDR, vtx->address); /* ADDR_E */ etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_CONTROL, 0x24 << VIVS_FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT); etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(0), VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT | (ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) | (0 << VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT) | (3 <<VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT) | VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF | (0x0 << VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT) | (0xc << VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT)); etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(1), VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT | (ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) | (0 << VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT) | (3 <<VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT) | VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF | (0xc << VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT) | (0x18 << VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT)); etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(2), VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT | (ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) | VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE | (0 << VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT) | (3 <<VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT) | VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF | (0x18 << VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT) | (0x24 << VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT)); etna_set_state(ctx, VIVS_VS_INPUT(0), 0x20100); etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_POINT_SPRITE_ENABLE, 0)); for(int prim=0; prim<6; ++prim) { etna_draw_primitives(ctx, PRIMITIVE_TYPE_TRIANGLE_STRIP, prim*4, 2); } etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH); etna_flush(ctx); etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH); etna_set_state(ctx, VIVS_RS_CONFIG, VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_X8R8G8B8) | VIVS_RS_CONFIG_SOURCE_TILED | VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_X8R8G8B8) | VIVS_RS_CONFIG_DEST_TILED); etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | (supertiled?VIVS_RS_SOURCE_STRIDE_TILING:0)); etna_set_state(ctx, VIVS_RS_DEST_STRIDE, (padded_width * 4 * 4) | (supertiled?VIVS_RS_DEST_STRIDE_TILING:0)); etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff); etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff); etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED); etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0); /* no AA, no endian switch */ etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address); /* ADDR_A */ etna_set_state(ctx, VIVS_RS_DEST_ADDR, rt->address); /* ADDR_A */ etna_set_state(ctx, VIVS_RS_WINDOW_SIZE, VIVS_RS_WINDOW_SIZE_HEIGHT(padded_height) | VIVS_RS_WINDOW_SIZE_WIDTH(padded_width)); etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb); /* Submit second command buffer */ etna_flush(ctx); etna_warm_up_rs(ctx, aux_rt->address, aux_rt_ts->address); etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts->address); /* ADDR_B */ etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt->address); /* ADDR_A */ etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR); etna_set_state(ctx, VIVS_TS_MEM_CONFIG, VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR | VIVS_TS_MEM_CONFIG_DEPTH_16BPP | VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION); etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR); etna_set_state(ctx, VIVS_PE_COLOR_FORMAT, ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_PARTIAL, 0)); /* Submit third command buffer, wait for pixel engine to finish */ etna_finish(ctx); etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH); etna_set_state(ctx, VIVS_RS_CONFIG, VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_X8R8G8B8) | VIVS_RS_CONFIG_SOURCE_TILED | VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_X8R8G8B8) /*| VIVS_RS_CONFIG_SWAP_RB*/); etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | (supertiled?VIVS_RS_SOURCE_STRIDE_TILING:0)); etna_set_state(ctx, VIVS_RS_DEST_STRIDE, width * 4); etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff); etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff); etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED); etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0); /* no AA, no endian switch */ etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, rt->address); etna_set_state(ctx, VIVS_RS_DEST_ADDR, bmp->address); etna_set_state(ctx, VIVS_RS_WINDOW_SIZE, VIVS_RS_WINDOW_SIZE_HEIGHT(height) | VIVS_RS_WINDOW_SIZE_WIDTH(width)); etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb); etna_finish(ctx); } bmp_dump32(bmp->logical, width, height, false, "/tmp/fb.bmp"); printf("Dump complete\n"); /* Unlock video memory */ if(etna_vidmem_unlock(bmp) != 0) { fprintf(stderr, "Cannot unlock vidmem\n"); exit(1); } etna_free(ctx); viv_close(); return 0; }
static int etna_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param) { struct etna_screen *screen = etna_screen(pscreen); switch (shader) { case PIPE_SHADER_FRAGMENT: case PIPE_SHADER_VERTEX: break; case PIPE_SHADER_COMPUTE: case PIPE_SHADER_GEOMETRY: case PIPE_SHADER_TESS_CTRL: case PIPE_SHADER_TESS_EVAL: return 0; default: DBG("unknown shader type %d", shader); return 0; } switch (param) { case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: return ETNA_MAX_TOKENS; case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: return ETNA_MAX_DEPTH; /* XXX */ case PIPE_SHADER_CAP_MAX_INPUTS: /* Maximum number of inputs for the vertex shader is the number * of vertex elements - each element defines one vertex shader * input register. For the fragment shader, this is the number * of varyings. */ return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings : screen->specs.vertex_max_elements; case PIPE_SHADER_CAP_MAX_OUTPUTS: return 16; /* see VIVS_VS_OUTPUT */ case PIPE_SHADER_CAP_MAX_TEMPS: return 64; /* Max native temporaries. */ case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: return 1; case PIPE_SHADER_CAP_MAX_PREDS: return 0; /* nothing uses this */ case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: return 1; case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: return 1; case PIPE_SHADER_CAP_SUBROUTINES: return 0; case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG); case PIPE_SHADER_CAP_INTEGERS: return 0; case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: return shader == PIPE_SHADER_FRAGMENT ? screen->specs.fragment_sampler_count : screen->specs.vertex_sampler_count; case PIPE_SHADER_CAP_PREFERRED_IR: return PIPE_SHADER_IR_TGSI; case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: return 4096; case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: return false; case PIPE_SHADER_CAP_SUPPORTED_IRS: return 0; case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: return 32; case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: return 0; } debug_printf("unknown shader param %d", param); return 0; }
static int etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) { struct etna_screen *screen = etna_screen(pscreen); switch (param) { /* Supported features (boolean caps). */ case PIPE_CAP_TWO_SIDED_STENCIL: case PIPE_CAP_ANISOTROPIC_FILTER: case PIPE_CAP_POINT_SPRITE: case PIPE_CAP_TEXTURE_SHADOW_MAP: case PIPE_CAP_BLEND_EQUATION_SEPARATE: case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: case PIPE_CAP_SM3: case PIPE_CAP_TEXTURE_BARRIER: case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_USER_CONSTANT_BUFFERS: case PIPE_CAP_TGSI_TEXCOORD: case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: return 1; /* Memory */ case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: return 256; case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: return 4; /* XXX could easily be supported */ case PIPE_CAP_GLSL_FEATURE_LEVEL: return 120; case PIPE_CAP_NPOT_TEXTURES: return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1, NON_POWER_OF_TWO); */ case PIPE_CAP_PRIMITIVE_RESTART: return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); case PIPE_CAP_ENDIANNESS: return PIPE_ENDIAN_LITTLE; /* on most Viv hw this is configurable (feature ENDIANNESS_CONFIG) */ /* Unsupported features. */ case PIPE_CAP_SEAMLESS_CUBE_MAP: case PIPE_CAP_TEXTURE_SWIZZLE: /* XXX supported on gc2000 */ case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */ case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */ case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */ case PIPE_CAP_TGSI_INSTANCEID: /* no idea, really */ case PIPE_CAP_START_INSTANCE: /* instancing not supported AFAIK */ case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* instancing not supported AFAIK */ case PIPE_CAP_SHADER_STENCIL_EXPORT: /* Fragment shader cannot export stencil value */ case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */ case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */ case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */ case PIPE_CAP_INDEP_BLEND_ENABLE: case PIPE_CAP_INDEP_BLEND_FUNC: case PIPE_CAP_DEPTH_CLIP_DISABLE: case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: /* Don't skip strict max uniform limit check */ case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: case PIPE_CAP_VERTEX_COLOR_CLAMPED: case PIPE_CAP_USER_VERTEX_BUFFERS: case PIPE_CAP_USER_INDEX_BUFFERS: case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: /* TODO: test me out with piglit */ case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: case PIPE_CAP_TEXTURE_GATHER_SM5: case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: case PIPE_CAP_FAKE_SW_MSAA: case PIPE_CAP_TEXTURE_QUERY_LOD: case PIPE_CAP_SAMPLE_SHADING: case PIPE_CAP_TEXTURE_GATHER_OFFSETS: case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: case PIPE_CAP_DRAW_INDIRECT: case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: case PIPE_CAP_SAMPLER_VIEW_TARGET: case PIPE_CAP_CLIP_HALFZ: case PIPE_CAP_VERTEXID_NOBASE: case PIPE_CAP_POLYGON_OFFSET_CLAMP: case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: case PIPE_CAP_TEXTURE_FLOAT_LINEAR: case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: case PIPE_CAP_DEPTH_BOUNDS_TEST: case PIPE_CAP_TGSI_TXQS: case PIPE_CAP_FORCE_PERSAMPLE_INTERP: case PIPE_CAP_SHAREABLE_SHADERS: case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: case PIPE_CAP_CLEAR_TEXTURE: case PIPE_CAP_DRAW_PARAMETERS: case PIPE_CAP_TGSI_PACK_HALF_FLOAT: case PIPE_CAP_MULTI_DRAW_INDIRECT: case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: case PIPE_CAP_INVALIDATE_BUFFER: case PIPE_CAP_GENERATE_MIPMAP: case PIPE_CAP_STRING_MARKER: case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: case PIPE_CAP_QUERY_BUFFER_OBJECT: case PIPE_CAP_QUERY_MEMORY_INFO: case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: case PIPE_CAP_CULL_DISTANCE: case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: case PIPE_CAP_TGSI_VOTE: case PIPE_CAP_MAX_WINDOW_RECTANGLES: case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED: case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS: case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: case PIPE_CAP_TGSI_ARRAY_COMPONENTS: case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS: case PIPE_CAP_TGSI_CAN_READ_OUTPUTS: case PIPE_CAP_NATIVE_FENCE_FD: case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY: case PIPE_CAP_TGSI_FS_FBFETCH: case PIPE_CAP_TGSI_MUL_ZERO_WINS: case PIPE_CAP_DOUBLES: case PIPE_CAP_INT64: case PIPE_CAP_INT64_DIVMOD: return 0; /* Stream output. */ case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: return 0; /* Geometry shader output, unsupported. */ case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES: case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS: case PIPE_CAP_MAX_VERTEX_STREAMS: return 0; case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: return 128; /* Texturing. */ case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: { int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size); assert(log2_max_tex_size > 0); return log2_max_tex_size; } case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */ return 5; case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: return 0; case PIPE_CAP_CUBE_MAP_ARRAY: return 0; case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: case PIPE_CAP_MIN_TEXEL_OFFSET: return -8; case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET: case PIPE_CAP_MAX_TEXEL_OFFSET: return 7; case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: return 0; case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: return 65536; /* Render targets. */ case PIPE_CAP_MAX_RENDER_TARGETS: return 1; /* Viewports and scissors. */ case PIPE_CAP_MAX_VIEWPORTS: return 1; /* Timer queries. */ case PIPE_CAP_QUERY_TIME_ELAPSED: case PIPE_CAP_OCCLUSION_QUERY: return 0; case PIPE_CAP_QUERY_TIMESTAMP: return 1; case PIPE_CAP_QUERY_PIPELINE_STATISTICS: return 0; /* Preferences */ case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: return 0; case PIPE_CAP_PCI_GROUP: case PIPE_CAP_PCI_BUS: case PIPE_CAP_PCI_DEVICE: case PIPE_CAP_PCI_FUNCTION: return 0; case PIPE_CAP_VENDOR_ID: case PIPE_CAP_DEVICE_ID: return 0xFFFFFFFF; case PIPE_CAP_ACCELERATED: return 1; case PIPE_CAP_VIDEO_MEMORY: return 0; case PIPE_CAP_UMA: return 1; } debug_printf("unknown param %d", param); return 0; }
/* Allocate 2D texture or render target resource */ static struct pipe_resource * etna_screen_resource_create(struct pipe_screen *screen, const struct pipe_resource *templat) { struct etna_screen *priv = etna_screen(screen); assert(templat); /* Check input */ if(templat->target == PIPE_TEXTURE_CUBE) { assert(templat->array_size == 6); } else if (templat->target == PIPE_BUFFER) { assert(templat->format == PIPE_FORMAT_R8_UNORM); /* bytes; want TYPELESS or similar */ assert(templat->array_size == 1); assert(templat->height0 == 1); assert(templat->depth0 == 1); assert(templat->array_size == 1); assert(templat->last_level == 0); } else { assert(templat->array_size == 1); } assert(templat->width0 != 0); assert(templat->height0 != 0); assert(templat->depth0 != 0); assert(templat->array_size != 0); /* Figure out what tiling to use -- for now, assume that textures cannot be supertiled, and cannot be linear. * There is a feature flag SUPERTILED_TEXTURE (not supported on any known hw) that may allow this, as well * as LINEAR_TEXTURE_SUPPORT (supported on gc880 and gc2000 at least), but not sure how it works. * Buffers always have LINEAR layout. */ unsigned layout = ETNA_LAYOUT_LINEAR; if(templat->target != PIPE_BUFFER) { if(!(templat->bind & PIPE_BIND_SAMPLER_VIEW) && priv->specs.can_supertile && !DBG_ENABLED(ETNA_DBG_NO_SUPERTILE)) layout = ETNA_LAYOUT_SUPER_TILED; else layout = ETNA_LAYOUT_TILED; } /* XXX multi tiled formats */ /* Determine scaling for antialiasing, allow override using debug flag */ int nr_samples = templat->nr_samples; if((templat->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) && !(templat->bind & PIPE_BIND_SAMPLER_VIEW)) { if(DBG_ENABLED(ETNA_DBG_MSAA_2X)) nr_samples = 2; if(DBG_ENABLED(ETNA_DBG_MSAA_4X)) nr_samples = 4; } int msaa_xscale = 1, msaa_yscale = 1; if(!translate_samples_to_xyscale(nr_samples, &msaa_xscale, &msaa_yscale, NULL)) { /* Number of samples not supported */ return NULL; } /* Determine needed padding (alignment of height/width) */ unsigned paddingX = 0, paddingY = 0; unsigned halign = TEXTURE_HALIGN_FOUR; etna_layout_multiple(layout, priv->dev->chip.pixel_pipes, (templat->bind & PIPE_BIND_SAMPLER_VIEW) && !VIV_FEATURE(priv->dev, chipMinorFeatures1, TEXTURE_HALIGN), &paddingX, &paddingY, &halign); assert(paddingX && paddingY); /* compute mipmap level sizes and offsets */ struct etna_resource *resource = CALLOC_STRUCT(etna_resource); int max_mip_level = templat->last_level; if(unlikely(max_mip_level >= ETNA_NUM_LOD)) /* max LOD supported by hw */ max_mip_level = ETNA_NUM_LOD - 1; unsigned ix = 0; unsigned x = templat->width0, y = templat->height0; unsigned offset = 0; while(true) { struct etna_resource_level *mip = &resource->levels[ix]; mip->width = x; mip->height = y; mip->padded_width = align(x * msaa_xscale, paddingX); mip->padded_height = align(y * msaa_yscale, paddingY); mip->stride = util_format_get_stride(templat->format, mip->padded_width); mip->offset = offset; mip->layer_stride = mip->stride * util_format_get_nblocksy(templat->format, mip->padded_height); mip->size = templat->array_size * mip->layer_stride; offset += align(mip->size, ETNA_PE_ALIGNMENT); /* align mipmaps to 64 bytes to be able to render to them */ if(ix == max_mip_level || (x == 1 && y == 1)) break; // stop at last level x = u_minify(x, 1); y = u_minify(y, 1); ix += 1; } /* determine memory type */ uint32_t flags = 0; /* XXX DRM_ETNA_GEM_CACHE_xxx */ enum viv_surf_type memtype = VIV_SURF_UNKNOWN; if(templat->bind & PIPE_BIND_SAMPLER_VIEW) flags |= DRM_ETNA_GEM_TYPE_TEX; else if(templat->bind & PIPE_BIND_RENDER_TARGET) flags |= DRM_ETNA_GEM_TYPE_RT; else if(templat->bind & PIPE_BIND_DEPTH_STENCIL) flags |= DRM_ETNA_GEM_TYPE_ZS; else if(templat->bind & PIPE_BIND_INDEX_BUFFER) flags |= DRM_ETNA_GEM_TYPE_IDX; else if(templat->bind & PIPE_BIND_VERTEX_BUFFER) flags |= DRM_ETNA_GEM_TYPE_VTX; DBG_F(ETNA_DBG_RESOURCE_MSGS, "%p: Allocate surface of %ix%i (padded to %ix%i), %i layers, of format %s, size %08x flags %08x, memtype %i", resource, templat->width0, templat->height0, resource->levels[0].padded_width, resource->levels[0].padded_height, templat->array_size, util_format_name(templat->format), offset, templat->bind, memtype); struct etna_bo *bo = 0; if(unlikely((bo = etna_bo_new(priv->dev, offset, flags)) == NULL)) { BUG("Problem allocating video memory for resource"); return NULL; } resource->base = *templat; resource->base.last_level = ix; /* real last mipmap level */ resource->base.screen = screen; resource->base.nr_samples = nr_samples; resource->layout = layout; resource->halign = halign; resource->bo = bo; resource->ts_bo = 0; /* TS is only created when first bound to surface */ pipe_reference_init(&resource->base.reference, 1); if(DBG_ENABLED(ETNA_DBG_ZERO)) { void *map = etna_bo_map(bo); memset(map, 0, offset); } return &resource->base; }
int main(int argc, char **argv) { int width, height; int width_s, height_s; int padded_width, padded_height; int backbuffer = 0; int supersample_x = 2; // 1 or 2 int supersample_y = 2; // 1 or 2 int extra_ps_inputs = 0; struct fbdemos_scaffold *fbs = 0; fbdemo_init(&fbs); width = fbs->width; height = fbs->height; struct viv_conn *conn = fbs->conn; bool supertiled = VIV_FEATURE(conn, chipMinorFeatures0,SUPER_TILED); unsigned bits_per_tile = VIV_FEATURE(conn, chipMinorFeatures0,2BITPERTILE)?2:4; printf("supertiled: %i bits per tile: %i\n", supertiled, bits_per_tile); width_s = width * supersample_x; height_s = height * supersample_y; padded_width = etna_align_up(width_s, 64); padded_height = etna_align_up(height_s, 64); extra_ps_inputs = (supersample_x > 1 || supersample_y > 1); // in case of supersample, there is an extra input to PS printf("padded_width %i padded_height %i\n", padded_width, padded_height); struct etna_bo *rt = 0; /* main render target */ struct etna_bo *rt_ts = 0; /* tile status for main render target */ struct etna_bo *z = 0; /* depth for main render target */ struct etna_bo *z_ts = 0; /* depth ts for main render target */ struct etna_bo *vtx = 0; /* vertex buffer */ struct etna_bo *idx = 0; /* index buffer */ struct etna_bo *aux_rt = 0; /* auxilary render target */ struct etna_bo *aux_rt_ts = 0; /* tile status for auxilary render target */ struct etna_bo *tex = 0; /* texture */ struct etna_bo *bmp = 0; /* bitmap */ /* TODO: anti aliasing (doubles width/height) */ size_t rt_size = padded_width * padded_height * 4; size_t rt_ts_size = etna_align_up((padded_width * padded_height * 4)*bits_per_tile/0x80, 0x100); size_t z_size = padded_width * padded_height * 2; size_t z_ts_size = etna_align_up((padded_width * padded_height * 2)*bits_per_tile/0x80, 0x100); size_t bmp_size = width * height * 4; if((rt=etna_bo_new(conn, rt_size, DRM_ETNA_GEM_TYPE_RT))==NULL || (rt_ts=etna_bo_new(conn, rt_ts_size, DRM_ETNA_GEM_TYPE_TS))==NULL || (z=etna_bo_new(conn, z_size, DRM_ETNA_GEM_TYPE_ZS))==NULL || (z_ts=etna_bo_new(conn, z_ts_size, DRM_ETNA_GEM_TYPE_TS))==NULL || (vtx=etna_bo_new(conn, VERTEX_BUFFER_SIZE, DRM_ETNA_GEM_TYPE_VTX))==NULL || (idx=etna_bo_new(conn, INDEX_BUFFER_SIZE, DRM_ETNA_GEM_TYPE_IDX))==NULL || (aux_rt=etna_bo_new(conn, 0x4000, DRM_ETNA_GEM_TYPE_RT))==NULL || (aux_rt_ts=etna_bo_new(conn, 0x100, DRM_ETNA_GEM_TYPE_TS))==NULL || (tex=etna_bo_new(conn, 0x100000, DRM_ETNA_GEM_TYPE_TEX))==NULL || (bmp=etna_bo_new(conn, bmp_size, DRM_ETNA_GEM_TYPE_BMP))==NULL ) { fprintf(stderr, "Error allocating video memory\n"); exit(1); } /* Phew, now we got all the memory we need. * Write interleaved attribute vertex stream. * Unlike the GL example we only do this once, not every time glDrawArrays is called, the same would be accomplished * from GL by using a vertex buffer object. */ memset(etna_bo_map(vtx), 0, VERTEX_BUFFER_SIZE); #ifndef INDEXED printf("Interleaving vertices...\n"); float *vertices_array = companion_vertices_array(); float *texture_coordinates_array = companion_texture_coordinates_array(); float *normals_array = companion_normals_array(); assert(COMPANION_ARRAY_COUNT*(3+3+2)*sizeof(float) < VERTEX_BUFFER_SIZE); float *vtx_map = (float*)etna_bo_map(vtx); for(int vert=0; vert<COMPANION_ARRAY_COUNT; ++vert) { int dest_idx = vert * (3 + 3 + 2); for(int comp=0; comp<3; ++comp) vtx_map[dest_idx+comp+0] = vertices_array[vert*3 + comp]; /* 0 */ for(int comp=0; comp<3; ++comp) vtx_map[dest_idx+comp+3] = normals_array[vert*3 + comp]; /* 1 */ for(int comp=0; comp<2; ++comp) vtx_map[dest_idx+comp+6] = texture_coordinates_array[vert*2 + comp]; /* 2 */ } #else printf("Interleaving vertices and copying index buffer...\n"); assert(COMPANION_VERTEX_COUNT*(3+3+2)*sizeof(float) < VERTEX_BUFFER_SIZE); float *vtx_map = (float*)etna_bo_map(vtx); for(int vert=0; vert<COMPANION_VERTEX_COUNT; ++vert) { int dest_idx = vert * (3 + 3 + 2); for(int comp=0; comp<3; ++comp) vtx_map[dest_idx+comp+0] = companion_vertices[vert][comp]; /* 0 */ for(int comp=0; comp<3; ++comp) vtx_map[dest_idx+comp+3] = companion_normals[vert][comp]; /* 1 */ for(int comp=0; comp<2; ++comp) vtx_map[dest_idx+comp+6] = companion_texture_coordinates[vert][comp]; /* 2 */ } assert(COMPANION_TRIANGLE_COUNT*3*sizeof(unsigned short) < INDEX_BUFFER_SIZE); memcpy(etna_bo_map(idx), &companion_triangles[0][0], COMPANION_TRIANGLE_COUNT*3*sizeof(unsigned short)); #endif /* Fill in texture (convert from RGB linear to tiled) */ #define TILE_WIDTH (4) #define TILE_HEIGHT (4) #define TILE_WORDS (TILE_WIDTH*TILE_HEIGHT) unsigned ytiles = COMPANION_TEXTURE_HEIGHT / TILE_HEIGHT; unsigned xtiles = COMPANION_TEXTURE_WIDTH / TILE_WIDTH; unsigned dst_stride = xtiles * TILE_WORDS; uint32_t *tex_map = (uint32_t*)etna_bo_map(tex); for(unsigned ty=0; ty<ytiles; ++ty) { for(unsigned tx=0; tx<xtiles; ++tx) { unsigned ofs = ty * dst_stride + tx * TILE_WORDS; for(unsigned y=0; y<TILE_HEIGHT; ++y) { for(unsigned x=0; x<TILE_WIDTH; ++x) { unsigned srcy = ty*TILE_HEIGHT + y; unsigned srcx = tx*TILE_WIDTH + x; unsigned src_ofs = (srcy*COMPANION_TEXTURE_WIDTH+srcx)*3; unsigned r,g,b,a; #ifndef TEST_PATTERN /* actual texture */ r = ((uint8_t*)companion_texture)[src_ofs+0]; g = ((uint8_t*)companion_texture)[src_ofs+1]; b = ((uint8_t*)companion_texture)[src_ofs+2]; #else /* test pattern */ r = srcx; g = srcy; b = 0; #endif a = 255; tex_map[ofs] = ((a&0xFF) << 24) | ((b&0xFF) << 16) | ((g&0xFF) << 8) | (r&0xFF); ofs += 1; } } } } struct etna_ctx *ctx = 0; if(etna_create(conn, &ctx) != ETNA_OK) { printf("Unable to create context\n"); exit(1); } for(int frame=0; frame<1000; ++frame) { printf("*** FRAME %i ****\n", frame); /* XXX part of this can be put outside the loop, but until we have usable context management * this is safest. */ etna_set_state(ctx, VIVS_GL_VERTEX_ELEMENT_CONFIG, 0x1); etna_set_state(ctx, VIVS_RA_CONTROL, 0x1); etna_set_state(ctx, VIVS_PA_W_CLIP_LIMIT, 0x34000001); etna_set_state(ctx, VIVS_PA_SYSTEM_MODE, 0x11); etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_UNK22, 0)); etna_set_state(ctx, VIVS_SE_CONFIG, 0x0); etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR); etna_set_state(ctx, VIVS_PE_ALPHA_CONFIG, ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR, 0) & ETNA_MASKED_BIT(VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA, 0) & ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR, BLEND_FUNC_ONE) & ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA, BLEND_FUNC_ONE) & ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR, BLEND_FUNC_ZERO) & ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA, BLEND_FUNC_ZERO) & ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_EQ_COLOR, BLEND_EQ_ADD) & ETNA_MASKED(VIVS_PE_ALPHA_CONFIG_EQ_ALPHA, BLEND_EQ_ADD)); etna_set_state(ctx, VIVS_PE_ALPHA_BLEND_COLOR, VIVS_PE_ALPHA_BLEND_COLOR_B(0) | VIVS_PE_ALPHA_BLEND_COLOR_G(0) | VIVS_PE_ALPHA_BLEND_COLOR_R(0) | VIVS_PE_ALPHA_BLEND_COLOR_A(0)); etna_set_state(ctx, VIVS_PE_ALPHA_OP, ETNA_MASKED_BIT(VIVS_PE_ALPHA_OP_ALPHA_TEST, 0)); etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_CULL_FACE_MODE, CCW)); etna_set_state(ctx, VIVS_PE_STENCIL_CONFIG, ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_REF_FRONT, 0) & ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_MASK_FRONT, 0xff) & ETNA_MASKED(VIVS_PE_STENCIL_CONFIG_WRITE_MASK, 0xff) & ETNA_MASKED_INL(VIVS_PE_STENCIL_CONFIG_MODE, DISABLED)); etna_set_state(ctx, VIVS_PE_STENCIL_OP, ETNA_MASKED(VIVS_PE_STENCIL_OP_FUNC_FRONT, COMPARE_FUNC_ALWAYS) & ETNA_MASKED(VIVS_PE_STENCIL_OP_FUNC_BACK, COMPARE_FUNC_ALWAYS) & ETNA_MASKED(VIVS_PE_STENCIL_OP_FAIL_FRONT, STENCIL_OP_KEEP) & ETNA_MASKED(VIVS_PE_STENCIL_OP_FAIL_BACK, STENCIL_OP_KEEP) & ETNA_MASKED(VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT, STENCIL_OP_KEEP) & ETNA_MASKED(VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK, STENCIL_OP_KEEP) & ETNA_MASKED(VIVS_PE_STENCIL_OP_PASS_FRONT, STENCIL_OP_KEEP) & ETNA_MASKED(VIVS_PE_STENCIL_OP_PASS_BACK, STENCIL_OP_KEEP)); etna_set_state(ctx, VIVS_SE_DEPTH_SCALE, 0x0); etna_set_state(ctx, VIVS_SE_DEPTH_BIAS, 0x0); etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_INL(VIVS_PA_CONFIG_FILL_MODE, SOLID) & ETNA_MASKED_INL(VIVS_PA_CONFIG_SHADE_MODEL, SMOOTH)); etna_set_state(ctx, VIVS_PE_COLOR_FORMAT, ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_OVERWRITE, 0) & ETNA_MASKED(VIVS_PE_COLOR_FORMAT_COMPONENTS, 0xf) & ETNA_MASKED(VIVS_PE_COLOR_FORMAT_FORMAT, RS_FORMAT_X8R8G8B8) & ETNA_MASKED_BIT(VIVS_PE_COLOR_FORMAT_SUPER_TILED, supertiled)); etna_set_state(ctx, VIVS_PE_COLOR_ADDR, etna_bo_gpu_address(rt)); etna_set_state(ctx, VIVS_PE_COLOR_STRIDE, padded_width * 4); uint32_t ts_msaa_config; if(supersample_x == 2 && supersample_y == 2) { // 4X MSAA etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG, ETNA_MASKED_INL(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES, 4X) & ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES, 0xf) & ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12, 0x0) & ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16, 0x0) ); etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E04, 0x0); etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E10(2), 0xaaa22a22); etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(8), 0x262a2288); etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(9), 0x886688a2); etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(10), 0x888866aa); etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(11), 0x668888a6); etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E10(1), 0xe6ae622a); etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(4), 0x46622a88); etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(5), 0x888888ae); etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(6), 0x888888e6); etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(7), 0x888888ca); etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E10(0), 0xeaa26e26); etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(0), 0x4a6e2688); etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(1), 0x888888a2); etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(2), 0x888888ea); etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(3), 0x888888c6); ts_msaa_config = VIVS_TS_MEM_CONFIG_MSAA | VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A8R8G8B8; } else if(supersample_x == 2 && supersample_y == 1) { // 2X MSAA etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG, ETNA_MASKED_INL(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES, 2X) & ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES, 0xf) & ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12, 0x0) & ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16, 0x0) ); etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E04, 0x0); etna_set_state(ctx, VIVS_RA_MULTISAMPLE_UNK00E10(0), 0xaa22); etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(0), 0x66aa2288); etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(1), 0x88558800); etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(2), 0x88881100); etna_set_state(ctx, VIVS_RA_CENTROID_TABLE(3), 0x33888800); ts_msaa_config = VIVS_TS_MEM_CONFIG_MSAA | VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A8R8G8B8; } else { // No multisampling etna_set_state(ctx, VIVS_GL_MULTI_SAMPLE_CONFIG, ETNA_MASKED_INL(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES, NONE) & ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES, 0xf) & ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12, 0x0) & ETNA_MASKED(VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16, 0x0) ); ts_msaa_config = 0; } etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR); etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0); etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, etna_bo_gpu_address(rt_ts)); etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, etna_bo_gpu_address(rt)); etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 0) & ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT, D16) & ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_SUPER_TILED, supertiled) & ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_EARLY_Z, 1)); etna_set_state(ctx, VIVS_PE_DEPTH_ADDR, etna_bo_gpu_address(z)); etna_set_state(ctx, VIVS_PE_DEPTH_STRIDE, padded_width * 2); etna_set_state(ctx, VIVS_PE_HDEPTH_CONTROL, VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED); etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0); etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_DEPTH); etna_set_state(ctx, VIVS_TS_DEPTH_CLEAR_VALUE, 0xffffffff); etna_set_state(ctx, VIVS_TS_DEPTH_STATUS_BASE, etna_bo_gpu_address(z_ts)); etna_set_state(ctx, VIVS_TS_DEPTH_SURFACE_BASE, etna_bo_gpu_address(z)); etna_set_state(ctx, VIVS_TS_MEM_CONFIG, VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR | VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR | VIVS_TS_MEM_CONFIG_DEPTH_16BPP | VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION | ts_msaa_config); #ifdef EXTRA_DELAYS /* Warm up RS on aux render target (is this needed?) */ etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH); etna_warm_up_rs(ctx, etna_bo_gpu_address(aux_rt), etna_bo_gpu_address(aux_rt_ts)); etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts_physical); etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt_physical); etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH); etna_warm_up_rs(ctx, aux_rt_physical, aux_rt_ts_physical); etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts_physical); etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt_physical); etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH); etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH); etna_warm_up_rs(ctx, aux_rt_physical, aux_rt_ts_physical); etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, rt_ts_physical); etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, rt_physical); #endif /* sync rasterizer to pixel engine after changes to PE config */ etna_stall(ctx, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE); /* Set up the resolve to clear tile status for main render target and depth * Regard the TS as an image of width 16 with 4 bytes per pixel (64 bytes per row) * */ etna_set_state(ctx, VIVS_RS_CONFIG, VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_A8R8G8B8) | VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_A8R8G8B8) ); etna_set_state_multi(ctx, VIVS_RS_DITHER(0), 2, (uint32_t[]){0xffffffff, 0xffffffff}); etna_set_state(ctx, VIVS_RS_FILL_VALUE(0), (bits_per_tile==4)?0x11111111:0x55555555); etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1 | (0xffff << VIVS_RS_CLEAR_CONTROL_BITS__SHIFT)); etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0); /* clear color ts */ etna_set_state(ctx, VIVS_RS_DEST_ADDR, etna_bo_gpu_address(rt_ts)); etna_set_state(ctx, VIVS_RS_DEST_STRIDE, 0x40); etna_set_state(ctx, VIVS_RS_WINDOW_SIZE, ((rt_ts_size/0x40) << VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT) | (16 << VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT)); etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb); /* clear depth ts */ etna_set_state(ctx, VIVS_RS_DEST_ADDR, etna_bo_gpu_address(z_ts)); etna_set_state(ctx, VIVS_RS_DEST_STRIDE, 0x40); etna_set_state(ctx, VIVS_RS_WINDOW_SIZE, ((z_ts_size/0x40) << VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT) | (16 << VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT)); etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb); /** Done */ etna_set_state(ctx, VIVS_TS_COLOR_CLEAR_VALUE, 0xff7f7f7f); etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR); etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, etna_bo_gpu_address(rt_ts)); etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, etna_bo_gpu_address(rt)); etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH); /* depth setup */ etna_set_state(ctx, VIVS_PE_DEPTH_CONFIG, ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE, 1) & ETNA_MASKED(VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC, COMPARE_FUNC_LESS) & ETNA_MASKED_INL(VIVS_PE_DEPTH_CONFIG_DEPTH_MODE, Z) & ETNA_MASKED_BIT(VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH, 0)); etna_set_state_f32(ctx, VIVS_PE_DEPTH_NEAR, 0.0); etna_set_state_f32(ctx, VIVS_PE_DEPTH_FAR, 1.0); etna_set_state_f32(ctx, VIVS_PE_DEPTH_NORMALIZE, 65535.0); /* set up primitive assembly and setup engine */ etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_OFFSET_Z, 0.0); etna_set_state_f32(ctx, VIVS_PA_VIEWPORT_SCALE_Z, 1.0); etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_X, width << 15); etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_OFFSET_Y, height << 15); etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_X, width << 15); etna_set_state_fixp(ctx, VIVS_PA_VIEWPORT_SCALE_Y, height << 15); etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_LEFT, 0); etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_TOP, 0); etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_RIGHT, (width << 16) | 5); etna_set_state_fixp(ctx, VIVS_SE_SCISSOR_BOTTOM, (height << 16) | 5); /* set up texture unit */ etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_TEXTURE); etna_set_state(ctx, VIVS_TE_SAMPLER_SIZE(0), VIVS_TE_SAMPLER_SIZE_WIDTH(512)|VIVS_TE_SAMPLER_SIZE_HEIGHT(512)); etna_set_state(ctx, VIVS_TE_SAMPLER_LOG_SIZE(0), VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(9<<5) | VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(9<<5)); etna_set_state(ctx, VIVS_TE_SAMPLER_LOD_ADDR(0,0), etna_bo_gpu_address(tex)); etna_set_state(ctx, VIVS_TE_SAMPLER_CONFIG0(0), VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_2D)| VIVS_TE_SAMPLER_CONFIG0_UWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE)| VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE)| VIVS_TE_SAMPLER_CONFIG0_MIN(TEXTURE_FILTER_LINEAR)| VIVS_TE_SAMPLER_CONFIG0_MIP(TEXTURE_FILTER_NONE)| VIVS_TE_SAMPLER_CONFIG0_MAG(TEXTURE_FILTER_LINEAR)| VIVS_TE_SAMPLER_CONFIG0_FORMAT(TEXTURE_FORMAT_X8R8G8B8)); etna_set_state(ctx, VIVS_TE_SAMPLER_LOD_CONFIG(0), 0x00000000); /* TE.SAMPLER[0].LOD_CONFIG := 0x0 */ /* shader setup */ etna_set_state(ctx, VIVS_VS_END_PC, vs_size/16); etna_set_state_multi(ctx, VIVS_VS_INPUT_COUNT, 3, (uint32_t[]){ /* VIVS_VS_INPUT_COUNT */ VIVS_VS_INPUT_COUNT_UNK8(1) | VIVS_VS_INPUT_COUNT_COUNT(3), /* VIVS_VS_TEMP_REGISTER_CONTROL */ VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS(6), /* VIVS_VS_OUTPUT(0) */ 0x10004}); etna_set_state(ctx, VIVS_VS_START_PC, 0x0); etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(45), 0.5); /* u11.y */ etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(44), 1.0); /* u11.x */ etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(27), 0.0); /* u6.w */ etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(23), 20.0); /* u5.w */ etna_set_state_f32(ctx, VIVS_VS_UNIFORMS(19), 2.0); /* u4.w */ /* Now load the shader itself */ etna_set_state_multi(ctx, VIVS_VS_INST_MEM(0), vs_size/4, vs); etna_set_state(ctx, VIVS_RA_CONTROL, 0x3); etna_set_state_f32(ctx, VIVS_PS_UNIFORMS(0), 1.0); /* u0.x */ etna_set_state_multi(ctx, VIVS_PS_END_PC, 2, (uint32_t[]){ /* VIVS_PS_END_PC */ ps_size/16, /* VIVS_PS_OUTPUT_REG */ 0x1}); etna_set_state(ctx, VIVS_PS_START_PC, 0x0); etna_set_state(ctx, VIVS_PA_ATTRIBUTE_ELEMENT_COUNT, 0x200); etna_set_state(ctx, VIVS_PA_SHADER_ATTRIBUTES(0), 0x200); etna_set_state(ctx, VIVS_PA_SHADER_ATTRIBUTES(1), 0x200); etna_set_state(ctx, VIVS_GL_VARYING_NUM_COMPONENTS, VIVS_GL_VARYING_NUM_COMPONENTS_VAR0(4)| /* position */ VIVS_GL_VARYING_NUM_COMPONENTS_VAR1(2) /* texture coordinate */ ); etna_set_state_multi(ctx, VIVS_GL_VARYING_COMPONENT_USE(0), 2, (uint32_t[]){ VIVS_GL_VARYING_COMPONENT_USE_COMP0(VARYING_COMPONENT_USE_USED) | VIVS_GL_VARYING_COMPONENT_USE_COMP1(VARYING_COMPONENT_USE_USED) | VIVS_GL_VARYING_COMPONENT_USE_COMP2(VARYING_COMPONENT_USE_USED) | VIVS_GL_VARYING_COMPONENT_USE_COMP3(VARYING_COMPONENT_USE_USED) | VIVS_GL_VARYING_COMPONENT_USE_COMP4(VARYING_COMPONENT_USE_USED) | VIVS_GL_VARYING_COMPONENT_USE_COMP5(VARYING_COMPONENT_USE_USED) , 0 }); etna_set_state_multi(ctx, VIVS_PS_INST_MEM(0), ps_size/4, ps); etna_set_state(ctx, VIVS_PS_INPUT_COUNT, VIVS_PS_INPUT_COUNT_UNK8(31)| VIVS_PS_INPUT_COUNT_COUNT(3 + extra_ps_inputs)); etna_set_state(ctx, VIVS_PS_TEMP_REGISTER_CONTROL, VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(3 + extra_ps_inputs)); etna_set_state(ctx, VIVS_PS_CONTROL, VIVS_PS_CONTROL_UNK1); etna_set_state(ctx, VIVS_GL_VARYING_TOTAL_COMPONENTS, VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(6)); /* 4+2=6 total varying components */ etna_set_state(ctx, VIVS_VS_LOAD_BALANCING, 0xf3f0542); /* depends on number of inputs/outputs/varyings? XXX how exactly */ etna_set_state(ctx, VIVS_VS_OUTPUT_COUNT, 3); etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_POINT_SIZE_ENABLE, 0)); /* Compute transform matrices in the same way as cube egl demo */ ESMatrix modelview; esMatrixLoadIdentity(&modelview); esTranslate(&modelview, 0.0f, 0.0f, -9.0f); esRotate(&modelview, 45.0f, 1.0f, 0.0f, 0.0f); esRotate(&modelview, 45.0f, 0.0f, 1.0f, 0.0f); esRotate(&modelview, frame*0.5f, 0.0f, 0.0f, 1.0f); esScale(&modelview, 0.475f, 0.475f, 0.475f); float aspect = (float)(height) / (float)(width); ESMatrix projection; esMatrixLoadIdentity(&projection); esFrustum(&projection, -2.8f, +2.8f, -2.8f * aspect, +2.8f * aspect, 6.0f, 10.0f); ESMatrix modelviewprojection; esMatrixLoadIdentity(&modelviewprojection); esMatrixMultiply(&modelviewprojection, &modelview, &projection); ESMatrix inverse, normal; /* compute inverse transpose normal transformation matrix */ esMatrixInverse3x3(&inverse, &modelview); esMatrixTranspose(&normal, &inverse); etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(0), 16, (uint32_t*)&modelviewprojection.m[0][0]); etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(16), 3, (uint32_t*)&normal.m[0][0]); /* u4.xyz */ etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(20), 3, (uint32_t*)&normal.m[1][0]); /* u5.xyz */ etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(24), 3, (uint32_t*)&normal.m[2][0]); /* u6.xyz */ etna_set_state_multi(ctx, VIVS_VS_UNIFORMS(28), 16, (uint32_t*)&modelview.m[0][0]); #ifdef INDEXED etna_set_state(ctx, VIVS_FE_INDEX_STREAM_BASE_ADDR, etna_bo_gpu_address(idx)); etna_set_state(ctx, VIVS_FE_INDEX_STREAM_CONTROL, VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_SHORT); #endif etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_BASE_ADDR, etna_bo_gpu_address(vtx)); etna_set_state(ctx, VIVS_FE_VERTEX_STREAM_CONTROL, FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE((3 + 3 + 2)*4)); etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(0), VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT | (ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) | VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(0) | VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(3) | VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF | VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0x0) | VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0xc)); etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(1), VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT | (ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) | VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(0) | VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(3) | VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF | VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0xc) | VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0x18)); etna_set_state(ctx, VIVS_FE_VERTEX_ELEMENT_CONFIG(2), VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT | (ENDIAN_MODE_NO_SWAP << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) | VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE | VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(0) | VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(2) | VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF | VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0x18) | VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0x20)); etna_set_state(ctx, VIVS_VS_INPUT(0), 0x20100); etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_POINT_SPRITE_ENABLE, 0)); #ifdef INDEXED etna_draw_indexed_primitives(ctx, PRIMITIVE_TYPE_TRIANGLES, 0, COMPANION_TRIANGLE_COUNT, 0); #else etna_draw_primitives(ctx, PRIMITIVE_TYPE_TRIANGLES, 0, COMPANION_TRIANGLE_COUNT); #endif etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH); #ifdef EXTRA_DELAYS etna_flush(ctx, NULL); #endif etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH); etna_set_state(ctx, VIVS_RS_CONFIG, VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_A8R8G8B8) | VIVS_RS_CONFIG_SOURCE_TILED | VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_A8R8G8B8) | VIVS_RS_CONFIG_DEST_TILED); etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | (supertiled?VIVS_RS_SOURCE_STRIDE_TILING:0)); etna_set_state(ctx, VIVS_RS_DEST_STRIDE, (padded_width * 4 * 4) | (supertiled?VIVS_RS_SOURCE_STRIDE_TILING:0)); etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff); etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff); etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED); etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0); etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, etna_bo_gpu_address(rt)); etna_set_state(ctx, VIVS_RS_DEST_ADDR, etna_bo_gpu_address(rt)); etna_set_state(ctx, VIVS_RS_WINDOW_SIZE, VIVS_RS_WINDOW_SIZE_HEIGHT(padded_height) | VIVS_RS_WINDOW_SIZE_WIDTH(padded_width)); etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb); #ifdef EXTRA_DELAYS etna_flush(ctx, NULL); etna_warm_up_rs(ctx, etna_bo_gpu_address(aux_rt), etna_bo_gpu_address(aux_rt_ts)); #endif etna_set_state(ctx, VIVS_TS_COLOR_STATUS_BASE, etna_bo_gpu_address(rt_ts)); etna_set_state(ctx, VIVS_TS_COLOR_SURFACE_BASE, etna_bo_gpu_address(rt)); etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR); etna_set_state(ctx, VIVS_TS_MEM_CONFIG, VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR | VIVS_TS_MEM_CONFIG_DEPTH_16BPP | VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION); etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR); /* Wait for pixel engine to finish */ #ifdef EXTRA_DELAYS etna_finish(ctx); #else etna_stall(ctx, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); #endif /* Copy result to framebuffer */ etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH); etna_set_state(ctx, VIVS_RS_CONFIG, VIVS_RS_CONFIG_SOURCE_FORMAT(RS_FORMAT_A8R8G8B8) | VIVS_RS_CONFIG_SOURCE_TILED | ((supersample_x>1)?VIVS_RS_CONFIG_DOWNSAMPLE_X:0) | ((supersample_y>1)?VIVS_RS_CONFIG_DOWNSAMPLE_Y:0) | VIVS_RS_CONFIG_DEST_FORMAT(RS_FORMAT_A8R8G8B8) | VIVS_RS_CONFIG_SWAP_RB); etna_set_state(ctx, VIVS_RS_SOURCE_STRIDE, (padded_width * 4 * 4) | (supertiled?VIVS_RS_SOURCE_STRIDE_TILING:0)); etna_set_state(ctx, VIVS_RS_DEST_STRIDE, fbs->fb.fb_fix.line_length); etna_set_state(ctx, VIVS_RS_DITHER(0), 0xffffffff); etna_set_state(ctx, VIVS_RS_DITHER(1), 0xffffffff); etna_set_state(ctx, VIVS_RS_CLEAR_CONTROL, VIVS_RS_CLEAR_CONTROL_MODE_DISABLED); etna_set_state(ctx, VIVS_RS_EXTRA_CONFIG, 0); etna_set_state(ctx, VIVS_RS_SOURCE_ADDR, etna_bo_gpu_address(rt)); etna_set_state(ctx, VIVS_RS_DEST_ADDR, etna_bo_gpu_address(fbs->fb.buffer[backbuffer])); etna_set_state(ctx, VIVS_RS_WINDOW_SIZE, VIVS_RS_WINDOW_SIZE_HEIGHT(height * supersample_y) | VIVS_RS_WINDOW_SIZE_WIDTH(width * supersample_x)); etna_set_state(ctx, VIVS_RS_KICKER, 0xbeebbeeb); etna_finish(ctx); /* switch buffers */ fb_set_buffer(&fbs->fb, backbuffer); backbuffer = 1-backbuffer; } etna_free(ctx); viv_close(conn); return 0; }
static struct pipe_resource * etna_resource_from_handle(struct pipe_screen *pscreen, const struct pipe_resource *tmpl, struct winsys_handle *handle, unsigned usage) { struct etna_screen *screen = etna_screen(pscreen); struct etna_resource *rsc; struct etna_resource_level *level; struct pipe_resource *prsc; struct pipe_resource *ptiled = NULL; DBG("target=%d, format=%s, %ux%ux%u, array_size=%u, last_level=%u, " "nr_samples=%u, usage=%u, bind=%x, flags=%x", tmpl->target, util_format_name(tmpl->format), tmpl->width0, tmpl->height0, tmpl->depth0, tmpl->array_size, tmpl->last_level, tmpl->nr_samples, tmpl->usage, tmpl->bind, tmpl->flags); rsc = CALLOC_STRUCT(etna_resource); if (!rsc) return NULL; level = &rsc->levels[0]; prsc = &rsc->base; *prsc = *tmpl; pipe_reference_init(&prsc->reference, 1); list_inithead(&rsc->list); prsc->screen = pscreen; rsc->bo = etna_screen_bo_from_handle(pscreen, handle, &level->stride); if (!rsc->bo) goto fail; rsc->seqno = 1; rsc->layout = modifier_to_layout(handle->modifier); rsc->halign = TEXTURE_HALIGN_FOUR; level->width = tmpl->width0; level->height = tmpl->height0; /* Determine padding of the imported resource. */ unsigned paddingX = 0, paddingY = 0; etna_layout_multiple(rsc->layout, screen->specs.pixel_pipes, VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN), &paddingX, &paddingY, &rsc->halign); if (!screen->specs.use_blt) etna_adjust_rs_align(screen->specs.pixel_pipes, NULL, &paddingY); level->padded_width = align(level->width, paddingX); level->padded_height = align(level->height, paddingY); level->layer_stride = level->stride * util_format_get_nblocksy(prsc->format, level->padded_height); level->size = level->layer_stride; /* The DDX must give us a BO which conforms to our padding size. * The stride of the BO must be greater or equal to our padded * stride. The size of the BO must accomodate the padded height. */ if (level->stride < util_format_get_stride(tmpl->format, level->padded_width)) { BUG("BO stride %u is too small for RS engine width padding (%zu, format %s)", level->stride, util_format_get_stride(tmpl->format, level->padded_width), util_format_name(tmpl->format)); goto fail; } if (etna_bo_size(rsc->bo) < level->stride * level->padded_height) { BUG("BO size %u is too small for RS engine height padding (%u, format %s)", etna_bo_size(rsc->bo), level->stride * level->padded_height, util_format_name(tmpl->format)); goto fail; } if (rsc->layout == ETNA_LAYOUT_LINEAR) { /* * Both sampler and pixel pipes can't handle linear, create a compatible * base resource, where we can attach the imported buffer as an external * resource. */ struct pipe_resource tiled_templat = *tmpl; /* * Remove BIND_SCANOUT to avoid recursion, as etna_resource_create uses * this function to import the scanout buffer and get a tiled resource. */ tiled_templat.bind &= ~PIPE_BIND_SCANOUT; ptiled = etna_resource_create(pscreen, &tiled_templat); if (!ptiled) goto fail; etna_resource(ptiled)->external = prsc; return ptiled; } return prsc; fail: etna_resource_destroy(pscreen, prsc); if (ptiled) etna_resource_destroy(pscreen, ptiled); return NULL; }
/* Create a new resource object, using the given template info */ struct pipe_resource * etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout, uint64_t modifier, const struct pipe_resource *templat) { struct etna_screen *screen = etna_screen(pscreen); struct etna_resource *rsc; unsigned size; DBG_F(ETNA_DBG_RESOURCE_MSGS, "target=%d, format=%s, %ux%ux%u, array_size=%u, " "last_level=%u, nr_samples=%u, usage=%u, bind=%x, flags=%x", templat->target, util_format_name(templat->format), templat->width0, templat->height0, templat->depth0, templat->array_size, templat->last_level, templat->nr_samples, templat->usage, templat->bind, templat->flags); /* Determine scaling for antialiasing, allow override using debug flag */ int nr_samples = templat->nr_samples; if ((templat->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) && !(templat->bind & PIPE_BIND_SAMPLER_VIEW)) { if (DBG_ENABLED(ETNA_DBG_MSAA_2X)) nr_samples = 2; if (DBG_ENABLED(ETNA_DBG_MSAA_4X)) nr_samples = 4; } int msaa_xscale = 1, msaa_yscale = 1; if (!translate_samples_to_xyscale(nr_samples, &msaa_xscale, &msaa_yscale, NULL)) { /* Number of samples not supported */ return NULL; } /* Determine needed padding (alignment of height/width) */ unsigned paddingX = 0, paddingY = 0; unsigned halign = TEXTURE_HALIGN_FOUR; if (!util_format_is_compressed(templat->format)) { /* If we have the TEXTURE_HALIGN feature, we can always align to the * resolve engine's width. If not, we must not align resources used * only for textures. If this GPU uses the BLT engine, never do RS align. */ bool rs_align = screen->specs.use_blt ? false : ( VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) || !etna_resource_sampler_only(templat)); etna_layout_multiple(layout, screen->specs.pixel_pipes, rs_align, &paddingX, &paddingY, &halign); assert(paddingX && paddingY); } else { /* Compressed textures are padded to their block size, but we don't have * to do anything special for that. */ paddingX = 1; paddingY = 1; } if (!screen->specs.use_blt && templat->target != PIPE_BUFFER) etna_adjust_rs_align(screen->specs.pixel_pipes, NULL, &paddingY); if (templat->bind & PIPE_BIND_SCANOUT) { struct pipe_resource scanout_templat = *templat; struct renderonly_scanout *scanout; struct winsys_handle handle; /* pad scanout buffer size to be compatible with the RS */ if (!screen->specs.use_blt && modifier == DRM_FORMAT_MOD_LINEAR) etna_adjust_rs_align(screen->specs.pixel_pipes, &paddingX, &paddingY); scanout_templat.width0 = align(scanout_templat.width0, paddingX); scanout_templat.height0 = align(scanout_templat.height0, paddingY); scanout = renderonly_scanout_for_resource(&scanout_templat, screen->ro, &handle); if (!scanout) return NULL; assert(handle.type == WINSYS_HANDLE_TYPE_FD); handle.modifier = modifier; rsc = etna_resource(pscreen->resource_from_handle(pscreen, templat, &handle, PIPE_HANDLE_USAGE_WRITE)); close(handle.handle); if (!rsc) return NULL; rsc->scanout = scanout; return &rsc->base; } rsc = CALLOC_STRUCT(etna_resource); if (!rsc) return NULL; rsc->base = *templat; rsc->base.screen = pscreen; rsc->base.nr_samples = nr_samples; rsc->layout = layout; rsc->halign = halign; pipe_reference_init(&rsc->base.reference, 1); list_inithead(&rsc->list); size = setup_miptree(rsc, paddingX, paddingY, msaa_xscale, msaa_yscale); uint32_t flags = DRM_ETNA_GEM_CACHE_WC; if (templat->bind & PIPE_BIND_VERTEX_BUFFER) flags |= DRM_ETNA_GEM_FORCE_MMU; struct etna_bo *bo = etna_bo_new(screen->dev, size, flags); if (unlikely(bo == NULL)) { BUG("Problem allocating video memory for resource"); goto free_rsc; } rsc->bo = bo; rsc->ts_bo = 0; /* TS is only created when first bound to surface */ if (DBG_ENABLED(ETNA_DBG_ZERO)) { void *map = etna_bo_map(bo); memset(map, 0, size); } return &rsc->base; free_rsc: FREE(rsc); return NULL; }
static boolean etna_screen_is_format_supported(struct pipe_screen *pscreen, enum pipe_format format, enum pipe_texture_target target, unsigned sample_count, unsigned usage) { struct etna_screen *screen = etna_screen(pscreen); unsigned allowed = 0; if (target != PIPE_BUFFER && target != PIPE_TEXTURE_1D && target != PIPE_TEXTURE_2D && target != PIPE_TEXTURE_3D && target != PIPE_TEXTURE_CUBE && target != PIPE_TEXTURE_RECT) return FALSE; if (usage & PIPE_BIND_RENDER_TARGET) { /* If render target, must be RS-supported format that is not rb swapped. * Exposing rb swapped (or other swizzled) formats for rendering would * involve swizzing in the pixel shader. */ if (translate_rs_format(format) != ETNA_NO_MATCH && !translate_rs_format_rb_swap(format)) { /* Validate MSAA; number of samples must be allowed, and render target * must have MSAA'able format. */ if (sample_count > 1) { if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) && translate_msaa_format(format) != ETNA_NO_MATCH) { allowed |= PIPE_BIND_RENDER_TARGET; } } else { allowed |= PIPE_BIND_RENDER_TARGET; } } } if (usage & PIPE_BIND_DEPTH_STENCIL) { if (translate_depth_format(format) != ETNA_NO_MATCH) allowed |= PIPE_BIND_DEPTH_STENCIL; } if (usage & PIPE_BIND_SAMPLER_VIEW) { uint32_t fmt = translate_texture_format(format); if (!gpu_supports_texure_format(screen, fmt)) fmt = ETNA_NO_MATCH; if (sample_count < 2 && fmt != ETNA_NO_MATCH) allowed |= PIPE_BIND_SAMPLER_VIEW; } if (usage & PIPE_BIND_VERTEX_BUFFER) { if (translate_vertex_format_type(format) != ETNA_NO_MATCH) allowed |= PIPE_BIND_VERTEX_BUFFER; } if (usage & PIPE_BIND_INDEX_BUFFER) { /* must be supported index format */ if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT || (format == PIPE_FORMAT_I32_UINT && VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) { allowed |= PIPE_BIND_INDEX_BUFFER; } } /* Always allowed */ allowed |= usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED); if (usage != allowed) { DBG("not supported: format=%s, target=%d, sample_count=%d, " "usage=%x, allowed=%x", util_format_name(format), target, sample_count, usage, allowed); } return usage == allowed; }
static boolean etna_screen_is_format_supported( struct pipe_screen *screen, enum pipe_format format, enum pipe_texture_target target, unsigned sample_count, unsigned usage) { struct etna_screen *priv = etna_screen(screen); unsigned allowed = 0; if (target >= PIPE_MAX_TEXTURE_TYPES) { return FALSE; } if (usage & PIPE_BIND_RENDER_TARGET) { /* if render target, must be RS-supported format */ if(translate_rt_format(format, true) != ETNA_NO_MATCH) { /* Validate MSAA; number of samples must be allowed, and render target must have * MSAA'able format. */ if(sample_count > 1) { if(translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) && translate_msaa_format(format, true) != ETNA_NO_MATCH) { allowed |= PIPE_BIND_RENDER_TARGET; } } else { allowed |= PIPE_BIND_RENDER_TARGET; } } } if (usage & PIPE_BIND_DEPTH_STENCIL) { /* must be supported depth format */ if(translate_depth_format(format, true) != ETNA_NO_MATCH) { allowed |= PIPE_BIND_DEPTH_STENCIL; } } if (usage & PIPE_BIND_SAMPLER_VIEW) { /* must be supported texture format */ if(sample_count < 2 && translate_texture_format(format, true) != ETNA_NO_MATCH) { allowed |= PIPE_BIND_SAMPLER_VIEW; } } if (usage & PIPE_BIND_VERTEX_BUFFER) { /* must be supported vertex format */ if(translate_vertex_format_type(format, true) == ETNA_NO_MATCH) { allowed |= PIPE_BIND_VERTEX_BUFFER; } } if (usage & PIPE_BIND_INDEX_BUFFER) { /* must be supported index format */ if(format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT || (format == PIPE_FORMAT_I32_UINT && VIV_FEATURE(priv->dev, chipFeatures, 32_BIT_INDICES))) { allowed |= PIPE_BIND_INDEX_BUFFER; } } /* Always allowed */ allowed |= usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_TRANSFER_READ | PIPE_BIND_TRANSFER_WRITE); return usage == allowed; }
static int etna_screen_get_shader_param( struct pipe_screen *screen, unsigned shader, enum pipe_shader_cap param ) { struct etna_screen *priv = etna_screen(screen); switch(shader) { case PIPE_SHADER_FRAGMENT: case PIPE_SHADER_VERTEX: break; case PIPE_SHADER_COMPUTE: case PIPE_SHADER_GEOMETRY: /* maybe we could emulate.. */ return 0; default: DBG("unknown shader type %d", shader); return 0; } switch (param) { case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: return ETNA_MAX_TOKENS; case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: return ETNA_MAX_DEPTH; /* XXX */ case PIPE_SHADER_CAP_MAX_INPUTS: return 16; /* XXX this amount is reserved */ case PIPE_SHADER_CAP_MAX_TEMPS: return 64; /* Max native temporaries. */ case PIPE_SHADER_CAP_MAX_ADDRS: return 1; /* Max native address registers */ case PIPE_SHADER_CAP_MAX_CONSTS: /* Absolute maximum on ideal hardware is 256 (as that's how much register space is reserved); * immediates are included in here, so actual space available for constants will always be less. * Also the amount of registers really available depends on the hw. * XXX see also: viv_specs.num_constants, if this is 0 we need to come up with some default value. */ return 256; case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: return 1; case PIPE_SHADER_CAP_MAX_PREDS: return 0; /* nothing uses this */ case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: return 1; case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: return 1; case PIPE_SHADER_CAP_SUBROUTINES: return 0; case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: return VIV_FEATURE(priv->dev, chipMinorFeatures0, HAS_SQRT_TRIG); case PIPE_SHADER_CAP_TGSI_POW_SUPPORTED: return false; case PIPE_SHADER_CAP_TGSI_LRP_SUPPORTED: return false; case PIPE_SHADER_CAP_INTEGERS: /* XXX supported on gc2000 but not yet implemented */ return 0; case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: return shader==PIPE_SHADER_FRAGMENT ? priv->specs.fragment_sampler_count : priv->specs.vertex_sampler_count; case PIPE_SHADER_CAP_PREFERRED_IR: return PIPE_SHADER_IR_TGSI; default: DBG("unknown shader param %d", param); return 0; } return 0; }
/* Create a new resource object, using the given template info */ struct pipe_resource * etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout, const struct pipe_resource *templat) { struct etna_screen *screen = etna_screen(pscreen); unsigned size; DBG_F(ETNA_DBG_RESOURCE_MSGS, "target=%d, format=%s, %ux%ux%u, array_size=%u, " "last_level=%u, nr_samples=%u, usage=%u, bind=%x, flags=%x", templat->target, util_format_name(templat->format), templat->width0, templat->height0, templat->depth0, templat->array_size, templat->last_level, templat->nr_samples, templat->usage, templat->bind, templat->flags); /* Determine scaling for antialiasing, allow override using debug flag */ int nr_samples = templat->nr_samples; if ((templat->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) && !(templat->bind & PIPE_BIND_SAMPLER_VIEW)) { if (DBG_ENABLED(ETNA_DBG_MSAA_2X)) nr_samples = 2; if (DBG_ENABLED(ETNA_DBG_MSAA_4X)) nr_samples = 4; } int msaa_xscale = 1, msaa_yscale = 1; if (!translate_samples_to_xyscale(nr_samples, &msaa_xscale, &msaa_yscale, NULL)) { /* Number of samples not supported */ return NULL; } /* If we have the TEXTURE_HALIGN feature, we can always align to the * resolve engine's width. If not, we must not align resources used * only for textures. */ bool rs_align = VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) || !etna_resource_sampler_only(templat); /* Determine needed padding (alignment of height/width) */ unsigned paddingX = 0, paddingY = 0; unsigned halign = TEXTURE_HALIGN_FOUR; etna_layout_multiple(layout, screen->specs.pixel_pipes, rs_align, &paddingX, &paddingY, &halign); assert(paddingX && paddingY); if (templat->bind != PIPE_BUFFER) { unsigned min_paddingY = 4 * screen->specs.pixel_pipes; if (paddingY < min_paddingY) paddingY = min_paddingY; } struct etna_resource *rsc = CALLOC_STRUCT(etna_resource); if (!rsc) return NULL; rsc->base = *templat; rsc->base.screen = pscreen; rsc->base.nr_samples = nr_samples; rsc->layout = layout; rsc->halign = halign; pipe_reference_init(&rsc->base.reference, 1); list_inithead(&rsc->list); size = setup_miptree(rsc, paddingX, paddingY, msaa_xscale, msaa_yscale); uint32_t flags = DRM_ETNA_GEM_CACHE_WC; if (templat->bind & PIPE_BIND_VERTEX_BUFFER) flags |= DRM_ETNA_GEM_FORCE_MMU; struct etna_bo *bo = etna_bo_new(screen->dev, size, flags); if (unlikely(bo == NULL)) { BUG("Problem allocating video memory for resource"); return NULL; } rsc->bo = bo; rsc->ts_bo = 0; /* TS is only created when first bound to surface */ if (templat->bind & PIPE_BIND_SCANOUT) rsc->scanout = renderonly_scanout_for_resource(&rsc->base, screen->ro); if (DBG_ENABLED(ETNA_DBG_ZERO)) { void *map = etna_bo_map(bo); memset(map, 0, size); } return &rsc->base; }
static boolean etna_get_specs(struct etna_screen *screen) { uint64_t val; uint32_t instruction_count; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) { DBG("could not get ETNA_GPU_INSTRUCTION_COUNT"); goto fail; } instruction_count = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE, &val)) { DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE"); goto fail; } screen->specs.vertex_output_buffer_size = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) { DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE"); goto fail; } screen->specs.vertex_cache_size = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) { DBG("could not get ETNA_GPU_SHADER_CORE_COUNT"); goto fail; } screen->specs.shader_core_count = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) { DBG("could not get ETNA_GPU_STREAM_COUNT"); goto fail; } screen->specs.stream_count = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) { DBG("could not get ETNA_GPU_REGISTER_MAX"); goto fail; } screen->specs.max_registers = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) { DBG("could not get ETNA_GPU_PIXEL_PIPES"); goto fail; } screen->specs.pixel_pipes = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) { DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS"); goto fail; } if (val == 0) { fprintf(stderr, "Warning: zero num constants (update kernel?)\n"); val = 168; } screen->specs.num_constants = val; /* Figure out gross GPU architecture. See rnndb/common.xml for a specific * description of the differences. */ if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5)) screen->specs.halti = 5; /* New GC7000/GC8x00 */ else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4)) screen->specs.halti = 4; /* Old GC7000/GC7400 */ else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3)) screen->specs.halti = 3; /* None? */ else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2)) screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */ else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1)) screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */ else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */ else screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */ if (screen->specs.halti >= 0) DBG("etnaviv: GPU arch: HALTI%d", screen->specs.halti); else DBG("etnaviv: GPU arch: pre-HALTI"); screen->specs.can_supertile = VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED); screen->specs.bits_per_tile = VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4; screen->specs.ts_clear_value = VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555 : 0x11111111; /* vertex and fragment samplers live in one address space */ screen->specs.vertex_sampler_offset = 8; screen->specs.fragment_sampler_count = 8; screen->specs.vertex_sampler_count = 4; screen->specs.vs_need_z_div = screen->model < 0x1000 && screen->model != 0x880; screen->specs.has_sin_cos_sqrt = VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG); screen->specs.has_sign_floor_ceil = VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL); screen->specs.has_shader_range_registers = screen->model >= 0x1000 || screen->model == 0x880; screen->specs.npot_tex_any_wrap = VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO); screen->specs.has_new_transcendentals = VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS); screen->specs.has_halti2_instructions = VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); if (screen->specs.halti >= 5) { /* GC7000 - this core must load shaders from memory. */ screen->specs.vs_offset = 0; screen->specs.ps_offset = 0; screen->specs.max_instructions = 0; /* Do not program shaders manually */ screen->specs.has_icache = true; } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) { /* GC3000 - this core is capable of loading shaders from * memory. It can also run shaders from registers, as a fallback, but * "max_instructions" does not have the correct value. It has place for * 2*256 instructions just like GC2000, but the offsets are slightly * different. */ screen->specs.vs_offset = 0xC000; /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses * this mirror for writing PS instructions, probably safest to do the * same. */ screen->specs.ps_offset = 0x8000 + 0x1000; screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */ screen->specs.has_icache = true; } else { if (instruction_count > 256) { /* unified instruction memory? */ screen->specs.vs_offset = 0xC000; screen->specs.ps_offset = 0xD000; /* like vivante driver */ screen->specs.max_instructions = 256; } else { screen->specs.vs_offset = 0x4000; screen->specs.ps_offset = 0x6000; screen->specs.max_instructions = instruction_count / 2; } screen->specs.has_icache = false; } if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) { screen->specs.max_varyings = 12; screen->specs.vertex_max_elements = 16; } else { screen->specs.max_varyings = 8; /* Etna_viv documentation seems confused over the correct value * here so choose the lower to be safe: HALTI0 says 16 i.s.o. * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */ screen->specs.vertex_max_elements = 10; } /* Etna_viv documentation does not indicate where varyings above 8 are * stored. Moreover, if we are passed more than 8 varyings, we will * walk off the end of some arrays. Limit the maximum number of varyings. */ if (screen->specs.max_varyings > ETNA_NUM_VARYINGS) screen->specs.max_varyings = ETNA_NUM_VARYINGS; /* from QueryShaderCaps in kernel driver */ if (screen->model < chipModel_GC4000) { screen->specs.max_vs_uniforms = 168; screen->specs.max_ps_uniforms = 64; } else { screen->specs.max_vs_uniforms = 256; screen->specs.max_ps_uniforms = 256; } if (screen->specs.halti >= 5) { screen->specs.has_unified_uniforms = true; screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0); screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4); } else if (screen->specs.halti >= 1) { /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess */ screen->specs.has_unified_uniforms = true; screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0); /* hardcode PS uniforms to start after end of VS uniforms - * for more flexibility this offset could be variable based on the * shader. */ screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4); } else { screen->specs.has_unified_uniforms = false; screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0); screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0); } screen->specs.max_texture_size = VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048; screen->specs.max_rendertarget_size = VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048; screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER); if (screen->specs.single_buffer) DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes); screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC); screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE); return true; fail: return false; }
static boolean etna_get_specs(struct etna_screen *screen) { uint64_t val; uint32_t instruction_count; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) { DBG("could not get ETNA_GPU_INSTRUCTION_COUNT"); goto fail; } instruction_count = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE, &val)) { DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE"); goto fail; } screen->specs.vertex_output_buffer_size = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) { DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE"); goto fail; } screen->specs.vertex_cache_size = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) { DBG("could not get ETNA_GPU_SHADER_CORE_COUNT"); goto fail; } screen->specs.shader_core_count = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) { DBG("could not get ETNA_GPU_STREAM_COUNT"); goto fail; } screen->specs.stream_count = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) { DBG("could not get ETNA_GPU_REGISTER_MAX"); goto fail; } screen->specs.max_registers = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) { DBG("could not get ETNA_GPU_PIXEL_PIPES"); goto fail; } if (val < 1 && val > ETNA_MAX_PIXELPIPES) { if (val == 0) { fprintf(stderr, "Warning: zero pixel pipes (update kernel?)\n"); val = 1; } else { fprintf(stderr, "Error: bad pixel pipes value %u\n", (unsigned int)val); goto fail; } } screen->specs.pixel_pipes = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) { DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS"); goto fail; } if (val == 0) { fprintf(stderr, "Warning: zero num constants (update kernel?)\n"); val = 168; } screen->specs.num_constants = val; screen->specs.can_supertile = VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED); screen->specs.bits_per_tile = VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4; screen->specs.ts_clear_value = VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555 : 0x11111111; /* vertex and fragment samplers live in one address space */ screen->specs.vertex_sampler_offset = 8; screen->specs.fragment_sampler_count = 8; screen->specs.vertex_sampler_count = 4; screen->specs.vs_need_z_div = screen->model < 0x1000 && screen->model != 0x880; screen->specs.has_sin_cos_sqrt = VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG); screen->specs.has_sign_floor_ceil = VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL); screen->specs.has_shader_range_registers = screen->model >= 0x1000 || screen->model == 0x880; screen->specs.npot_tex_any_wrap = VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO); screen->specs.has_new_sin_cos = VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS); if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) { /* GC3000 - this core is capable of loading shaders from * memory. It can also run shaders from registers, as a fallback, but * "max_instructions" does not have the correct value. It has place for * 2*256 instructions just like GC2000, but the offsets are slightly * different. */ screen->specs.vs_offset = 0xC000; /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses * this mirror for writing PS instructions, probably safest to do the * same. */ screen->specs.ps_offset = 0x8000 + 0x1000; screen->specs.max_instructions = 256; } else { if (instruction_count > 256) { /* unified instruction memory? */ screen->specs.vs_offset = 0xC000; screen->specs.ps_offset = 0xD000; /* like vivante driver */ screen->specs.max_instructions = 256; } else { screen->specs.vs_offset = 0x4000; screen->specs.ps_offset = 0x6000; screen->specs.max_instructions = instruction_count / 2; } } if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) { screen->specs.max_varyings = 12; screen->specs.vertex_max_elements = 16; } else { screen->specs.max_varyings = 8; /* Etna_viv documentation seems confused over the correct value * here so choose the lower to be safe: HALTI0 says 16 i.s.o. * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */ screen->specs.vertex_max_elements = 10; } /* Etna_viv documentation does not indicate where varyings above 8 are * stored. Moreover, if we are passed more than 8 varyings, we will * walk off the end of some arrays. Limit the maximum number of varyings. */ if (screen->specs.max_varyings > ETNA_NUM_VARYINGS) screen->specs.max_varyings = ETNA_NUM_VARYINGS; /* from QueryShaderCaps in kernel driver */ if (screen->model < chipModel_GC4000) { screen->specs.max_vs_uniforms = 168; screen->specs.max_ps_uniforms = 64; } else { screen->specs.max_vs_uniforms = 256; screen->specs.max_ps_uniforms = 256; } screen->specs.max_texture_size = VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048; screen->specs.max_rendertarget_size = VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048; return true; fail: return false; }
/* Allocate 2D texture or render target resource */ static struct pipe_resource * etna_screen_resource_create(struct pipe_screen *screen, const struct pipe_resource *templat) { struct etna_screen *priv = etna_screen(screen); assert(templat); unsigned element_size = util_format_get_blocksize(templat->format); if(!element_size) return NULL; /* Check input */ if(templat->target == PIPE_TEXTURE_CUBE) { assert(templat->array_size == 6); } else if (templat->target == PIPE_BUFFER) { assert(templat->format == PIPE_FORMAT_R8_UNORM); /* bytes; want TYPELESS or similar */ assert(templat->array_size == 1); assert(templat->height0 == 1); assert(templat->depth0 == 1); assert(templat->array_size == 1); assert(templat->last_level == 0); } else { assert(templat->array_size == 1); } assert(templat->width0 != 0); assert(templat->height0 != 0); assert(templat->depth0 != 0); assert(templat->array_size != 0); /* Figure out what tiling to use -- for now, assume that textures cannot be supertiled, and cannot be linear. * There is a feature flag SUPERTILED_TEXTURE (not supported on any known hw) that may allow this, as well * as LINEAR_TEXTURE_SUPPORT (supported on gc880 and gc2000 at least), but not sure how it works. * Buffers always have LINEAR layout. */ unsigned layout = ETNA_LAYOUT_LINEAR; if(templat->target != PIPE_BUFFER) { if(!(templat->bind & PIPE_BIND_SAMPLER_VIEW) && priv->specs.can_supertile && !DBG_ENABLED(ETNA_DBG_NO_SUPERTILE)) layout = ETNA_LAYOUT_SUPER_TILED; else layout = ETNA_LAYOUT_TILED; } /* XXX multi tiled formats */ /* Determine scaling for antialiasing, allow override using debug flag */ int nr_samples = templat->nr_samples; if((templat->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) && !(templat->bind & PIPE_BIND_SAMPLER_VIEW)) { if(DBG_ENABLED(ETNA_DBG_MSAA_2X)) nr_samples = 2; if(DBG_ENABLED(ETNA_DBG_MSAA_4X)) nr_samples = 4; } int msaa_xscale = 1, msaa_yscale = 1; if(!translate_samples_to_xyscale(nr_samples, &msaa_xscale, &msaa_yscale, NULL)) { /* Number of samples not supported */ assert(0); } /* Determine needed padding (alignment of height/width) */ unsigned paddingX = 0, paddingY = 0; unsigned halign = TEXTURE_HALIGN_FOUR; etna_layout_multiple(layout, priv->dev->chip.pixel_pipes, (templat->bind & PIPE_BIND_SAMPLER_VIEW) && !VIV_FEATURE(priv->dev, chipMinorFeatures1, TEXTURE_HALIGN), &paddingX, &paddingY, &halign); assert(paddingX && paddingY); /* determine mipmap levels */ struct etna_resource *resource = CALLOC_STRUCT(etna_resource); int max_mip_level = templat->last_level; if(unlikely(max_mip_level >= ETNA_NUM_LOD)) /* max LOD supported by hw */ max_mip_level = ETNA_NUM_LOD - 1; /* take care about DXTx formats, which have a divSize of non-1x1 * also: lower mipmaps are still 4x4 due to tiling. In as sense, compressed formats are already tiled. * XXX UYVY formats? */ unsigned divSizeX = util_format_get_blockwidth(templat->format); unsigned divSizeY = util_format_get_blockheight(templat->format); unsigned ix = 0; unsigned x = templat->width0, y = templat->height0; unsigned offset = 0; while(true) { struct etna_resource_level *mip = &resource->levels[ix]; mip->width = x; mip->height = y; mip->padded_width = align(x * msaa_xscale, paddingX); mip->padded_height = align(y * msaa_yscale, paddingY); mip->stride = align(mip->padded_width, divSizeX)/divSizeX * element_size; mip->offset = offset; mip->layer_stride = align(mip->padded_width, divSizeX)/divSizeX * align(mip->padded_height, divSizeY)/divSizeY * element_size; mip->size = templat->array_size * mip->layer_stride; offset += align(mip->size, ETNA_PE_ALIGNMENT); /* align mipmaps to 64 bytes to be able to render to them */ if(ix == max_mip_level || (x == 1 && y == 1)) break; // stop at last level x = MAX2(x >> 1, 1); y = MAX2(y >> 1, 1); ix += 1; } /* Determine memory size, and whether to create a tile status */ size_t rt_size = offset; /* determine memory type */ enum viv_surf_type memtype = VIV_SURF_UNKNOWN; if(templat->bind & PIPE_BIND_SAMPLER_VIEW) memtype = VIV_SURF_TEXTURE; else if(templat->bind & PIPE_BIND_RENDER_TARGET) memtype = VIV_SURF_RENDER_TARGET; else if(templat->bind & PIPE_BIND_DEPTH_STENCIL) memtype = VIV_SURF_DEPTH; else if(templat->bind & PIPE_BIND_INDEX_BUFFER) memtype = VIV_SURF_INDEX; else if(templat->bind & PIPE_BIND_VERTEX_BUFFER) memtype = VIV_SURF_VERTEX; DBG_F(ETNA_DBG_RESOURCE_MSGS, "%p: Allocate surface of %ix%i (padded to %ix%i) of format %s (%i bpe %ix%i), size %08zx flags %08x, memtype %i", resource, templat->width0, templat->height0, resource->levels[0].padded_width, resource->levels[0].padded_height, util_format_name(templat->format), element_size, divSizeX, divSizeY, rt_size, templat->bind, memtype); struct etna_vidmem *rt = 0; if(unlikely(etna_vidmem_alloc_linear(priv->dev, &rt, rt_size, memtype, VIV_POOL_DEFAULT, true) != ETNA_OK)) { BUG("Problem allocating video memory for resource"); return NULL; } resource->base = *templat; resource->base.last_level = ix; /* real last mipmap level */ resource->base.screen = screen; resource->base.nr_samples = nr_samples; resource->layout = layout; resource->halign = halign; resource->surface = rt; resource->ts = 0; /* TS is only created when first bound to surface */ pipe_reference_init(&resource->base.reference, 1); if(DBG_ENABLED(ETNA_DBG_ZERO)) { memset(resource->surface->logical, 0, rt_size); } for(unsigned ix=0; ix<=resource->base.last_level; ++ix) { struct etna_resource_level *mip = &resource->levels[ix]; mip->address = resource->surface->address + mip->offset; mip->logical = resource->surface->logical + mip->offset; DBG_F(ETNA_DBG_RESOURCE_MSGS, " %08x level %i: %ix%i (%i) stride=%i layer_stride=%i", (int)mip->address, ix, (int)mip->width, (int)mip->height, (int)mip->size, (int)mip->stride, (int)mip->layer_stride); } return &resource->base; }