/**Function*************************************************************
Synopsis [Writes reached state BDD into a BLIF file.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Llb_ManDumpReached( DdManager * ddG, DdNode * bReached, char * pModel, char * pFileName )
{
FILE * pFile;
Vec_Ptr_t * vNamesIn, * vNamesOut;
char * pName;
int i, nDigits;
// reorder the BDD
Cudd_ReduceHeap( ddG, CUDD_REORDER_SYMM_SIFT, 1 );
// create input names
nDigits = Extra_Base10Log( Cudd_ReadSize(ddG) );
vNamesIn = Vec_PtrAlloc( Cudd_ReadSize(ddG) );
for ( i = 0; i < Cudd_ReadSize(ddG); i++ )
{
pName = Llb_ManGetDummyName( "ff", i, nDigits );
Vec_PtrPush( vNamesIn, Extra_UtilStrsav(pName) );
}
// create output names
vNamesOut = Vec_PtrAlloc( 1 );
Vec_PtrPush( vNamesOut, Extra_UtilStrsav("Reached") );
// write the file
pFile = fopen( pFileName, "wb" );
Cudd_DumpBlif( ddG, 1, &bReached, (char **)Vec_PtrArray(vNamesIn), (char **)Vec_PtrArray(vNamesOut), pModel, pFile, 0 );
fclose( pFile );
// cleanup
Vec_PtrForEachEntry( char *, vNamesIn, pName, i )
ABC_FREE( pName );
Vec_PtrForEachEntry( char *, vNamesOut, pName, i )
ABC_FREE( pName );
Vec_PtrFree( vNamesIn );
Vec_PtrFree( vNamesOut );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Frame_t * Abc_FrameAllocate()
{
Abc_Frame_t * p;
extern void define_cube_size( int n );
extern void set_espresso_flags();
// allocate and clean
p = ABC_CALLOC( Abc_Frame_t, 1 );
// get version
p->sVersion = Abc_UtilsGetVersion( p );
// set streams
p->Err = stderr;
p->Out = stdout;
p->Hst = NULL;
p->Status = -1;
p->nFrames = -1;
// set the starting step
p->nSteps = 1;
p->fBatchMode = 0;
// networks to be used by choice
p->vStore = Vec_PtrAlloc( 16 );
p->vAbcObjIds = Vec_IntAlloc( 0 );
// initialize decomposition manager
// define_cube_size(20);
// set_espresso_flags();
// initialize the trace manager
// Abc_HManStart();
p->vPlugInComBinPairs = Vec_PtrAlloc( 100 );
return p;
}
/**Function*************************************************************
Synopsis [Starts the AIG manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Ivy_Man_t * Ivy_ManStart()
{
Ivy_Man_t * p;
// start the manager
p = ALLOC( Ivy_Man_t, 1 );
memset( p, 0, sizeof(Ivy_Man_t) );
// perform initializations
p->Ghost.Id = -1;
p->nTravIds = 1;
p->fCatchExor = 1;
// allocate arrays for nodes
p->vPis = Vec_PtrAlloc( 100 );
p->vPos = Vec_PtrAlloc( 100 );
p->vBufs = Vec_PtrAlloc( 100 );
p->vObjs = Vec_PtrAlloc( 100 );
// prepare the internal memory manager
Ivy_ManStartMemory( p );
// create the constant node
p->pConst1 = Ivy_ManFetchMemory( p );
p->pConst1->fPhase = 1;
Vec_PtrPush( p->vObjs, p->pConst1 );
p->nCreated = 1;
// start the table
p->nTableSize = 10007;
p->pTable = ALLOC( int, p->nTableSize );
memset( p->pTable, 0, sizeof(int) * p->nTableSize );
return p;
}
/**Function*************************************************************
Synopsis [Starts the AIG manager.]
Description [The argument of this procedure is a soft limit on the
the number of nodes, or 0 if the limit is unknown.]
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Aig_ManStart( int nNodesMax )
{
Aig_Man_t * p;
if ( nNodesMax <= 0 )
nNodesMax = 10007;
// start the manager
p = ALLOC( Aig_Man_t, 1 );
memset( p, 0, sizeof(Aig_Man_t) );
// perform initializations
p->nTravIds = 1;
p->fCatchExor = 0;
// allocate arrays for nodes
p->vPis = Vec_PtrAlloc( 100 );
p->vPos = Vec_PtrAlloc( 100 );
p->vObjs = Vec_PtrAlloc( 1000 );
p->vBufs = Vec_PtrAlloc( 100 );
// prepare the internal memory manager
p->pMemObjs = Aig_MmFixedStart( sizeof(Aig_Obj_t), nNodesMax );
// create the constant node
p->pConst1 = Aig_ManFetchMemory( p );
p->pConst1->Type = AIG_OBJ_CONST1;
p->pConst1->fPhase = 1;
p->nObjs[AIG_OBJ_CONST1]++;
// start the table
p->nTableSize = Aig_PrimeCudd( nNodesMax );
p->pTable = ALLOC( Aig_Obj_t *, p->nTableSize );
memset( p->pTable, 0, sizeof(Aig_Obj_t *) * p->nTableSize );
return p;
}
/**Function*************************************************************
Synopsis [Starts the AIG manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Hop_Man_t * Hop_ManStart()
{
Hop_Man_t * p;
// start the manager
p = ALLOC( Hop_Man_t, 1 );
memset( p, 0, sizeof(Hop_Man_t) );
// perform initializations
p->nTravIds = 1;
p->fRefCount = 1;
p->fCatchExor = 0;
// allocate arrays for nodes
p->vPis = Vec_PtrAlloc( 100 );
p->vPos = Vec_PtrAlloc( 100 );
// prepare the internal memory manager
Hop_ManStartMemory( p );
// create the constant node
p->pConst1 = Hop_ManFetchMemory( p );
p->pConst1->Type = AIG_CONST1;
p->pConst1->fPhase = 1;
p->nCreated = 1;
// start the table
// p->nTableSize = 107;
p->nTableSize = 10007;
p->pTable = ALLOC( Hop_Obj_t *, p->nTableSize );
memset( p->pTable, 0, sizeof(Hop_Obj_t *) * p->nTableSize );
return p;
}
/**Function*************************************************************
Synopsis [Start the memory manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Part_Man_t * Part_ManStart( int nChunkSize, int nStepSize )
{
Part_Man_t * p;
p = ALLOC( Part_Man_t, 1 );
memset( p, 0, sizeof(Part_Man_t) );
p->nChunkSize = nChunkSize;
p->nStepSize = nStepSize;
p->vMemory = Vec_PtrAlloc( 1000 );
p->vFree = Vec_PtrAlloc( 1000 );
return p;
}
/**Function*************************************************************
Synopsis [Sets up the SAT sat_solver.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NtkMiterSatCreateInt( sat_solver * pSat, Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pNode, * pFanin, * pNodeC, * pNodeT, * pNodeE;
Vec_Ptr_t * vNodes, * vSuper;
Vec_Int_t * vVars;
int i, k, fUseMuxes = 1;
// int fOrderCiVarsFirst = 0;
int RetValue = 0;
assert( Abc_NtkIsStrash(pNtk) );
// clean the CI node pointers
Abc_NtkForEachCi( pNtk, pNode, i )
pNode->pCopy = NULL;
// start the data structures
vNodes = Vec_PtrAlloc( 1000 ); // the nodes corresponding to vars in the sat_solver
vSuper = Vec_PtrAlloc( 100 ); // the nodes belonging to the given implication supergate
vVars = Vec_IntAlloc( 100 ); // the temporary array for variables in the clause
// add the clause for the constant node
pNode = Abc_AigConst1(pNtk);
pNode->fMarkA = 1;
pNode->pCopy = (Abc_Obj_t *)(ABC_PTRINT_T)vNodes->nSize;
Vec_PtrPush( vNodes, pNode );
Abc_NtkClauseTriv( pSat, pNode, vVars );
/*
// add the PI variables first
Abc_NtkForEachCi( pNtk, pNode, i )
{
pNode->fMarkA = 1;
pNode->pCopy = (Abc_Obj_t *)vNodes->nSize;
Vec_PtrPush( vNodes, pNode );
}
*/
// collect the nodes that need clauses and top-level assignments
Vec_PtrClear( vSuper );
Abc_NtkForEachCo( pNtk, pNode, i )
{
// get the fanin
pFanin = Abc_ObjFanin0(pNode);
// create the node's variable
if ( pFanin->fMarkA == 0 )
{
pFanin->fMarkA = 1;
pFanin->pCopy = (Abc_Obj_t *)(ABC_PTRINT_T)vNodes->nSize;
Vec_PtrPush( vNodes, pFanin );
}
// add the trivial clause
Vec_PtrPush( vSuper, Abc_ObjChild0(pNode) );
}
/**Function*************************************************************
Synopsis [Starts rewriting manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Rwr_Man_t * Rwr_ManStart( bool fPrecompute )
{
Dec_Man_t * pManDec;
Rwr_Man_t * p;
int clk = clock();
clk = clock();
p = ALLOC( Rwr_Man_t, 1 );
memset( p, 0, sizeof(Rwr_Man_t) );
p->nFuncs = (1<<16);
pManDec = Abc_FrameReadManDec();
p->puCanons = pManDec->puCanons;
p->pPhases = pManDec->pPhases;
p->pPerms = pManDec->pPerms;
p->pMap = pManDec->pMap;
// initialize practical NPN classes
p->pPractical = Rwr_ManGetPractical( p );
// create the table
p->pTable = ALLOC( Rwr_Node_t *, p->nFuncs );
memset( p->pTable, 0, sizeof(Rwr_Node_t *) * p->nFuncs );
// create the elementary nodes
p->pMmNode = Extra_MmFixedStart( sizeof(Rwr_Node_t) );
p->vForest = Vec_PtrAlloc( 100 );
Rwr_ManAddVar( p, 0x0000, fPrecompute ); // constant 0
Rwr_ManAddVar( p, 0xAAAA, fPrecompute ); // var A
Rwr_ManAddVar( p, 0xCCCC, fPrecompute ); // var B
Rwr_ManAddVar( p, 0xF0F0, fPrecompute ); // var C
Rwr_ManAddVar( p, 0xFF00, fPrecompute ); // var D
p->nClasses = 5;
// other stuff
p->nTravIds = 1;
p->pPerms4 = Extra_Permutations( 4 );
p->vLevNums = Vec_IntAlloc( 50 );
p->vFanins = Vec_PtrAlloc( 50 );
p->vFaninsCur = Vec_PtrAlloc( 50 );
p->vNodesTemp = Vec_PtrAlloc( 50 );
if ( fPrecompute )
{ // precompute subgraphs
Rwr_ManPrecompute( p );
// Rwr_ManPrint( p );
Rwr_ManWriteToArray( p );
}
else
{ // load saved subgraphs
Rwr_ManLoadFromArray( p, 0 );
// Rwr_ManPrint( p );
Rwr_ManPreprocess( p );
}
p->timeStart = clock() - clk;
return p;
}
/**Function*************************************************************
Synopsis [Starts representation of equivalence classes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Dch_Cla_t * Dch_ClassesStart( Aig_Man_t * pAig )
{
Dch_Cla_t * p;
p = ABC_ALLOC( Dch_Cla_t, 1 );
memset( p, 0, sizeof(Dch_Cla_t) );
p->pAig = pAig;
p->pId2Class = ABC_CALLOC( Aig_Obj_t **, Aig_ManObjNumMax(pAig) );
p->pClassSizes = ABC_CALLOC( int, Aig_ManObjNumMax(pAig) );
p->vClassOld = Vec_PtrAlloc( 100 );
p->vClassNew = Vec_PtrAlloc( 100 );
assert( pAig->pReprs == NULL );
Aig_ManReprStart( pAig, Aig_ManObjNumMax(pAig) );
return p;
}
/**Function*************************************************************
Synopsis [Performs area recovery for each node.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void If_ManImproveExpand( If_Man_t * p, int nLimit )
{
Vec_Ptr_t * vFront, * vFrontOld, * vVisited;
If_Obj_t * pObj;
int i;
vFront = Vec_PtrAlloc( nLimit );
vFrontOld = Vec_PtrAlloc( nLimit );
vVisited = Vec_PtrAlloc( 100 );
// iterate through all nodes in the topological order
If_ManForEachNode( p, pObj, i )
If_ManImproveNodeExpand( p, pObj, nLimit, vFront, vFrontOld, vVisited );
Vec_PtrFree( vFront );
Vec_PtrFree( vFrontOld );
Vec_PtrFree( vVisited );
}
/**Function*************************************************************
Synopsis [Marks and collects the TFI cone of the node.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Abc_MfsWinMarkTfi( Abc_Obj_t * pNode )
{
Vec_Ptr_t * vCone;
vCone = Vec_PtrAlloc( 100 );
Abc_MfsWinMarkTfi_rec( pNode, vCone );
return vCone;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Bus_Man_t * Bus_ManStart( Abc_Ntk_t * pNtk, SC_Lib * pLib, SC_BusPars * pPars )
{
Bus_Man_t * p;
p = ABC_CALLOC( Bus_Man_t, 1 );
p->pPars = pPars;
p->pNtk = pNtk;
p->pLib = pLib;
p->pInv = Abc_SclFindInvertor(pLib, pPars->fAddBufs)->pRepr->pPrev;//->pAve;
if ( pPars->fUseWireLoads )
{
if ( pNtk->pWLoadUsed == NULL )
{
p->pWLoadUsed = Abc_SclFindWireLoadModel( pLib, Abc_SclGetTotalArea(pNtk) );
pNtk->pWLoadUsed = Abc_UtilStrsav( p->pWLoadUsed->pName );
}
else
p->pWLoadUsed = Abc_SclFetchWireLoadModel( pLib, pNtk->pWLoadUsed );
}
if ( p->pWLoadUsed )
p->vWireCaps = Abc_SclFindWireCaps( p->pWLoadUsed );
p->vFanouts = Vec_PtrAlloc( 100 );
p->vCins = Vec_FltAlloc( 2*Abc_NtkObjNumMax(pNtk) + 1000 );
p->vETimes = Vec_FltAlloc( 2*Abc_NtkObjNumMax(pNtk) + 1000 );
p->vLoads = Vec_FltAlloc( 2*Abc_NtkObjNumMax(pNtk) + 1000 );
p->vDepts = Vec_FltAlloc( 2*Abc_NtkObjNumMax(pNtk) + 1000 );
Vec_FltFill( p->vCins, Abc_NtkObjNumMax(pNtk), 0 );
Vec_FltFill( p->vETimes, Abc_NtkObjNumMax(pNtk), 0 );
Vec_FltFill( p->vLoads, Abc_NtkObjNumMax(pNtk), 0 );
Vec_FltFill( p->vDepts, Abc_NtkObjNumMax(pNtk), 0 );
pNtk->pBSMan = p;
return p;
}
/**Function*************************************************************
Synopsis [Returns the nodes whose values are implied by pNode.]
Description [Attention! Both pNode and results can be complemented!
Also important: Currently, this procedure only does backward propagation.
In general, it may find more implications if forward propagation is enabled.]
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Aig_ManFindImplications( Aig_Man_t * p, Aig_Obj_t * pNode )
{
Vec_Ptr_t * vImplics;
vImplics = Vec_PtrAlloc( 100 );
Aig_ManFindImplications_rec( pNode, vImplics );
return vImplics;
}
/**Function*************************************************************
Synopsis [Creates a multi-input multi-output box in the hierarchical design.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Io_ReadBlifNetworkSubcircuit( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens )
{
Abc_Obj_t * pBox;
Vec_Ptr_t * vNames;
char * pName;
int i;
// create a new node and add it to the network
if ( vTokens->nSize < 3 )
{
p->LineCur = Extra_FileReaderGetLineNumber(p->pReader, 0);
sprintf( p->sError, "The .subcircuit line has less than three tokens." );
Io_ReadBlifPrintErrorMessage( p );
return 1;
}
// store the names of formal/actual inputs/outputs of the box
vNames = Vec_PtrAlloc( 10 );
Vec_PtrForEachEntryStart( char *, vTokens, pName, i, 1 )
// Vec_PtrPush( vNames, Abc_NtkRegisterName(p->pNtkCur, pName) );
Vec_PtrPush( vNames, Extra_UtilStrsav(pName) ); // memory leak!!!
// create a new box and add it to the network
pBox = Abc_NtkCreateBlackbox( p->pNtkCur );
// set the pointer to the node names
Abc_ObjSetData( pBox, vNames );
// remember the line of the file
pBox->pCopy = (Abc_Obj_t *)(ABC_PTRINT_T)Extra_FileReaderGetLineNumber(p->pReader, 0);
return 0;
}
/**Function*************************************************************
Synopsis [Builds implication supergate.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Obj_t * Dar_BalanceBuildSuperTop( Aig_Man_t * p, Vec_Ptr_t * vSuper, Aig_Type_t Type, int fUpdateLevel, int nLutSize )
{
Vec_Ptr_t * vSubset;
Aig_Obj_t * pObj;
int i, nBaseSizeAll, nBaseSize;
assert( vSuper->nSize > 1 );
// sort the new nodes by level in the decreasing order
Vec_PtrSort( vSuper, (int (*)(void))Aig_NodeCompareLevelsDecrease );
// add one LUT at a time
while ( Vec_PtrSize(vSuper) > 1 )
{
// isolate the group of nodes with nLutSize inputs
nBaseSizeAll = 0;
vSubset = Vec_PtrAlloc( nLutSize );
Vec_PtrForEachEntryReverse( Aig_Obj_t *, vSuper, pObj, i )
{
nBaseSize = Aig_BaseSize( p, pObj, nLutSize );
if ( nBaseSizeAll + nBaseSize > nLutSize && Vec_PtrSize(vSubset) > 1 )
break;
nBaseSizeAll += nBaseSize;
Vec_PtrPush( vSubset, pObj );
}
// remove them from vSuper
Vec_PtrShrink( vSuper, Vec_PtrSize(vSuper) - Vec_PtrSize(vSubset) );
// create the new supergate
pObj = Dar_BalanceBuildSuper( p, vSubset, Type, fUpdateLevel );
Vec_PtrFree( vSubset );
// add the new output
Dar_BalancePushUniqueOrderByLevel( vSuper, pObj, Type == AIG_OBJ_EXOR );
}
/**Function*************************************************************
Synopsis [Selects gates useful for area-only mapping.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Amap_LibSelectGates( Amap_Lib_t * p, int fVerbose )
{
Vec_Ptr_t * vSelect;
Amap_Gat_t * pGate, * pGate2;
int i, k;//, clk = Abc_Clock();
p->pGate0 = Amap_LibFindGate( p, 0 );
p->pGate1 = Amap_LibFindGate( p, ~0 );
p->pGateBuf = Amap_LibFindGate( p, 0xAAAAAAAA );
p->pGateInv = Amap_LibFindGate( p, ~0xAAAAAAAA );
vSelect = Vec_PtrAlloc( 100 );
Vec_PtrForEachEntry( Amap_Gat_t *, p->vSorted, pGate, i )
{
if ( pGate->pFunc == NULL || pGate->pTwin != NULL )
continue;
Vec_PtrForEachEntryStop( Amap_Gat_t *, p->vSorted, pGate2, k, i )
{
if ( pGate2->pFunc == NULL || pGate2->pTwin != NULL )
continue;
if ( pGate2->nPins != pGate->nPins )
continue;
if ( !memcmp( pGate2->pFunc, pGate->pFunc, sizeof(unsigned) * Abc_TruthWordNum(pGate->nPins) ) )
break;
}
if ( k < i )
continue;
Vec_PtrPush( vSelect, pGate );
}
return vSelect;
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Allocs a library.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Amap_Lib_t * Amap_LibAlloc()
{
Amap_Lib_t * p;
p = (Amap_Lib_t *)ABC_ALLOC( Amap_Lib_t, 1 );
memset( p, 0, sizeof(Amap_Lib_t) );
p->vGates = Vec_PtrAlloc( 100 );
p->pMemGates = Aig_MmFlexStart();
p->pMemSet = Aig_MmFlexStart();
return p;
}
/**Function*************************************************************
Synopsis [For each cut, returns PIs that can be quantified.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Llb_ManCutSupps( Aig_Man_t * p, Vec_Ptr_t * vResult )
{
Vec_Ptr_t * vSupps, * vOne, * vLower, * vUpper;
int i;
vSupps = Vec_PtrAlloc( 100 );
Vec_PtrPush( vSupps, Vec_PtrAlloc(0) );
vLower = (Vec_Ptr_t *)Vec_PtrEntry( vResult, 0 );
Vec_PtrForEachEntryStart( Vec_Ptr_t *, vResult, vUpper, i, 1 )
{
vOne = Llb_ManCutSupp( p, vLower, vUpper );
Vec_PtrPush( vSupps, vOne );
vLower = vUpper;
}
assert( Vec_PtrSize(vSupps) == Vec_PtrSize(vResult) );
return vSupps;
}
/**Function*************************************************************
Synopsis [Adds strashed nodes for one node.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_ManSpeedupNode( Nwk_Man_t * pNtk, Aig_Man_t * pAig, Nwk_Obj_t * pNode, Vec_Ptr_t * vLeaves, Vec_Ptr_t * vTimes )
{
Vec_Ptr_t * vNodes;
Nwk_Obj_t * pObj, * pObj2;
Aig_Obj_t * ppCofs[32], * pAnd, * pTemp;
int nCofs, i, k, nSkip;
// quit of regulars are the same
Vec_PtrForEachEntry( Nwk_Obj_t *, vLeaves, pObj, i )
Vec_PtrForEachEntry( Nwk_Obj_t *, vLeaves, pObj2, k )
if ( i != k && Aig_Regular((Aig_Obj_t *)pObj->pCopy) == Aig_Regular((Aig_Obj_t *)pObj2->pCopy) )
{
// printf( "Identical after structural hashing!!!\n" );
return;
}
// collect the AIG nodes
vNodes = Vec_PtrAlloc( 100 );
Aig_ManIncrementTravId( pAig );
Aig_ObjSetTravIdCurrent( pAig, Aig_ManConst1(pAig) );
Vec_PtrForEachEntry( Nwk_Obj_t *, vLeaves, pObj, i )
{
pAnd = (Aig_Obj_t *)pObj->pCopy;
Aig_ObjSetTravIdCurrent( pAig, Aig_Regular(pAnd) );
}
/**Function*************************************************************
Synopsis [Starts the simulation manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Sim_Man_t * Sim_ManStart( Abc_Ntk_t * pNtk, int fLightweight )
{
Sim_Man_t * p;
// start the manager
p = ALLOC( Sim_Man_t, 1 );
memset( p, 0, sizeof(Sim_Man_t) );
p->pNtk = pNtk;
p->nInputs = Abc_NtkCiNum(p->pNtk);
p->nOutputs = Abc_NtkCoNum(p->pNtk);
// internal simulation information
p->nSimBits = 2048;
p->nSimWords = SIM_NUM_WORDS(p->nSimBits);
p->vSim0 = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), p->nSimWords, 0 );
p->fLightweight = fLightweight;
if (!p->fLightweight) {
p->vSim1 = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), p->nSimWords, 0 );
// support information
p->nSuppBits = Abc_NtkCiNum(pNtk);
p->nSuppWords = SIM_NUM_WORDS(p->nSuppBits);
p->vSuppStr = Sim_ComputeStrSupp( pNtk );
p->vSuppFun = Sim_UtilInfoAlloc( Abc_NtkCoNum(p->pNtk), p->nSuppWords, 1 );
// other data
p->pMmPat = Extra_MmFixedStart( sizeof(Sim_Pat_t) + p->nSuppWords * sizeof(unsigned) );
p->vFifo = Vec_PtrAlloc( 100 );
p->vDiffs = Vec_IntAlloc( 100 );
// allocate support targets (array of unresolved outputs for each input)
p->vSuppTargs = Vec_VecStart( p->nInputs );
}
return p;
}
/**Function*************************************************************
Synopsis [Computes supports of the partitions.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Llb_ImgSupports( Aig_Man_t * p, Vec_Ptr_t * vDdMans, Vec_Int_t * vStart, Vec_Int_t * vStop, int fAddPis, int fVerbose )
{
Vec_Ptr_t * vSupps;
Vec_Int_t * vOne;
Aig_Obj_t * pObj;
DdManager * dd;
DdNode * bSupp, * bTemp;
int i, Entry, nSize;
nSize = Cudd_ReadSize( (DdManager *)Vec_PtrEntry( vDdMans, 0 ) );
vSupps = Vec_PtrAlloc( 100 );
// create initial
vOne = Vec_IntStart( nSize );
Vec_IntForEachEntry( vStart, Entry, i )
Vec_IntWriteEntry( vOne, Entry, 1 );
Vec_PtrPush( vSupps, vOne );
// create intermediate
Vec_PtrForEachEntry( DdManager *, vDdMans, dd, i )
{
vOne = Vec_IntStart( nSize );
bSupp = Cudd_Support( dd, dd->bFunc ); Cudd_Ref( bSupp );
for ( bTemp = bSupp; bTemp != Cudd_ReadOne(dd); bTemp = cuddT(bTemp) )
Vec_IntWriteEntry( vOne, bTemp->index, 1 );
Cudd_RecursiveDeref( dd, bSupp );
Vec_PtrPush( vSupps, vOne );
}
/**Function*************************************************************
Synopsis [Verifies the fanouts.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Ivy_ManCheckFanouts( Ivy_Man_t * p )
{
Vec_Ptr_t * vFanouts;
Ivy_Obj_t * pObj, * pFanout, * pFanin;
int i, k, RetValue = 1;
if ( !p->fFanout )
return 1;
vFanouts = Vec_PtrAlloc( 100 );
// make sure every fanin is a fanout
Ivy_ManForEachObj( p, pObj, i )
{
pFanin = Ivy_ObjFanin0(pObj);
if ( pFanin == NULL )
continue;
Ivy_ObjForEachFanout( p, pFanin, vFanouts, pFanout, k )
if ( pFanout == pObj )
break;
if ( k == Vec_PtrSize(vFanouts) )
{
printf( "Node %d is a fanin of node %d but the fanout is not there.\n", pFanin->Id, pObj->Id );
RetValue = 0;
}
pFanin = Ivy_ObjFanin1(pObj);
if ( pFanin == NULL )
continue;
Ivy_ObjForEachFanout( p, pFanin, vFanouts, pFanout, k )
if ( pFanout == pObj )
break;
if ( k == Vec_PtrSize(vFanouts) )
{
printf( "Node %d is a fanin of node %d but the fanout is not there.\n", pFanin->Id, pObj->Id );
RetValue = 0;
}
// check that the previous fanout has the same fanin
if ( pObj->pPrevFan0 )
{
if ( Ivy_ObjFanin0(pObj->pPrevFan0) != Ivy_ObjFanin0(pObj) &&
Ivy_ObjFanin0(pObj->pPrevFan0) != Ivy_ObjFanin1(pObj) &&
Ivy_ObjFanin1(pObj->pPrevFan0) != Ivy_ObjFanin0(pObj) &&
Ivy_ObjFanin1(pObj->pPrevFan0) != Ivy_ObjFanin1(pObj) )
{
printf( "Node %d has prev %d without common fanin.\n", pObj->Id, pObj->pPrevFan0->Id );
RetValue = 0;
}
}
// check that the previous fanout has the same fanin
if ( pObj->pPrevFan1 )
{
if ( Ivy_ObjFanin0(pObj->pPrevFan1) != Ivy_ObjFanin0(pObj) &&
Ivy_ObjFanin0(pObj->pPrevFan1) != Ivy_ObjFanin1(pObj) &&
Ivy_ObjFanin1(pObj->pPrevFan1) != Ivy_ObjFanin0(pObj) &&
Ivy_ObjFanin1(pObj->pPrevFan1) != Ivy_ObjFanin1(pObj) )
{
printf( "Node %d has prev %d without common fanin.\n", pObj->Id, pObj->pPrevFan1->Id );
RetValue = 0;
}
}
}
/**Function*************************************************************
Synopsis [Computes the set of complete clock gates.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Cgt_ManCompleteGates( Aig_Man_t * pAig, Vec_Vec_t * vGatesAll, int nOdcMax, int fVerbose )
{
Vec_Ptr_t * vFanout, * vGatesFull;
Aig_Obj_t * pGate, * pGateR;
int i, k;
vFanout = Vec_PtrAlloc( 100 );
vGatesFull = Vec_PtrAlloc( 100 );
Vec_VecForEachEntry( Aig_Obj_t *, vGatesAll, pGate, i, k )
{
pGateR = Aig_Regular(pGate);
if ( pGateR->fMarkA )
continue;
pGateR->fMarkA = 1;
Cgt_ManCollectFanoutPos( pAig, pGateR, vFanout );
if ( Cgt_ManCheckGateComplete( pAig, vGatesAll, pGate, vFanout ) )
Vec_PtrPush( vGatesFull, pGate );
}
/**Function*************************************************************
Synopsis [Starts the rewriting manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Ref_Man_t * Dar_ManRefStart( Aig_Man_t * pAig, Dar_RefPar_t * pPars )
{
Ref_Man_t * p;
// start the manager
p = ALLOC( Ref_Man_t, 1 );
memset( p, 0, sizeof(Ref_Man_t) );
p->pAig = pAig;
p->pPars = pPars;
// other data
p->vCuts = Vec_VecStart( pPars->nCutsMax );
p->vTruthElem = Vec_PtrAllocTruthTables( pPars->nLeafMax );
p->vTruthStore = Vec_PtrAllocSimInfo( 256, Kit_TruthWordNum(pPars->nLeafMax) );
p->vMemory = Vec_IntAlloc( 1 << 16 );
p->vCutNodes = Vec_PtrAlloc( 256 );
p->vLeavesBest = Vec_PtrAlloc( pPars->nLeafMax );
return p;
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Cov_Man_t * Cov_ManAlloc( Abc_Ntk_t * pNtk, int nFaninMax )
{
Cov_Man_t * pMan;
Cov_Obj_t * pMem;
Abc_Obj_t * pObj;
int i;
assert( pNtk->pManCut == NULL );
// start the manager
pMan = ABC_ALLOC( Cov_Man_t, 1 );
memset( pMan, 0, sizeof(Cov_Man_t) );
pMan->nFaninMax = nFaninMax;
pMan->nCubesMax = 2 * pMan->nFaninMax;
pMan->nWords = Abc_BitWordNum( nFaninMax * 2 );
// get the cubes
pMan->vComTo0 = Vec_IntAlloc( 2*nFaninMax );
pMan->vComTo1 = Vec_IntAlloc( 2*nFaninMax );
pMan->vPairs0 = Vec_IntAlloc( nFaninMax );
pMan->vPairs1 = Vec_IntAlloc( nFaninMax );
pMan->vTriv0 = Vec_IntAlloc( 1 ); Vec_IntPush( pMan->vTriv0, -1 );
pMan->vTriv1 = Vec_IntAlloc( 1 ); Vec_IntPush( pMan->vTriv1, -1 );
// allocate memory for object structures
pMan->pMemory = pMem = ABC_ALLOC( Cov_Obj_t, sizeof(Cov_Obj_t) * Abc_NtkObjNumMax(pNtk) );
memset( pMem, 0, sizeof(Cov_Obj_t) * Abc_NtkObjNumMax(pNtk) );
// allocate storage for the pointers to the memory
pMan->vObjStrs = Vec_PtrAlloc( Abc_NtkObjNumMax(pNtk) );
Vec_PtrFill( pMan->vObjStrs, Abc_NtkObjNumMax(pNtk), NULL );
Abc_NtkForEachObj( pNtk, pObj, i )
Vec_PtrWriteEntry( pMan->vObjStrs, i, pMem + i );
// create the cube manager
pMan->pManMin = Min_ManAlloc( nFaninMax );
return pMan;
}
/**Fnction*************************************************************
Synopsis [Collects internal nodes in the DFS order.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Bbl_ManDfs( Bbl_Man_t * p )
{
Vec_Ptr_t * vNodes;
Bbl_Obj_t * pObj;
vNodes = Vec_PtrAlloc( 1000 );
Bbl_ManForEachObj( p, pObj )
if ( Bbl_ObjIsLut(pObj) )
Bbl_ManDfs_rec( pObj, vNodes );
return vNodes;
}
/**Function*************************************************************
Synopsis [Collects the supergate.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Saig_DetectConstrCollectSuper( Aig_Obj_t * pObj )
{
Vec_Ptr_t * vSuper;
assert( !Aig_IsComplement(pObj) );
assert( Aig_ObjIsAnd(pObj) );
vSuper = Vec_PtrAlloc( 4 );
Saig_DetectConstrCollectSuper_rec( Aig_ObjChild0(pObj), vSuper );
Saig_DetectConstrCollectSuper_rec( Aig_ObjChild1(pObj), vSuper );
return vSuper;
}
/**Function*************************************************************
Synopsis [Gets fanin node names.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Abc_NodeGetFaninNames( Abc_Obj_t * pNode )
{
Vec_Ptr_t * vNodes;
Abc_Obj_t * pFanin;
int i;
vNodes = Vec_PtrAlloc( 100 );
Abc_ObjForEachFanin( pNode, pFanin, i )
Vec_PtrPush( vNodes, Abc_UtilStrsav(Abc_ObjName(pFanin)) );
return vNodes;
}
/**Function*************************************************************
Synopsis [Computes and adds all single-cube divisors to storage.]
Description [This procedure should be called once when the matrix is
already contructed before the process of logic extraction begins..]
SideEffects []
SeeAlso []
***********************************************************************/
void Fxu_MatrixComputeSingles( Fxu_Matrix * p, int fUse0, int nSingleMax )
{
Fxu_Var * pVar;
Vec_Ptr_t * vSingles;
int i, k;
// set the weight limit
p->nWeightLimit = 1 - fUse0;
// iterate through columns in the matrix and collect single-cube divisors
vSingles = Vec_PtrAlloc( 10000 );
Fxu_MatrixForEachVariable( p, pVar )
Fxu_MatrixComputeSinglesOneCollect( p, pVar, vSingles );
p->nSingleTotal = Vec_PtrSize(vSingles) / 3;
// check if divisors should be filtered
if ( Vec_PtrSize(vSingles) > nSingleMax )
{
int * pWeigtCounts, nDivCount, Weight, i, c;;
assert( Vec_PtrSize(vSingles) % 3 == 0 );
// count how many divisors have the given weight
pWeigtCounts = ABC_ALLOC( int, 1000 );
memset( pWeigtCounts, 0, sizeof(int) * 1000 );
for ( i = 2; i < Vec_PtrSize(vSingles); i += 3 )
{
Weight = (int)(ABC_PTRUINT_T)Vec_PtrEntry(vSingles, i);
if ( Weight >= 999 )
pWeigtCounts[999]++;
else
pWeigtCounts[Weight]++;
}
// select the bound on the weight (above this bound, singles will be included)
nDivCount = 0;
for ( c = 999; c >= 0; c-- )
{
nDivCount += pWeigtCounts[c];
if ( nDivCount >= nSingleMax )
break;
}
ABC_FREE( pWeigtCounts );
// collect singles with the given costs
k = 0;
for ( i = 2; i < Vec_PtrSize(vSingles); i += 3 )
{
Weight = (int)(ABC_PTRUINT_T)Vec_PtrEntry(vSingles, i);
if ( Weight < c )
continue;
Vec_PtrWriteEntry( vSingles, k++, Vec_PtrEntry(vSingles, i-2) );
Vec_PtrWriteEntry( vSingles, k++, Vec_PtrEntry(vSingles, i-1) );
Vec_PtrWriteEntry( vSingles, k++, Vec_PtrEntry(vSingles, i) );
if ( k/3 == nSingleMax )
break;
}
Vec_PtrShrink( vSingles, k );
// adjust the weight limit
p->nWeightLimit = c;
}
Vec_Ptr_t * Wlc_NtkSimulate( Wlc_Ntk_t * p, Vec_Int_t * vNodes, int nWords, int nFrames )
{
Gia_Obj_t * pObj;
Vec_Ptr_t * vOne, * vRes;
Gia_Man_t * pGia = Wlc_NtkBitBlast( p, NULL, 0, 0 );
Wlc_Obj_t * pWlcObj;
int f, i, k, w, nBits, Counter = 0;
// allocate simulation info for one timeframe
Vec_WrdFreeP( &pGia->vSims );
pGia->vSims = Vec_WrdStart( Gia_ManObjNum(pGia) * nWords );
pGia->iPatsPi = nWords;
// allocate resulting simulation info
vRes = Vec_PtrAlloc( Vec_IntSize(vNodes) );
Wlc_NtkForEachObjVec( vNodes, p, pWlcObj, i )
{
nBits = Wlc_ObjRange(pWlcObj);
vOne = Vec_PtrAlloc( nBits );
for ( k = 0; k < nBits; k++ )
Vec_PtrPush( vOne, ABC_CALLOC(word, nWords * nFrames) );
Vec_PtrPush( vRes, vOne );
}