static void store_zeroX(uint16_t addr, uint8_t value) { if (addr == 0) { cbm2mem_set_bank_exec(value); } else if (addr == 1) { cbm2mem_set_bank_ind(value); } }
void store_zeroX(WORD addr, BYTE value) { if (addr == 0) { cbm2mem_set_bank_exec(value); } else if (addr == 1) { cbm2mem_set_bank_ind(value); } }
void zero_store(WORD addr, BYTE value) { if (addr == 0) { cbm2mem_set_bank_exec(value); } else if (addr == 1) { cbm2mem_set_bank_ind(value); } _mem_write_tab_ptr[0]((WORD)(addr & 0xff), value); }
void zero_store(uint16_t addr, uint8_t value) { if (addr == 0) { cbm2mem_set_bank_exec(value); } else if (addr == 1) { cbm2mem_set_bank_ind(value); } _mem_write_tab_ptr[0]((uint16_t)(addr & 0xff), value); }
static int mem_read_ram_snapshot_module(snapshot_t *p) { BYTE byte, vmajor, vminor; snapshot_module_t *m; BYTE config, hwconfig; int memsize; int effective_ramsize, effective_start; int bank0; m = snapshot_module_open(p, module_name, &vmajor, &vminor); if (m == NULL) return -1; if (vmajor != CBM2MEM_DUMP_VER_MAJOR) { snapshot_module_close(m); return -1; } SMR_B(m, &byte); memsize = ((int)byte) & 0xff; SMR_B(m, &config); SMR_B(m, &hwconfig); resources_set_int("ModelLine", hwconfig & 3); SMR_B(m, &byte); cbm2mem_set_bank_exec(byte); SMR_B(m, &byte); cbm2mem_set_bank_ind(byte); SMR_BA(m, mem_ram + 0xf0000, 0x0800); SMR_BA(m, mem_rom + 0xd000, 0x0800); /* calculate start and size of RAM to load */ /* ramsize starts counting at 0x10000 if less than 512k */ bank0 = config & 64; effective_ramsize = memsize << 7; effective_start = 0x10000; if (bank0 || effective_ramsize >= 512) { effective_start = 0; } if (bank0 && effective_ramsize < 512) { effective_ramsize -= 64; } SMR_BA(m, mem_ram + effective_start, memsize << 17); ramsize = effective_ramsize; cart08_ram = config & 1; cart1_ram = config & 2; cart2_ram = config & 4; cart4_ram = config & 8; cart6_ram = config & 16; cartC_ram = config & 32; if (memsize < 4) { SMR_BA(m, mem_ram + 0x10000, memsize << 17); } else { SMR_BA(m, mem_ram, memsize << 17); } if (memsize < 4) { /* if 1M memory, bank 15 is included */ if (config & 1) { SMR_BA(m, mem_ram + 0xf0800, 0x0800); } if (config & 2) { SMR_BA(m, mem_ram + 0xf1000, 0x1000); } if (config & 4) { SMR_BA(m, mem_ram + 0xf2000, 0x2000); } if (config & 8) { SMR_BA(m, mem_ram + 0xf4000, 0x2000); } if (config & 16) { SMR_BA(m, mem_ram + 0xf6000, 0x2000); } if (config & 32) { SMR_BA(m, mem_ram + 0xfc000, 0x1000); } } mem_initialize_memory(); snapshot_module_close(m); return 0; }