static int cpus_power_domain_off(uint32_t cpu_id, uint32_t pd_cfg) { uint32_t cpu_pd; uint32_t core_pm_value; cpu_pd = PD_CPUL0 + cpu_id; if (pmu_power_domain_st(cpu_pd) == pmu_pd_off) return 0; if (pd_cfg == core_pwr_pd) { if (check_cpu_wfie(cpu_id, CKECK_WFEI_MSK)) return -EINVAL; /* disable core_pm cfg */ mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), CORES_PM_DISABLE); set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg); pmu_power_domain_ctr(cpu_pd, pmu_pd_off); } else { set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg); core_pm_value = BIT(core_pm_en); if (pd_cfg == core_pwr_wfi_int) core_pm_value |= BIT(core_pm_int_wakeup_en); mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), core_pm_value); dsb(); } return 0; }
static int cpus_id_power_domain(uint32_t cluster, uint32_t cpu, uint32_t pd_state, uint32_t wfie_msk) { uint32_t pd; uint64_t mpidr; if (cluster) pd = PD_CPUB0 + cpu; else pd = PD_CPUL0 + cpu; if (pmu_power_domain_st(pd) == pd_state) return 0; if (pd_state == pmu_pd_off) { mpidr = (cluster << MPIDR_AFF1_SHIFT) | cpu; if (check_cpu_wfie(mpidr, wfie_msk)) return -EINVAL; } return pmu_power_domain_ctr(pd, pd_state); }