/*--------------------------------------------------------------------*/
void dma_setup(void)
{
/* DAC channel 1 shares DMA controller 2 Channel 3. */
/* Enable DMA2 clock and IRQ */
rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA2EN);
nvic_enable_irq(NVIC_DMA2_CHANNEL3_IRQ);
dma_channel_reset(DMA2,DMA_CHANNEL3);
dma_set_priority(DMA2,DMA_CHANNEL3,DMA_CCR_PL_LOW);
dma_set_memory_size(DMA2,DMA_CHANNEL3,DMA_CCR_MSIZE_8BIT);
dma_set_peripheral_size(DMA2,DMA_CHANNEL3,DMA_CCR_PSIZE_8BIT);
dma_enable_memory_increment_mode(DMA2,DMA_CHANNEL3);
dma_enable_circular_mode(DMA2,DMA_CHANNEL3);
dma_set_read_from_memory(DMA2,DMA_CHANNEL3);
/* The register to target is the DAC1 8-bit right justified data register */
dma_set_peripheral_address(DMA2,DMA_CHANNEL3,(uint32_t) &DAC_DHR8R1);
/* The array v[] is filled with the waveform data to be output */
dma_set_memory_address(DMA2,DMA_CHANNEL3,(uint32_t) v);
dma_set_number_of_data(DMA2,DMA_CHANNEL3,256);
dma_enable_transfer_complete_interrupt(DMA2, DMA_CHANNEL3);
dma_enable_channel(DMA2,DMA_CHANNEL3);
}
void acq_init()
{
/* Initialize amplifier control GPIO */
gpio_mode_setup(BANK_AMP, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO_AMP);
gpio_clear(BANK_AMP, GPIO_AMP);
gpio_mode_setup(BANK_LED, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO_LED);
gpio_clear(BANK_LED, GPIO_LED);
/* Initialize SPI GPIOs */
gpio_mode_setup(BANK_CS, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_CS);
gpio_mode_setup(BANK_SCLK, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_SCLK);
gpio_mode_setup(BANK_DOUT, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_DOUT);
gpio_set_af(BANK_CS, GPIO_AF6, GPIO_CS);
gpio_set_af(BANK_SCLK, GPIO_AF6, GPIO_SCLK);
gpio_set_af(BANK_DOUT, GPIO_AF6, GPIO_DOUT);
rcc_periph_clock_enable(RCC_SPI3);
acq_spi_init(SPI_C1);
rcc_periph_clock_enable(RCC_DMA1);
dma_channel_reset(DMA1, DMA_CHANNEL2);
dma_disable_channel(DMA1, DMA_CHANNEL2);
dma_set_peripheral_address(DMA1, DMA_CHANNEL2, (uint32_t)&SPI_DR(SPI_C1));
dma_set_memory_address(DMA1, DMA_CHANNEL2, (uint32_t)&acq_channel.buff);
dma_set_number_of_data(DMA1, DMA_CHANNEL2, BUFFER_SIZE);
dma_set_priority(DMA1, DMA_CHANNEL2, DMA_CCR_PL_MEDIUM);
dma_set_memory_size(DMA1, DMA_CHANNEL2, DMA_CCR_MSIZE_16BIT);
dma_set_peripheral_size(DMA1, DMA_CHANNEL2, DMA_CCR_PSIZE_16BIT);
dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL2);
dma_set_read_from_peripheral(DMA1, DMA_CHANNEL2);
dma_enable_circular_mode(DMA1, DMA_CHANNEL2);
nvic_set_priority(NVIC_DMA1_CHANNEL2_IRQ, PRIO_ACQ);
}
static void platform_init_adc() {
/* Set up DMA for the ADC */
nvic_enable_irq(NVIC_DMA2_STREAM0_IRQ);
nvic_set_priority(NVIC_DMA2_STREAM0_IRQ, 64);
/* Set up ADC */
for (int i = 0; i < NUM_SENSORS; ++i) {
if (config.sensors[i].method == SENSOR_ADC) {
adc_pins[i] = config.sensors[i].pin;
gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, (1<<adc_pins[i]));
}
}
adc_off(ADC1);
adc_enable_scan_mode(ADC1);
adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_15CYC);
adc_power_on(ADC1);
adc_disable_dma(ADC1);
adc_enable_dma(ADC1);
adc_clear_overrun_flag(ADC1);
adc_set_dma_continue(ADC1);
dma_stream_reset(DMA2, DMA_STREAM0);
dma_set_priority(DMA2, DMA_STREAM0, DMA_SxCR_PL_HIGH);
dma_set_memory_size(DMA2, DMA_STREAM0, DMA_SxCR_MSIZE_16BIT);
dma_set_peripheral_size(DMA2, DMA_STREAM0, DMA_SxCR_PSIZE_16BIT);
dma_enable_memory_increment_mode(DMA2, DMA_STREAM0);
dma_set_transfer_mode(DMA2, DMA_STREAM0, DMA_SxCR_DIR_PERIPHERAL_TO_MEM);
dma_enable_circular_mode(DMA2, DMA_STREAM0);
dma_set_peripheral_address(DMA2, DMA_STREAM0, (uint32_t) &ADC1_DR);
dma_set_memory_address(DMA2, DMA_STREAM0, (uint32_t) adc_dma_buf);
dma_set_number_of_data(DMA2, DMA_STREAM0, NUM_SENSORS);
dma_enable_transfer_complete_interrupt(DMA2, DMA_STREAM0);
dma_channel_select(DMA2, DMA_STREAM0, DMA_SxCR_CHSEL_0);
dma_enable_stream(DMA2, DMA_STREAM0);
adc_set_regular_sequence(ADC1, NUM_SENSORS, adc_pins);
}
/*--------------------------------------------------------------------*/
void dma_setup(void)
{
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_DMA2EN);
/* ADC1 uses DMA controller 2 Stream 0 channel 0. */
/* Enable DMA2 clock and IRQ */
nvic_enable_irq(NVIC_DMA2_STREAM0_IRQ);
dma_stream_reset(DMA2,DMA_STREAM0);
dma_set_priority(DMA2,DMA_STREAM0,DMA_SxCR_PL_LOW);
dma_set_peripheral_size(DMA2,DMA_STREAM0,DMA_SxCR_PSIZE_32BIT);
/* The register to target is the ADC regular data register */
dma_set_peripheral_address(DMA2,DMA_STREAM0,(uint32_t) &ADC1_DR);
/* The array v[] is filled with the waveform data to be output */
dma_set_memory_size(DMA2,DMA_STREAM0,DMA_SxCR_MSIZE_32BIT);
dma_set_memory_address(DMA2,DMA_STREAM0,(uint32_t) v);
dma_set_number_of_data(DMA2,DMA_STREAM0,64);
dma_set_transfer_mode(DMA2,DMA_STREAM0, DMA_SxCR_DIR_PERIPHERAL_TO_MEM);
dma_enable_memory_increment_mode(DMA2,DMA_STREAM0);
dma_enable_circular_mode(DMA2,DMA_STREAM0);
/* Don't use FIFO */
dma_enable_direct_mode(DMA2,DMA_STREAM0);
dma_enable_transfer_complete_interrupt(DMA2, DMA_STREAM0);
dma_channel_select(DMA2, DMA_STREAM0, DMA_SxCR_CHSEL_0);
dma_enable_stream(DMA2,DMA_STREAM0);
}
/*--------------------------------------------------------------------*/
static void dma_setup(void)
{
/* DAC channel 1 uses DMA controller 1 Stream 5 Channel 7. */
/* Enable DMA1 clock and IRQ */
rcc_periph_clock_enable(RCC_DMA1);
nvic_enable_irq(NVIC_DMA1_STREAM5_IRQ);
dma_stream_reset(DMA1, DMA_STREAM5);
dma_set_priority(DMA1, DMA_STREAM5, DMA_SxCR_PL_LOW);
dma_set_memory_size(DMA1, DMA_STREAM5, DMA_SxCR_MSIZE_8BIT);
dma_set_peripheral_size(DMA1, DMA_STREAM5, DMA_SxCR_PSIZE_8BIT);
dma_enable_memory_increment_mode(DMA1, DMA_STREAM5);
dma_enable_circular_mode(DMA1, DMA_STREAM5);
dma_set_transfer_mode(DMA1, DMA_STREAM5,
DMA_SxCR_DIR_MEM_TO_PERIPHERAL);
/* The register to target is the DAC1 8-bit right justified data
register */
dma_set_peripheral_address(DMA1, DMA_STREAM5, (uint32_t) &DAC_DHR8R1);
/* The array v[] is filled with the waveform data to be output */
dma_set_memory_address(DMA1, DMA_STREAM5, (uint32_t) waveform);
dma_set_number_of_data(DMA1, DMA_STREAM5, 256);
dma_enable_transfer_complete_interrupt(DMA1, DMA_STREAM5);
dma_channel_select(DMA1, DMA_STREAM5, DMA_SxCR_CHSEL_7);
dma_enable_stream(DMA1, DMA_STREAM5);
}
static int timer_dma(uint8_t *tx_buf, int tx_len)
{
dma_int_enable();
/* Reset DMA channels*/
dma_channel_reset(DMA1, DMA_CHANNEL3);
/* Set up tx dma */
dma_set_peripheral_address(DMA1, DMA_CHANNEL3, (uint32_t)&TIM_CCR2(TIM3));
dma_set_memory_address(DMA1, DMA_CHANNEL3, (uint32_t)tx_buf);
dma_set_number_of_data(DMA1, DMA_CHANNEL3, tx_len);
dma_set_read_from_memory(DMA1, DMA_CHANNEL3);
dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL3);
dma_set_peripheral_size(DMA1, DMA_CHANNEL3, DMA_CCR_PSIZE_32BIT);
dma_set_memory_size(DMA1, DMA_CHANNEL3, DMA_CCR_MSIZE_8BIT);
dma_set_priority(DMA1, DMA_CHANNEL3, DMA_CCR_PL_HIGH);
dma_enable_circular_mode(DMA1, DMA_CHANNEL3);
dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL3);
dma_enable_half_transfer_interrupt(DMA1, DMA_CHANNEL3);
dma_enable_channel(DMA1, DMA_CHANNEL3);
return 0;
}
/**
* Initialize analog to digital converter
*/
void adc_init(adc_callback_t half_transfer_callback,
adc_callback_t transfer_complete_callback)
{
/* Reset adc_state. */
adc_state.dma_transfer_error_counter = 0;
adc_state.half_transfer_callback = half_transfer_callback;
adc_state.transfer_complete_callback = transfer_complete_callback;
/* Initialize peripheral clocks. */
rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA1EN);
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN);
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN);
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC2EN);
/* Initialize the ADC input GPIO. */
/* WARNING: this code is written to work with strip. On the strip
* hardware we are lucky and all the ADC channels are on the same bank
* so we can initialize all of them in one go. This code will need to be
* changed/improved if we ever have to support hardware that has the
* ADC's spread over more then one bank.
*/
gpio_set_mode(ADC_BANK, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_ANALOG, ADC_PORT_U_VOLTAGE |
ADC_PORT_V_VOLTAGE |
ADC_PORT_W_VOLTAGE |
ADC_PORT_V_BATT |
ADC_PORT_CURRENT);
/* Configure DMA for data aquisition. */
/* Channel 1 reacts to: ADC1, TIM2_CH3 and TIM4_CH1 */
dma_channel_reset(DMA1, DMA_CHANNEL1);
dma_set_peripheral_address(DMA1, DMA_CHANNEL1, (uint32_t)&ADC1_DR);
dma_set_memory_address(DMA1, DMA_CHANNEL1,
(uint32_t)adc_state.raw_data);
dma_set_number_of_data(DMA1, DMA_CHANNEL1, ADC_RAW_SAMPLE_COUNT/2);
dma_set_read_from_peripheral(DMA1, DMA_CHANNEL1);
dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL1);
dma_enable_circular_mode(DMA1, DMA_CHANNEL1);
dma_set_peripheral_size(DMA1, DMA_CHANNEL1, DMA_CCR_PSIZE_32BIT);
dma_set_memory_size(DMA1, DMA_CHANNEL1, DMA_CCR_MSIZE_32BIT);
dma_set_priority(DMA1, DMA_CHANNEL1, DMA_CCR_PL_VERY_HIGH);
dma_enable_half_transfer_interrupt(DMA1, DMA_CHANNEL1);
dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL1);
dma_enable_transfer_error_interrupt(DMA1, DMA_CHANNEL1);
dma_enable_channel(DMA1, DMA_CHANNEL1);
/* Configure interrupts in NVIC. */
nvic_set_priority(NVIC_DMA1_CHANNEL1_IRQ, 0);
nvic_enable_irq(NVIC_DMA1_CHANNEL1_IRQ);
/* Disable ADC's. */
adc_off(ADC1);
adc_off(ADC2);
/* Enable dualmode. */
adc_set_dual_mode(ADC_CR1_DUALMOD_RSM); /* Dualmode regular only. */
/* Configure the adc channels. */
adc_config(ADC1, adc1_channel_array);
adc_config(ADC2, adc2_channel_array);
/* Start converting. */
adc_start_conversion_regular(ADC1);
}