void mmc_wakeup(void) { int stat; stat = APB_Rd(MMC_LP_CTRL1); serial_put_hex(stat,32); f_serial_puts("MMC_LP_CTRL1\n"); wait_uart_empty(); stat = APB_Rd(MMC_CLK_CNTL); serial_put_hex(stat,32); f_serial_puts("MMC_CLK_CNTL\n"); wait_uart_empty(); do { stat = APB_Rd(UPCTL_STAT_ADDR); stat &= 0x7; if(stat == UPCTL_STAT_LOW_POWER) { APB_Wr(UPCTL_SCTL_ADDR, SCTL_CMD_WAKEUP); //while(stat != UPCTL_STAT_LOW_POWER); } else if(stat == UPCTL_STAT_INIT) { APB_Wr(UPCTL_SCTL_ADDR, SCTL_CMD_CONFIG); //while(stat != UPCTL_STAT_CONFIG); } else if(stat == UPCTL_STAT_CONFIG) { APB_Wr(UPCTL_SCTL_ADDR, SCTL_CMD_GO); //while(stat != UPCTL_STAT_ACCESS); } stat = APB_Rd(UPCTL_STAT_ADDR); stat &= 0x7; } while(stat != UPCTL_STAT_ACCESS); }
void print_key() { unsigned reg = 0xc8100000; unsigned i,data; for (i=0;i<0x750;i+=4) { data = readl(reg+i); serial_put_hex(reg+i,32); f_serial_puts("="); serial_put_hex(data,32); f_serial_puts("\n"); } }
int main(void) { unsigned cmd; char c; int i = 0,j; timer_init(); #ifdef POWER_OFF_VDDIO f_serial_puts("sleep ... off\n"); #else f_serial_puts("sleep .......\n"); #endif while(1){ cmd = readl(P_AO_RTI_STATUS_REG0); if(cmd == 0) { delay_ms(10); continue; } c = (char)cmd; if(c == 't') { #if (defined(POWER_OFF_VDDIO) || defined(POWER_OFF_HDMI_VCC) || defined(POWER_OFF_AVDD33) || defined(POWER_OFF_AVDD25)) init_I2C(); #endif copy_reboot_code(); enter_power_down(); break; } else if(c == 'q') { serial_puts(" - quit command loop\n"); writel(0,P_AO_RTI_STATUS_REG0); break; } else { serial_puts(" - cmd no support (ARC)\n"); } //command executed writel(0,P_AO_RTI_STATUS_REG0); } while(1){ asm(".long 0x003f236f"); //add sync instruction. asm("SLEEP"); } return 0; }
void copy_reboot_code_temp(volatile unsigned char * arm_base, unsigned int size) { int i; int code_size; volatile unsigned char* pcode = *(int *)(0x0004);//appf_arc_code_memory[1] code_size = *(int *)(0x0008);//appf_arc_code_memory[2] *(unsigned int *)arm_base = code_size; arm_base+=4; if (size - 4 < code_size) { f_serial_puts("Error: arm_reboot[] is too small!\n"); return; } //copy new code for ARM restart for (i = 0; i < code_size; i++) { /* f_serial_puts("[ "); serial_put_hex(*arm_base,8); f_serial_puts(" , "); serial_put_hex(*pcode,8); f_serial_puts(" ] "); */ *arm_base = *pcode; pcode++; arm_base++; } }
void chip_power_on_at_24M() { writel(readl(P_AO_RTI_PIN_MUX_REG)&~(1 << 9),P_AO_RTI_PIN_MUX_REG); //open ddr writel(readl(P_AO_GPIO_O_EN_N)|(1 << 19),P_AO_GPIO_O_EN_N); writel(readl(P_AO_GPIO_O_EN_N)&~(1 << 3),P_AO_GPIO_O_EN_N); //wait_uart_empty(); writel(readl(P_AO_RTI_PIN_MUX_REG)&~(1 << 10),P_AO_RTI_PIN_MUX_REG); //open stb writel(readl(P_AO_GPIO_O_EN_N)&~(1 << 18),P_AO_GPIO_O_EN_N); writel(readl(P_AO_GPIO_O_EN_N)&~(1 << 2),P_AO_GPIO_O_EN_N); //udelay__(500); f_serial_puts("open vdde pwm \n"); //wait_uart_empty(); writel(readl(P_AO_RTI_PIN_MUX_REG)&~(1 << 29), P_AO_RTI_PIN_MUX_REG); //vdde pwm writel(readl(P_AO_RTI_PIN_MUX_REG)&~(1 << 21), P_AO_RTI_PIN_MUX_REG); writel(readl(P_AO_GPIO_O_EN_N)&~(1 << 28), P_AO_GPIO_O_EN_N); writel(readl(P_AO_GPIO_O_EN_N)&~(1 << 12), P_AO_GPIO_O_EN_N); //udelay__(500); //f_serial_puts("close Isolation \n"); //wait_uart_empty(); writel(readl(P_AO_RTI_PWR_CNTL_REG0)|(0x1 << 9),P_AO_RTI_PWR_CNTL_REG0 ); //close Isolation //udelay__(200); writel(readl(P_AO_RTI_PWR_CNTL_REG0)&~(0x3 << 3),P_AO_RTI_PWR_CNTL_REG0 ); //udelay__(200); }
void power_up_core(void) { f_serial_puts("power up core.\n"); wait_uart_empty(); //Just store P_HHI_SYS_CPU_CLK_CNTL. The A9 core will be reset later. // writel(hhi_sys_cpu_clk_cntl,0xc1100000 + 0x1067*4); }
//unsigned int hhi_sys_cpu_clk_cntl; void power_down_core(void) { f_serial_puts("power down core.\n"); wait_uart_empty(); //Enable the auto clock gate off which be pre-setting @ os_api.c // writel(readl(0xc1100000 + 0x1078*4)| 1<<1,0xc1100000 + 0x1078*4); // udelay(1); // writel(readl(0xc1100000 + 0x1078*4)& (~(1<<1)),0xc1100000 + 0x1078*4); //Set A9 clk for 24M/128 // hhi_sys_cpu_clk_cntl = readl(0xc1100000 + 0x1067*4); // writel(readl(0xc1100000 + 0x1067*4) & (~(3<<0)) | (3<<2) | (1<<7) | (0x3f<<8),0xc1100000 + 0x1067*4); }
void ddr_data_training(void) { int stat; //start trainning. // DDR PHY initialization // UPCTL enter cfg mode. MMC_Wr(UPCTL_SCTL_ADDR, 1); // init: 0, cfg: 1, go: 2, sleep: 3, wakeup: 4 //while ((MMC_Rd(UPCTL_STAT_ADDR) & 0x7 ) != 3 ) {} MMC_Wr( PUB_DTAR_ADDR, (0xFc0 | (0xFFFF <<12) | (7 << 28))); //let training address is 0x9fffff00; MMC_Wr( PUB_PIR_ADDR, 0x189); //MMC_Wr( PUB_PIR_ADDR, 0x69); //no training //DDR3_SDRAM_INIT_WAIT : while( !(MMC_Rd(PUB_PGSR_ADDR & 1))) {} //check data training result //check ZQ calibraration status. stat = MMC_Rd(PUB_ZQ0SR0_ADDR); serial_put_hex(stat,32); f_serial_puts(" PUB_ZQ0SR0\n"); stat = MMC_Rd(PUB_ZQ0SR1_ADDR); serial_put_hex(stat,32); f_serial_puts(" PUB_ZQ0SR1\n"); //check data training result. stat = MMC_Rd(PUB_DX0GSR0_ADDR); serial_put_hex(stat,32); f_serial_puts(" PUB_DX0GSR0\n"); wait_uart_empty(); stat = MMC_Rd(PUB_DX1GSR0_ADDR); serial_put_hex(stat,32); f_serial_puts(" PUB_DX1GSR0\n"); wait_uart_empty(); stat = MMC_Rd(PUB_DX2GSR0_ADDR); serial_put_hex(stat,32); f_serial_puts(" PUB_DX2GSR0\n"); wait_uart_empty(); stat = MMC_Rd(PUB_DX3GSR0_ADDR); serial_put_hex(stat,32); f_serial_puts(" PUB_DX3GSR0\n"); wait_uart_empty(); dbg_out("d",9); MMC_Wr(UPCTL_SCTL_ADDR, 2); // init: 0, cfg: 1, go: 2, sleep: 3, wakeup: 4 //while ((MMC_Rd(UPCTL_STAT_ADDR) & 0x7 ) != 3 ) {} }
void init_I2C() { unsigned v,reg; //struct aml_i2c_reg_ctrl* ctrl; //save gpio intr setting gpio_sel0 = readl(0xc8100084); gpio_mask = readl(0xc8100080); f_serial_puts("i2c init\n"); //1. set pinmux v = readl(P_AO_RTI_PIN_MUX_REG); //master v |= ((1<<5)|(1<<6)); v &= ~((1<<2)|(1<<24)|(1<<1)|(1<<23)); //slave // v |= ((1<<1)|(1<<2)|(1<<3)|(1<<4)); writel(v,P_AO_RTI_PIN_MUX_REG); udelay__(10000); reg = readl(P_AO_I2C_M_0_CONTROL_REG); reg &= 0xCFC00FFF; reg |= (I2C_CLK_DIV_IN_RESUME <<12); // at 24MHz, i2c speed to 100KHz writel(reg,P_AO_I2C_M_0_CONTROL_REG); writel(0,P_AO_I2C_M_0_TOKEN_LIST0); writel(0,P_AO_I2C_M_0_TOKEN_LIST1); // delay_ms(20); // delay_ms(1); udelay__(1000); }
void enter_power_down() { int i; unsigned int uboot_cmd_flag=readl(P_AO_RTI_STATUS_REG2);//u-boot suspend cmd flag unsigned int vcin_state = 0; int voltage = 0; int axp_ocv = 0; int wdt_flag; // First, we disable all memory accesses. f_serial_puts("step 1\n"); asm(".long 0x003f236f"); //add sync instruction. store_restore_plls(0); f_serial_puts("ddr self-refresh\n"); wait_uart_empty(); ddr_self_refresh(); f_serial_puts("CPU off...\n"); wait_uart_empty(); cpu_off(); f_serial_puts("CPU off done\n"); wait_uart_empty(); #ifdef CONFIG_CEC_WAKEUP hdmi_cec_func_config = readl(P_AO_DEBUG_REG0); f_serial_puts("CEC M8:uboot: P_AO_DEBUG_REG0:\n"); serial_put_hex(hdmi_cec_func_config,32); f_serial_puts("\n"); #endif if(p_arc_pwr_op->power_off_at_24M) p_arc_pwr_op->power_off_at_24M(); #ifdef CONFIG_M201_COSTDOWN /* for led */ clrbits_le32(P_AO_GPIO_O_EN_N,1<<18); setbits_le32(P_AO_GPIO_O_EN_N,1<<29); #endif // while(readl(0xc8100000) != 0x13151719) // {} //non 32k crystal oscillator platform DONT enter 32k in suspend mode #ifndef CONFIG_NON_32K switch_24M_to_32K(); #endif if(p_arc_pwr_op->power_off_at_32K_1) p_arc_pwr_op->power_off_at_32K_1(); if(p_arc_pwr_op->power_off_at_32K_2) p_arc_pwr_op->power_off_at_32K_2(); // gate off: bit0: REMOTE; bit3: UART #ifndef CONFIG_NON_32K writel(readl(P_AO_RTI_GEN_CNTL_REG0)&(~(0x8)),P_AO_RTI_GEN_CNTL_REG0); #endif if(uboot_cmd_flag == 0x87654321)//u-boot suspend cmd flag { if(p_arc_pwr_op->power_off_ddr15) p_arc_pwr_op->power_off_ddr15(); } wdt_flag=readl(P_WATCHDOG_TC)&(1<<19); if(wdt_flag) writel(readl(P_WATCHDOG_TC)&(~(1<<19)),P_WATCHDOG_TC); #if 1 vcin_state = p_arc_pwr_op->detect_key(uboot_cmd_flag); #else for(i=0;i<10;i++) { udelay__(1000); //udelay(1000); } #endif if(uboot_cmd_flag == 0x87654321)//u-boot suspend cmd flag { if(p_arc_pwr_op->power_on_ddr15) p_arc_pwr_op->power_on_ddr15(); } if(wdt_flag) writel((6*7812|((1<<16)-1))|(1<<19),P_WATCHDOG_TC); // gate on: bit0: REMOTE; bit3: UART writel(readl(P_AO_RTI_GEN_CNTL_REG0)|0x8,P_AO_RTI_GEN_CNTL_REG0); if(p_arc_pwr_op->power_on_at_32K_2) p_arc_pwr_op->power_on_at_32K_2(); if(p_arc_pwr_op->power_on_at_32K_1) p_arc_pwr_op->power_on_at_32K_1(); #ifndef CONFIG_NON_32K switch_32K_to_24M(); #endif // power on even more domains if(p_arc_pwr_op->power_on_at_24M) p_arc_pwr_op->power_on_at_24M(); uart_reset(); f_serial_puts("step 8: ddr resume\n"); wait_uart_empty(); ddr_resume(); #ifdef CONFIG_M201_COSTDOWN /* for led */ clrbits_le32(P_AO_GPIO_O_EN_N,1<<29); setbits_le32(P_AO_GPIO_O_EN_N,1<<18); #endif f_serial_puts("restore pll\n"); wait_uart_empty(); store_restore_plls(1);//Before switch back to clk81, we need set PLL if (uboot_cmd_flag == 0x87654321 && (vcin_state == FLAG_WAKEUP_PWROFF)) { /* * power off system before ARM is restarted */ f_serial_puts("no extern power shutdown\n"); wait_uart_empty(); p_arc_pwr_op->shut_down(); do { udelay__(2000 * 100); f_serial_puts("wait shutdown...\n"); wait_uart_empty(); }while(1); } #ifdef CONFIG_MESON_TRUSTZONE copy_reboot_code(temp_arm_base); #else copy_reboot_code(NULL); #endif writel(vcin_state,P_AO_RTI_STATUS_REG2); f_serial_puts("restart arm\n"); wait_uart_empty(); restart_arm(); if (uboot_cmd_flag == 0x87654321) { writel(0,P_AO_RTI_STATUS_REG2); writel(readl(P_AO_RTI_PWR_CNTL_REG0)|(1<<4),P_AO_RTI_PWR_CNTL_REG0); clrbits_le32(P_HHI_SYS_CPU_CLK_CNTL,1<<19); //writel(10,0xc1109904); writel(1<<19|1<<24|10,0xc1109900); do{udelay__(200);f_serial_puts("wait reset...\n");wait_uart_empty();}while(1); } }
void printf_arc(const char *str) { f_serial_puts(str); wait_uart_empty(); }
int main(void) { unsigned cmd; char c; int i = 0,j; timer_init(); #ifdef POWER_OFF_VDDIO f_serial_puts("sleep ... off\n"); #else f_serial_puts("sleep7 .......\n"); #endif while(1){ cmd = readl(P_AO_RTI_STATUS_REG0); if(cmd == 0) { delay_ms(10); continue; } c = (char)cmd; if(c == 't') { #if (defined(POWER_OFF_VDDIO) || defined(POWER_OFF_HDMI_VCC) || defined(POWER_OFF_AVDD33) || defined(POWER_OFF_AVDD25)) init_I2C(); #endif copy_reboot_code(); enter_power_down(); //test_arc_core(); break; } else if(c == 'q') { serial_puts(" - quit command loop\n"); writel(0,P_AO_RTI_STATUS_REG0); break; } else { serial_puts(" - cmd no support (ARC)\n"); } //command executed writel(0,P_AO_RTI_STATUS_REG0); } while(1){ udelay(6000); cmd = readl(P_AO_RTI_STATUS_REG1); c = (char)cmd; if(c == 0) { udelay(6000); cmd = readl(P_AO_RTI_STATUS_REG1); c = (char)cmd; if((c == 0)||(c!='r')) { #ifdef _UART_DEBUG_COMMUNICATION_ serial_put_hex(cmd,32); f_serial_puts(" arm boot fail\n\n"); wait_uart_empty(); #endif #if 0 //power down cmd = readl(P_AO_GPIO_O_EN_N); cmd &= ~(1<<6); cmd &= ~(1<<22); writel(cmd,P_AO_GPIO_O_EN_N); #endif } } else if(c=='r') { writel(0,0xc8100030); #ifdef _UART_DEBUG_COMMUNICATION_ //f_serial_puts("arm boot succ\n"); //wait_uart_empty(); #endif } else { #ifdef _UART_DEBUG_COMMUNICATION_ serial_put_hex(cmd,32); f_serial_puts(" arm unkonw state\n"); wait_uart_empty(); #endif } //cmd='f'; //writel(cmd,P_AO_RTI_STATUS_REG1); asm(".long 0x003f236f"); //add sync instruction. //asm("SLEEP"); asm("FLAG 1");//halt mode } return 0; }
void enter_power_down() { int i; unsigned v1,v2,v; unsigned rtc_ctrl; unsigned power_key; //******************************************* //* power down flow //******************************************* f_serial_puts("\n"); wait_uart_empty(); // disable jtag setbits_le32(P_AO_RTI_PIN_MUX_REG, 1<<13); clrbits_le32(P_AO_RTI_PIN_MUX_REG, 1<<14); // turn off mali clock clrbits_le32(P_HHI_MALI_CLK_CNTL, 1 << 8); // disable all memory accesses. disable_mmc_req(); //save registers for clk and ddr store_restore_plls(1); //mmc enter sleep mmc_sleep(); // delay_ms(20); // save ddr power APB_Wr(MMC_PHY_CTRL, APB_Rd(MMC_PHY_CTRL)|(1<<0)|(1<<8)|(1<<13)); APB_Wr(PCTL_PHYCR_ADDR, APB_Rd(PCTL_PHYCR_ADDR)|(1<<6)); APB_Wr(PCTL_DLLCR9_ADDR, APB_Rd(PCTL_DLLCR9_ADDR)|(1<<31)); // delay_ms(20); // power down DDR writel(readl(P_HHI_DDR_PLL_CNTL)|(1<<15),P_HHI_DDR_PLL_CNTL); // enable retention enable_retention(); writel(0,P_AO_RTI_STATUS_REG1); // reset A9 // setbits_le32(P_A9_CFG2, 7<<16); clrbits_le32(P_HHI_SYS_CPU_CLK_CNTL, 1<<4); // disable APB_CLK clrbits_le32(P_HHI_SYS_CPU_CLK_CNTL, 1<<5); // disable AT_CLK setbits_le32(P_HHI_SYS_CPU_CLK_CNTL,1<<19); udelay(10); // enable iso ee for A9 writel(readl(P_AO_RTI_PWR_CNTL_REG0)&(~(1<<4)),P_AO_RTI_PWR_CNTL_REG0); udelay(1000); #ifdef POWER_OFF_HDMI_VCC reg7_off(); #endif #ifdef POWER_OFF_AVDD33 reg5_off(); #endif #ifdef POWER_OFF_EE //iso EE from AO //comment isolate EE. otherwise cannot detect power key. // writel(readl(P_AO_RTI_PWR_CNTL_REG0)&(~(1<<0)),P_AO_RTI_PWR_CNTL_REG0); writel(readl(P_AO_RTI_PWR_CNTL_REG0)&(~(1<<2)),P_AO_RTI_PWR_CNTL_REG0); writel(readl(P_AO_RTI_PWR_CNTL_REG0)&(~(1<<3)),P_AO_RTI_PWR_CNTL_REG0); //?? Gate off clk81 to EE domain writel(readl(P_AO_RTI_GEN_CNTL_REG0)&(~(1<<12)),P_AO_RTI_GEN_CNTL_REG0); //------------------------------- //turn off EE voltage //v = readl(0xC8100024); //v &= ~(1<<9); //v &= ~(1<<25); //writel(v,0xC8100024); #else // ee use 32k writel(readl(P_HHI_MPEG_CLK_CNTL)|(1<<9),P_HHI_MPEG_CLK_CNTL); #endif // change RTC filter for 32k rtc_ctrl = readl(0xC810074c); //writel(0x00800000,0xC810074c); writel(0,0xC810074c); // switch to 32k writel(readl(P_AO_RTI_PWR_CNTL_REG0)|(1<<8),P_AO_RTI_PWR_CNTL_REG0); udelay(100); #ifdef POWER_OFF_VDDIO vddio_off(); #endif #ifdef POWER_OFF_AVDD25 reg6_off(); #endif #ifdef POWER_OFF_VCC power_off_VCC(0); #endif udelay(100); #if (defined(POWER_DOWN_VCC12) || defined(POWER_DOWN_DDR)) switch_voltage(1); #endif #ifdef POWER_DOWN_DDR powerdown_ddr(); #endif #ifdef POWER_DOWN_VCC12 powerdown_vcc12(); #endif // gate off REMOTE, UART //writel(readl(P_AO_RTI_GEN_CNTL_REG0)&(~(0xF)),P_AO_RTI_GEN_CNTL_REG0); // wait key #if 1 //backup the remote config (on arm) backup_remote_register(); //set the ir_remote to 32k mode at ARC init_custom_trigger(); //set the detect gpio //setbits_le32(P_AO_GPIO_O_EN_N,(1<<3)); while(1) { //detect remote key power_key=readl(P_AO_IR_DEC_FRAME); if(power_key==0xf50a7748) break; //detect IO key /*power_key=readl(P_AO_GPIO_I); power_key=power_key&(1<<3); if(!power_key) break; */ #ifdef RTC_AUTO_WAKE_UP power_key = readl(0xc8100744); if((power_key&8) != 0) break; #endif } #elif 1 power_key = readl(0Xc8100744); while (((power_key&4) != 0)&&((power_key&8) == 0)) { power_key = readl(0Xc8100744); } #else for(i=0;i<64;i++) { udelay(1000); //udelay(1000); } #endif // gate on REMOTE, I2C s/m, UART //writel(readl(P_AO_RTI_GEN_CNTL_REG0)|0xF, P_AO_RTI_GEN_CNTL_REG0); udelay(10); #ifdef POWER_DOWN_DDR powerup_ddr(); #endif #ifdef POWER_DOWN_VCC12 powerup_vcc12(); #endif #if (defined(POWER_DOWN_VCC12) || defined(POWER_DOWN_DDR)) switch_voltage(0); #endif #ifdef POWER_OFF_VCC power_off_VCC(1); #endif #ifdef POWER_OFF_AVDD25 reg6_on(); #endif #ifdef POWER_OFF_VDDIO vddio_on(); #endif udelay(100); // switch to clk81 writel(readl(P_AO_RTI_PWR_CNTL_REG0)&(~(0x1<<8)),P_AO_RTI_PWR_CNTL_REG0); udelay(100); // restore RTC filter writel(rtc_ctrl,0xC810074c); // set AO interrupt mask writel(0xFFFF,P_AO_IRQ_STAT_CLR); #ifdef POWER_OFF_EE //turn on EE voltage //v = readl(0xC8100024); //v &= ~(1<<9); //v |= (1<<25); //writel(v,0xC8100024); //delay_ms(200); // un-iso AO domain from EE bit0=signals, bit1=reset, bit2=irq, bit3=test_mode writel(readl(P_AO_RTI_PWR_CNTL_REG0)|(0xD<<0),P_AO_RTI_PWR_CNTL_REG0); //un isolate the reset in the EE writel(readl(P_AO_RTI_PWR_CNTL_REG0)|(0x1<<5),P_AO_RTI_PWR_CNTL_REG0); writel(readl(P_AO_RTI_PWR_CNTL_REG0)|(0x1<<5)|(1<<3)|(1<<2)|(1<<1)|(1<<0), \ P_AO_RTI_PWR_CNTL_REG0); #else // ee go back to clk81 writel(readl(P_HHI_MPEG_CLK_CNTL)&(~(0x1<<9)),P_HHI_MPEG_CLK_CNTL); #endif #ifdef POWER_OFF_AVDD33 reg5_on(); #endif #ifdef POWER_OFF_HDMI_VCC reg7_on(); #endif store_restore_plls(0); init_ddr_pll(); udelay(1000); uart_reset(); reset_mmc(); // initialize mmc and put it to sleep init_pctl(); mmc_sleep(); // disable retention disable_retention(); // Next, we wake up mmc_wakeup(); // Next, we enable all requests enable_mmc_req(); // f_serial_puts("restart arm...\n"); //0. make sure a9 reset setbits_le32(P_A9_CFG2,1<<17); // release APB reset udelay(1000); setbits_le32(P_A9_CFG2,1<<16); // release AXI reset udelay(1000); setbits_le32(P_A9_CFG2,1<<18); // release A9DBG reset udelay(1000); setbits_le32(P_HHI_SYS_CPU_CLK_CNTL,1<<19); udelay(1000); //1. write flag if (power_key&8) writel(0xabcd1234,P_AO_RTI_STATUS_REG2); else writel(0x1234abcd,P_AO_RTI_STATUS_REG2); //2. remap AHB SRAM writel(3,P_AO_REMAP_REG0); writel(2,P_AHB_ARBDEC_REG); //3. turn off romboot clock writel(readl(P_HHI_GCLK_MPEG1)&0x7fffffff,P_HHI_GCLK_MPEG1); //4. Release ISO for A9 domain. setbits_le32(P_AO_RTI_PWR_CNTL_REG0,1<<4); udelay(1000); writel( (0 << 9) | // select xtal as clock source (0 << 0) , P_HHI_MALI_CLK_CNTL); delay_ms(1); setbits_le32(P_HHI_SYS_CPU_CLK_CNTL, (1<<14)|(1<<15)); // soft reset udelay(10); clrbits_le32(P_HHI_SYS_CPU_CLK_CNTL, (1<<14)|(1<<15)); // soft reset udelay(1000); //reset A9 writel(0xF,P_RESET4_REGISTER);// -- reset arm.ww writel(1<<14,P_RESET2_REGISTER);// -- reset arm.mali udelay(1000); clrbits_le32(P_A9_CFG2,1<<17); // release APB reset udelay(1000); clrbits_le32(P_A9_CFG2,1<<16); // release AXI reset udelay(1000); clrbits_le32(P_A9_CFG2,1<<18); // release A9DBG reset udelay(1000); setbits_le32(P_HHI_SYS_CPU_CLK_CNTL, 1<<4); // enable APB_CLK udelay(10); clrbits_le32(P_HHI_SYS_CPU_CLK_CNTL,1<<19); // release A9 reset udelay(1000); //reset the IR REMOTE resume_remote_register(); // delay_1s(); // delay_1s(); // delay_1s(); }
void init_pctl(void) { int nTempVal; int stat; MMC_Wr(MMC_PHY_CTRL,v_mmc_phy_ctrl); /* MMC_Wr(UPCTL_DLLCR9_ADDR, v_dllcr9); //2a8 MMC_Wr(UPCTL_IOCR_ADDR, v_iocr); //248 MMC_Wr(UPCTL_PHYCR_ADDR, 2);//???? */ //wait to DDR PLL lock. //while (!(MMC_Rd(MMC_CLK_CNTL) & (1<<29)) ) {} //dbg_out("d",1); //Enable DDR DLL clock input from PLL. // MMC_Wr(MMC_CLK_CNTL, 0xc0000080); // @@@ select the final mux from PLL output directly. // MMC_Wr(MMC_CLK_CNTL, 0xc00000c0); //enable the clock. //MMC_Wr(MMC_CLK_CNTL, v_mmc_clk_cntl); // release the DDR DLL reset pin. // MMC_Wr( MMC_SOFT_RST, 0xffff); //__udelay(10); //UPCTL memory timing registers MMC_Wr(UPCTL_TOGCNT1U_ADDR, v_t_1us_pck); //1us = nn cycles. MMC_Wr(UPCTL_TOGCNT100N_ADDR, v_t_100ns_pck);//100ns = nn cycles. MMC_Wr(UPCTL_TINIT_ADDR, v_t_init_us); //200us. // MMC_Wr(UPCTL_TRSTH_ADDR, 2); // 0 for ddr2; 500 for ddr3. 2 for simulation. MMC_Wr(UPCTL_TRSTH_ADDR, v_t_rsth_us); // 0 for ddr2; 2 for simulation; 500 for ddr3. //??? MMC_Wr(UPCTL_TRSTL_ADDR, v_t_rstl_us); //????? MMC_Wr(UPCTL_MCFG_ADDR,v_mcfg); MMC_Wr(UPCTL_DFIODTCFG_ADDR, v_dfiodrcfg_adr);//add for Eric fine-tune //configure DDR PHY PUBL registers. // 2:0 011: DDR3 mode. 100: LPDDR2 mode. // 3: 8 bank. MMC_Wr(PUB_DCR_ADDR, 0x3 | (1 << 3)); MMC_Wr(PUB_PGCR_ADDR, 0x01842e04); //PUB_PGCR_ADDR: c8001008 MMC_Wr( PUB_MR0_ADDR,v_msr0); MMC_Wr( PUB_MR1_ADDR,v_msr1); MMC_Wr( PUB_MR2_ADDR,v_msr2); MMC_Wr( PUB_MR3_ADDR,v_msr3); // MMC_Wr( PUB_MR3_ADDR,0); MMC_Wr(PUB_DTPR0_ADDR,v_pub_dtpr0); MMC_Wr(PUB_DTPR1_ADDR,v_pub_dtpr1); MMC_Wr(PUB_DTPR2_ADDR,v_pub_dtpr2); MMC_Wr(PUB_PTR0_ADDR,v_pub_ptr0); // MMC_Wr( PUB_PIR_ADDR, 0x17);//Add By Dai __udelay(50); //wait PHY DLL LOCK while(!(MMC_Rd( PUB_PGSR_ADDR) & 1)) {} dbg_out("d",2); // configure DDR3_rst pin. MMC_Wr( PUB_ACIOCR_ADDR, MMC_Rd( PUB_ACIOCR_ADDR) & 0xdfffffff ); MMC_Wr( PUB_DSGCR_ADDR, MMC_Rd(PUB_DSGCR_ADDR) & 0xffffffef); //MMC_Wr( PUB_ZQ0CR1_ADDR, 0x18); //??????? //MMC_Wr( PUB_ZQ0CR1_ADDR, 0x7b); //??????? #ifdef CONFIG_TURN_OFF_ODT if(v_zq0cr0 & (1<<28)) MMC_Wr( PUB_ZQ0CR0_ADDR, v_zq0cr0); else MMC_Wr( PUB_ZQ0CR1_ADDR, v_zq0cr1); if(v_cmdzq) MMC_Wr( MMC_CMDZQ_CTRL, v_cmdzq); #else MMC_Wr( PUB_ZQ0CR1_ADDR, v_zq0cr1); #endif //for simulation to reduce the init time. // MMC_Wr(PUB_PTR1_ADDR,v_pub_ptr1); // MMC_Wr(PUB_PTR2_ADDR,v_pub_ptr2); // MMC_Wr( PUB_PIR_ADDR, 0x9);//Add By Dai __udelay(20); //wait DDR3_ZQ_DONE: #ifndef CONFIG_TURN_OFF_ODT while( !(MMC_Rd( PUB_PGSR_ADDR) & (1<< 2))) {} #endif dbg_out("d",3); // wait DDR3_PHY_INIT_WAIT : #ifndef CONFIG_TURN_OFF_ODT while (!(MMC_Rd(PUB_PGSR_ADDR) & 1 )) {} #endif dbg_out("d",4); // Monitor DFI initialization status. #ifndef CONFIG_TURN_OFF_ODT while(!(MMC_Rd(UPCTL_DFISTSTAT0_ADDR) & 1)) {} #endif dbg_out("d",5); MMC_Wr(UPCTL_POWCTL_ADDR, 1); while(!(MMC_Rd( UPCTL_POWSTAT_ADDR & 1) )) {} dbg_out("d",6); // initial upctl ddr timing. MMC_Wr(UPCTL_TREFI_ADDR, v_t_refi_100ns); // 7800ns to one refresh command. // wr_reg UPCTL_TREFI_ADDR, 78 MMC_Wr(UPCTL_TMRD_ADDR, v_t_mrd); //wr_reg UPCTL_TMRD_ADDR, 4 MMC_Wr(UPCTL_TRFC_ADDR, v_t_rfc); //64: 400Mhz. 86: 533Mhz. // wr_reg UPCTL_TRFC_ADDR, 86 MMC_Wr(UPCTL_TRP_ADDR, v_t_rp); // 8 : 533Mhz. //wr_reg UPCTL_TRP_ADDR, 8 MMC_Wr(UPCTL_TAL_ADDR, v_t_al); //wr_reg UPCTL_TAL_ADDR, 0 // MMC_Wr(UPCTL_TCWL_ADDR, v_t_cl-1 + v_t_al); MMC_Wr(UPCTL_TCWL_ADDR, v_t_cwl); //wr_reg UPCTL_TCWL_ADDR, 6 MMC_Wr(UPCTL_TCL_ADDR, v_t_cl); //6: 400Mhz. 8 : 533Mhz. // wr_reg UPCTL_TCL_ADDR, 8 MMC_Wr(UPCTL_TRAS_ADDR, v_t_ras); //16: 400Mhz. 20: 533Mhz. // wr_reg UPCTL_TRAS_ADDR, 20 MMC_Wr(UPCTL_TRC_ADDR, v_t_rc); //24 400Mhz. 28 : 533Mhz. //wr_reg UPCTL_TRC_ADDR, 28 MMC_Wr(UPCTL_TRCD_ADDR, v_t_rcd); //6: 400Mhz. 8: 533Mhz. // wr_reg UPCTL_TRCD_ADDR, 8 MMC_Wr(UPCTL_TRRD_ADDR, v_t_rrd); //5: 400Mhz. 6: 533Mhz. //wr_reg UPCTL_TRRD_ADDR, 6 MMC_Wr(UPCTL_TRTP_ADDR, v_t_rtp); // wr_reg UPCTL_TRTP_ADDR, 4 MMC_Wr(UPCTL_TWR_ADDR, v_t_wr); // wr_reg UPCTL_TWR_ADDR, 8 MMC_Wr(UPCTL_TWTR_ADDR, v_t_wtr); //wr_reg UPCTL_TWTR_ADDR, 4 MMC_Wr(UPCTL_TEXSR_ADDR, v_t_exsr); //wr_reg UPCTL_TEXSR_ADDR, 200 MMC_Wr(UPCTL_TXP_ADDR, v_t_xp); //wr_reg UPCTL_TXP_ADDR, 4 MMC_Wr(UPCTL_TDQS_ADDR, v_t_dqs); // wr_reg UPCTL_TDQS_ADDR, 2 MMC_Wr(UPCTL_TRTW_ADDR, v_t_trtw); //wr_reg UPCTL_TRTW_ADDR, 2 //MMC_Wr(UPCTL_TCKSRE_ADDR, 5); MMC_Wr(UPCTL_TCKSRE_ADDR, v_t_cksre); //wr_reg UPCTL_TCKSRE_ADDR, 5 //MMC_Wr(UPCTL_TCKSRX_ADDR, 5); MMC_Wr(UPCTL_TCKSRX_ADDR, v_t_cksrx); //wr_reg UPCTL_TCKSRX_ADDR, 5 MMC_Wr(UPCTL_TMOD_ADDR, v_t_mod); //wr_reg UPCTL_TMOD_ADDR, 8 //MMC_Wr(UPCTL_TCKE_ADDR, 4); MMC_Wr(UPCTL_TCKE_ADDR, v_t_cke); //wr_reg UPCTL_TCKE_ADDR, 4 MMC_Wr(UPCTL_TZQCS_ADDR, 64); //wr_reg UPCTL_TZQCS_ADDR , 64 // MMC_Wr(UPCTL_TZQCL_ADDR, v_t_zqcl); MMC_Wr(UPCTL_TZQCL_ADDR, 512); //wr_reg UPCTL_TZQCL_ADDR , 512 MMC_Wr(UPCTL_TXPDLL_ADDR, 10); // wr_reg UPCTL_TXPDLL_ADDR, 10 MMC_Wr(UPCTL_TZQCSI_ADDR, 1000); // wr_reg UPCTL_TZQCSI_ADDR, 1000 MMC_Wr(UPCTL_SCFG_ADDR, 0xf00); // wr_reg UPCTL_SCFG_ADDR, 0xf00 // MMC_Wr(UPCTL_LPDDR2ZQCFG_ADDR,v_odtcfg); //???? // MMC_Wr(UPCTL_ZQCR_ADDR,v_zqcr); //????? MMC_Wr( UPCTL_SCTL_ADDR, 1); while (!( MMC_Rd(UPCTL_STAT_ADDR) & 1)) { MMC_Wr(UPCTL_SCTL_ADDR, 1); } dbg_out("d",7); //config the DFI interface. MMC_Wr( UPCTL_PPCFG_ADDR, (0xf0 << 1) ); MMC_Wr( UPCTL_DFITCTRLDELAY_ADDR, 2 ); MMC_Wr( UPCTL_DFITPHYWRDATA_ADDR, 0x1 ); MMC_Wr( UPCTL_DFITPHYWRLAT_ADDR, v_t_cwl -1 ); //CWL -1 MMC_Wr( UPCTL_DFITRDDATAEN_ADDR, v_t_cl - 2 ); //CL -2 MMC_Wr( UPCTL_DFITPHYRDLAT_ADDR, 15 ); MMC_Wr( UPCTL_DFITDRAMCLKDIS_ADDR, 2 ); MMC_Wr( UPCTL_DFITDRAMCLKEN_ADDR, 2 ); MMC_Wr( UPCTL_DFISTCFG0_ADDR, 0x4 ); MMC_Wr( UPCTL_DFITCTRLUPDMIN_ADDR, 0x4000 ); MMC_Wr( UPCTL_DFILPCFG0_ADDR, ( 1 | (7 << 4) | (1 << 8) | (10 << 12) | (12 <<16) | (1 <<24) | ( 7 << 28))); MMC_Wr( UPCTL_CMDTSTATEN_ADDR, 1); while (!(MMC_Rd(UPCTL_CMDTSTAT_ADDR) & 1 )) {} dbg_out("d",8); //MMC_Wr( PUB_DTAR_ADDR, (0x0 | (0 <<12) | (7 << 28))); //training address is 0x90001800 not safe //MMC_Wr( PUB_DTAR_ADDR, (0xFc0 | (0xFFFF <<12) | (7 << 28))); //let training address is 0x9fffff00; MMC_Wr(PUB_DTAR_ADDR,v_dtar); serial_put_hex(MMC_Rd(PUB_DTAR_ADDR),32); f_serial_puts(" PUB_DTAR_ADDR\n"); //start trainning. // DDR PHY initialization #ifdef CONFIG_TURN_OFF_ODT if(v_zq0cr0 & (1<<28)) MMC_Wr( PUB_PIR_ADDR, 0x1e1); else MMC_Wr( PUB_PIR_ADDR, 0x1e9); //MMC_Wr( PUB_PIR_ADDR, 0x69); //no training #else MMC_Wr( PUB_PIR_ADDR, 0x1e9); #endif //DDR3_SDRAM_INIT_WAIT : while( !(MMC_Rd(PUB_PGSR_ADDR & 1))) {} dbg_out("d",9); if(MMC_Rd(PUB_PGSR_ADDR) & (3<<5)){ f_serial_puts("PUB_PGSR="); serial_put_hex(MMC_Rd(PUB_PGSR_ADDR),8); f_serial_puts("\n"); #ifdef CONFIG_TURN_OFF_ODT MMC_Wr( PUB_PIR_ADDR, 0x1e1 | (1<<28)); #else MMC_Wr( PUB_PIR_ADDR, 0x1e9 | (1<<28)); #endif while( !(MMC_Rd(PUB_PGSR_ADDR & 1))) {} dbg_out("d",0x91); f_serial_puts("PUB_PGSR="); serial_put_hex(MMC_Rd(PUB_PGSR_ADDR),8); f_serial_puts("\n"); } //check ZQ calibraration status. stat = MMC_Rd(PUB_ZQ0SR0_ADDR); serial_put_hex(stat,32); f_serial_puts(" PUB_ZQ0SR0\n"); stat = MMC_Rd(PUB_ZQ0SR1_ADDR); serial_put_hex(stat,32); f_serial_puts(" PUB_ZQ0SR1\n"); //check data training result. stat = MMC_Rd(PUB_DX0GSR0_ADDR); serial_put_hex(stat,32); f_serial_puts(" PUB_DX0GSR0\n"); wait_uart_empty(); stat = MMC_Rd(PUB_DX1GSR0_ADDR); serial_put_hex(stat,32); f_serial_puts(" PUB_DX1GSR0\n"); wait_uart_empty(); stat = MMC_Rd(PUB_DX2GSR0_ADDR); serial_put_hex(stat,32); f_serial_puts(" PUB_DX2GSR0\n"); wait_uart_empty(); stat = MMC_Rd(PUB_DX3GSR0_ADDR); serial_put_hex(stat,32); f_serial_puts(" PUB_DX3GSR0\n"); wait_uart_empty(); MMC_Wr(UPCTL_SCTL_ADDR, 2); // init: 0, cfg: 1, go: 2, sleep: 3, wakeup: 4 while ((MMC_Rd(UPCTL_STAT_ADDR) & 0x7 ) != 3 ) {} dbg_out("d",10); __udelay(200); // MMC_Wr(MMC_DDR_CTRL,v_mmc_ddr_ctrl); // MMC_Wr(MMC_PHY_CTRL,v_mmc_phy_ctrl); // MMC_Wr(UPCTL_PHYCR_ADDR, 2); // MMC_Wr(MMC_REQ_CTRL, 0xff ); //enable request in kreboot.s // udelay(50); // MMC_Wr(UPCTL_IOCR_ADDR, v_iocr); //248 //traning result /* MMC_Wr(UPCTL_RDGR0_ADDR,v_rdgr0); MMC_Wr(UPCTL_RSLR0_ADDR,v_rslr0); MMC_Wr(PUB_DX0GSR0_ADDR,v_dx0gsr0); MMC_Wr(PUB_DX0GSR1_ADDR,v_dx0gsr1); MMC_Wr(PUB_DX0DQSTR_ADDR,v_dx0dqstr); MMC_Wr(PUB_DX1GSR0_ADDR,v_dx1gsr0); MMC_Wr(PUB_DX1GSR1_ADDR,v_dx1gsr1); MMC_Wr(PUB_DX1DQSTR_ADDR,v_dx1dqstr); MMC_Wr(PUB_DX2GSR0_ADDR,v_dx2gsr0); MMC_Wr(PUB_DX2GSR1_ADDR,v_dx2gsr1); MMC_Wr(PUB_DX2DQSTR_ADDR,v_dx2dqstr); MMC_Wr(PUB_DX3GSR0_ADDR,v_dx3gsr0); MMC_Wr(PUB_DX3GSR1_ADDR,v_dx3gsr1); MMC_Wr(PUB_DX3DQSTR_ADDR,v_dx3dqstr); MMC_Wr(PUB_DX4GSR0_ADDR,v_dx4gsr0); MMC_Wr(PUB_DX4GSR1_ADDR,v_dx4gsr1); MMC_Wr(PUB_DX4DQSTR_ADDR,v_dx4dqstr); MMC_Wr(PUB_DX5GSR0_ADDR,v_dx5gsr0); MMC_Wr(PUB_DX5GSR1_ADDR,v_dx5gsr1); MMC_Wr(PUB_DX5DQSTR_ADDR,v_dx5dqstr); MMC_Wr(PUB_DX6GSR0_ADDR,v_dx6gsr0); MMC_Wr(PUB_DX6GSR1_ADDR,v_dx6gsr1); MMC_Wr(PUB_DX6DQSTR_ADDR,v_dx6dqstr); MMC_Wr(PUB_DX7GSR0_ADDR,v_dx7gsr0); MMC_Wr(PUB_DX7GSR1_ADDR,v_dx7gsr1); MMC_Wr(PUB_DX7DQSTR_ADDR,v_dx7dqstr); MMC_Wr(PUB_DX8GSR0_ADDR,v_dx8gsr0); MMC_Wr(PUB_DX8GSR1_ADDR,v_dx8gsr1); MMC_Wr(PUB_DX8DQSTR_ADDR,v_dx8dqstr); */ // MMC_Wr(MMC_REQ_CTRL, 0xff ); Already enable request in kreboot.s return 0; }
int main(void) { unsigned cmd; char c; p_arc_pwr_op = &arc_pwr_op; timer_init(); arc_pwr_register((struct arc_pwr_op *)p_arc_pwr_op);//init arc_pwr_op arc_param->serial_disable=0; serial_put_hex(readl(P_AO_RTI_STATUS_REG1),32); writel(0,P_AO_RTI_STATUS_REG1); f_serial_puts("sleep .......\n"); arc_param->serial_disable=0; while(1){ cmd = readl(P_AO_RTI_STATUS_REG0); if(cmd == 0) { delay_ms(10); continue; } c = (char)cmd; if(c == 't') { init_I2C(); // copy_reboot_code(); #ifdef CONFIG_MESON_TRUSTZONE copy_reboot_code_temp(temp_arm_base, sizeof(temp_arm_base)); #endif enter_power_down(); //test_arc_core(); break; } else if(c == 'q') { f_serial_puts(" - quit command loop\n"); writel(0,P_AO_RTI_STATUS_REG0); break; } else { f_serial_puts(" - cmd no support (ARC)\n"); } //command executed writel(0,P_AO_RTI_STATUS_REG0); } // asm("SLEEP"); while(1){ // udelay__(600); cmd = readl(P_AO_RTI_STATUS_REG1); c = (char)cmd; // f_serial_puts("REG2="); // serial_put_hex(readl(P_AO_RTI_STATUS_REG2),32); if(c == 0) { udelay__(6000); cmd = readl(P_AO_RTI_STATUS_REG1); c = (char)cmd; if((c == 0)||(c!='r')) { #ifdef _UART_DEBUG_COMMUNICATION_ serial_put_hex(cmd,32); f_serial_puts(" arm boot fail\n\n"); wait_uart_empty(); #endif #if 0 //power down cmd = readl(P_AO_GPIO_O_EN_N); cmd &= ~(1<<6); cmd &= ~(1<<22); writel(cmd,P_AO_GPIO_O_EN_N); #endif } } else if ( cmd == 1 ) { serial_put_hex(cmd,32); f_serial_puts(" ARM has started running\n"); wait_uart_empty(); } else if ( cmd == 2 ) { serial_put_hex(cmd,32); f_serial_puts(" Reenable SEC\n"); wait_uart_empty(); } else if(c=='r') { f_serial_puts("arm boot succ\n"); wait_uart_empty(); asm(".long 0x003f236f"); //add sync instruction. asm("flag 1"); asm("nop"); asm("nop"); asm("nop"); } else { #ifdef _UART_DEBUG_COMMUNICATION_ serial_put_hex(cmd,32); f_serial_puts(" arm unkonw state\n"); wait_uart_empty(); #endif } //cmd='f'; //writel(cmd,P_AO_RTI_STATUS_REG1); } return 0; }
void store_restore_plls(int flag) { int i; if(!flag) { pll_settings[0]=readl(P_HHI_SYS_PLL_CNTL); pll_settings[1]=readl(P_HHI_SYS_PLL_CNTL2); pll_settings[2]=readl(P_HHI_SYS_PLL_CNTL3); pll_settings[3]=readl(P_HHI_SYS_PLL_CNTL4); pll_settings[4]=readl(P_HHI_SYS_PLL_CNTL5); for(i=0;i<10;i++)//store mpll mpll_settings[i]=readl(P_HHI_MPLL_CNTL + 4*i); //disable sys pll & mpll writel(readl(P_HHI_SYS_PLL_CNTL) & (~(1<<30)),P_HHI_SYS_PLL_CNTL); writel(readl(P_HHI_MPLL_CNTL) & (~(1<<30)),P_HHI_MPLL_CNTL); return; } #define M8_PLL_ENTER_RESET(pll) \ writel((1<<29), pll); #define M8_PLL_RELEASE_RESET(pll) \ writel(readl(pll)&(~(1<<29)),pll); //M8 PLL enable: bit 30 ; 1-> enable;0-> disable #define M8_PLL_SETUP(set, pll) \ writel((set) |(1<<29) |(1<<30), pll);\ udelay__(1000); //wait 1ms for PLL lock //wait for pll lock //must wait first (100us+) then polling lock bit to check #define M8_PLL_WAIT_FOR_LOCK(pll) \ do{\ udelay__(1000);\ f_serial_puts(" Lock mpll\n"); \ wait_uart_empty(); \ }while((readl(pll)&0x80000000)==0); writel(readl(P_AM_ANALOG_TOP_REG1)|1, P_AM_ANALOG_TOP_REG1); //bandgap enable //SYS,MPLL writel(readl(P_HHI_MPLL_CNTL6)|(1<<26), P_HHI_MPLL_CNTL6); //VID,HDMI writel(readl(P_HHI_VID_PLL_CNTL5)|(1<<16), P_HHI_VID_PLL_CNTL5); //DDR // writel(readl(0xc8000410)|(1<<12),0xc8000410); //??? // writel(readl(P_HHI_MPEG_CLK_CNTL)&(~(1<<8)), P_HHI_MPEG_CLK_CNTL); // udelay__(10); //PLL setup: bandgap enable -> 1ms delay -> PLL reset + PLL set -> // PLL enable -> 1ms delay -> PLL release from reset //SYS PLL init do{ //BANDGAP reset for SYS_PLL,MPLL lock fail writel_reg_bits(P_HHI_MPLL_CNTL6,0,26,1); udelay__(10); writel_reg_bits(P_HHI_MPLL_CNTL6,1,26,1); udelay__(1000); //1ms for bandgap bootup M8_PLL_ENTER_RESET(P_HHI_SYS_PLL_CNTL); writel(pll_settings[1],P_HHI_SYS_PLL_CNTL2); writel(pll_settings[2],P_HHI_SYS_PLL_CNTL3); writel(pll_settings[3],P_HHI_SYS_PLL_CNTL4); writel(pll_settings[4],P_HHI_SYS_PLL_CNTL5); M8_PLL_SETUP(pll_settings[0], P_HHI_SYS_PLL_CNTL); M8_PLL_RELEASE_RESET(P_HHI_SYS_PLL_CNTL); if(arc_param->serial_disable) udelay__(1000); else { f_serial_puts(" Lock sys pll\n"); wait_uart_empty(); } }while((readl(P_HHI_SYS_PLL_CNTL)&(1<<31))==0); //MPLL init //FIXED PLL/Multi-phase PLL, fixed to 2.55GHz M8_PLL_ENTER_RESET(P_HHI_MPLL_CNTL); //set reset bit to 1 for(i=1;i<10;i++) writel(mpll_settings[i],P_HHI_MPLL_CNTL+4*i); M8_PLL_SETUP(mpll_settings[0], P_HHI_MPLL_CNTL); //2.55G, FIXED M8_PLL_RELEASE_RESET(P_HHI_MPLL_CNTL); //set reset bit to 0 // M8_PLL_WAIT_FOR_LOCK(P_HHI_MPLL_CNTL); //need bandgap reset? do{ if(arc_param->serial_disable) udelay__(1000); else { udelay__(500); f_serial_puts(" Lock mpll~\n"); wait_uart_empty(); } //M8_PLL_LOCK_CHECK(n_pll_try_times,5); if((readl(P_HHI_MPLL_CNTL)&(1<<31))!=0) break; writel(readl(P_HHI_MPLL_CNTL) | (1<<29), P_HHI_MPLL_CNTL); udelay__(500); M8_PLL_RELEASE_RESET(P_HHI_MPLL_CNTL); udelay__(500); }while((readl(P_HHI_MPLL_CNTL)&(1<<31))==0); }
void test_arc_core() { int i; int j,k; unsigned int power_key=0; for(i=0;i<1000;i++) { asm("mov r0,r0"); asm("mov r0,r0"); //udelay(1000); //udelay(1000); } f_serial_puts("\n"); wait_uart_empty(); writel(0,P_AO_RTI_STATUS_REG1); // reset A9 clock //setbits_le32(P_HHI_SYS_CPU_CLK_CNTL,1<<19); // enable iso ee for A9 //writel(readl(P_AO_RTI_PWR_CNTL_REG0)&(~(1<<4)),P_AO_RTI_PWR_CNTL_REG0); // wait key power_key = readl(0Xc8100744); f_serial_puts("get power_key\n"); #if 0 while (((power_key&4) != 0)&&((power_key&8) == 0)) { power_key = readl(0Xc8100744); } #else for(i=0;i<1000;i++) { for(j=0;j<1000;j++) { for(k=0;k<100;k++) { asm("mov r0,r0"); } } //udelay(1000); //udelay(1000); } #endif f_serial_puts("delay 2s\n"); //0. make sure a9 reset // setbits_le32(P_HHI_SYS_CPU_CLK_CNTL,1<<19); #if 0 //1. write flag if (power_key&8) writel(0xabcd1234,P_AO_RTI_STATUS_REG2); else writel(0x1234abcd,P_AO_RTI_STATUS_REG2); #endif //2. remap AHB SRAM writel(3,P_AO_REMAP_REG0); writel(2,P_AHB_ARBDEC_REG); f_serial_puts("remap arm arc\n"); //3. turn off romboot clock writel(readl(P_HHI_GCLK_MPEG1)&0x7fffffff,P_HHI_GCLK_MPEG1); f_serial_puts("off romboot clock\n"); //4. Release ISO for A9 domain. //setbits_le32(P_AO_RTI_PWR_CNTL_REG0,1<<4); //reset A9 writel(0xF,P_RESET4_REGISTER);// -- reset arm.ww // writel(1<<14,P_RESET2_REGISTER);// -- reset arm.mali delay_ms(1); // clrbits_le32(P_HHI_SYS_CPU_CLK_CNTL,1<<19); // release A9 reset // f_serial_puts("arm reboot\n"); // wait_uart_empty(); f_serial_puts("arm reboot\n"); }