static _mali_osk_errcode_t enable_mali_clocks(struct device *dev)
{
int err;
err = clk_enable(mali_clock);
MALI_DEBUG_PRINT(3,("enable_mali_clocks mali_clock %p error %d \n", mali_clock, err));
/* set clock rate */
#ifdef CONFIG_MALI_DVFS
if (mali_dvfs_control != 0 || mali_gpu_clk >= mali_runtime_resume.clk) {
mali_clk_set_rate(mali_gpu_clk, GPU_MHZ);
} else {
#ifdef CONFIG_REGULATOR
mali_regulator_set_voltage(mali_runtime_resume.vol, mali_runtime_resume.vol);
exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_runtime_resume.clk * GPU_ASV_VOLT));
#endif
mali_clk_set_rate(mali_runtime_resume.clk, GPU_MHZ);
set_mali_dvfs_current_step(mali_runtime_resume.step);
}
#else
mali_clk_set_rate((unsigned int)mali_gpu_clk, GPU_MHZ);
maliDvfsStatus.currentStep = MALI_DVFS_DEFAULT_STEP;
#endif
MALI_SUCCESS;
}
static int exynos5_init_int_table(struct device *dev,
struct devfreq_data_int *data)
{
unsigned int i;
unsigned int ret;
unsigned int freq;
unsigned int volt;
exynos5_devfreq_int_profile.max_state = data->max_state;
data->int_asv_abb_table = kzalloc(sizeof(int) * data->max_state, GFP_KERNEL);
for (i = 0; i < data->max_state; ++i) {
freq = devfreq_int_opp_list[i].freq;
volt = get_match_volt(ID_INT, freq);
if (!volt)
volt = devfreq_int_opp_list[i].volt;
exynos5_devfreq_int_profile.freq_table[i] = freq;
devfreq_int_opp_list[i].volt = volt;
ret = opp_add(dev, freq, volt);
if (ret) {
pr_err("DEVFREQ(INT) : Failed to add opp entries %uKhz, %uV\n", freq, volt);
return ret;
} else {
pr_info("DEVFREQ(INT) : %uKhz, %uV\n", freq, volt);
}
data->int_asv_abb_table[i] = get_match_abb(ID_INT, freq);
pr_info("DEVFREQ(INT) : %uKhz, ABB %u\n", freq, data->int_asv_abb_table[i]);
}
return 0;
}
static void __init set_volt_table_CA53(void)
{
unsigned int i;
unsigned int asv_volt = 0;
for (i = 0; i < CPUFREQ_LEVEL_END_CA53; i++) {
asv_volt = get_match_volt(ID_CL0, exynos7420_freq_table_CA53[i].frequency);
if (!asv_volt)
exynos7420_volt_table_CA53[i] = asv_voltage_7420_CA53[i];
else
exynos7420_volt_table_CA53[i] = asv_volt;
pr_info("CPUFREQ of CA53 L%d : %d uV\n", i,
exynos7420_volt_table_CA53[i]);
exynos7420_abb_table_CA53[i] =
get_match_abb(ID_CL0, exynos7420_freq_table_CA53[i].frequency);
pr_info("CPUFREQ of CA53 L%d : ABB %d\n", i,
exynos7420_abb_table_CA53[i]);
}
switch (exynos_get_table_ver()) {
case 0 :
case 1 :
case 4 :
max_support_idx_CA53 = L6; break; /* 1.4GHz */
case 5 :
max_support_idx_CA53 = L8; break; /* 1.2GHz */
default :
#ifdef CONFIG_AP_FIVE
max_support_idx_CA53 = L5; /* 1.5GHz */
#else
#ifdef CONFIG_AP_SIX
max_support_idx_CA53 = L4; /* 1.6GHz */
#else
#ifdef CONFIG_AP_SEVEN
max_support_idx_CA53 = L3; /* 1.7GHz */
#endif
#endif
#endif
}
#ifdef CONFIG_AP_MIN_FOUR
min_support_idx_CA53 = L16; /* 400MHz */
#else
#ifdef CONFIG_AP_MIN_TWO
min_support_idx_CA53 = L18; /* 200MHz */
#endif
#endif
pr_info("CPUFREQ of CA53 max_freq : L%d %u khz\n", max_support_idx_CA53,
exynos7420_freq_table_CA53[max_support_idx_CA53].frequency);
pr_info("CPUFREQ of CA53 min_freq : L%d %u khz\n", min_support_idx_CA53,
exynos7420_freq_table_CA53[min_support_idx_CA53].frequency);
}
static int gpu_dvfs_update_asv_table(struct exynos_context *platform)
{
int i, voltage, dvfs_table_size;
gpu_dvfs_info *dvfs_table;
#ifdef CONFIG_PWRCAL
struct dvfs_rate_volt g3d_rate_volt[48];
int cal_table_size;
int j;
dvfs_table = platform->table;
dvfs_table_size = platform->table_size;
cal_table_size = cal_dfs_get_rate_asv_table(dvfs_g3d, g3d_rate_volt);
if (!cal_table_size)
GPU_LOG(DVFS_WARNING, DUMMY, 0u, 0u, "Failed get G3D ASV table\n");
for (i = 0; i < dvfs_table_size; i++) {
for (j = 0; j < cal_table_size; j++) {
if (dvfs_table[i].clock * 1000 == g3d_rate_volt[j].rate) {
voltage = g3d_rate_volt[j].volt;
if (voltage > 0) {
dvfs_table[i].voltage = g3d_rate_volt[j].volt;
GPU_LOG(DVFS_WARNING, DUMMY, 0u, 0u, "G3D %dKhz ASV is %duV\n", dvfs_table[i].clock*1000, dvfs_table[i].voltage);
}
}
}
}
#else
DVFS_ASSERT(platform);
dvfs_table = platform->table;
dvfs_table_size = platform->table_size;
for (i = 0; i < dvfs_table_size; i++) {
if (platform->dynamic_abb_status) {
dvfs_table[i].asv_abb = get_match_abb(ID_G3D, dvfs_table[i].clock*1000);
GPU_LOG(DVFS_WARNING, DUMMY, 0u, 0u, "DEVFREQ: %uKhz, ABB %u\n", dvfs_table[i].clock*1000, dvfs_table[i].asv_abb);
}
voltage = get_match_volt(ID_G3D, dvfs_table[i].clock*1000);
if (voltage > 0)
dvfs_table[i].voltage = voltage;
GPU_LOG(DVFS_WARNING, DUMMY, 0u, 0u, "G3D %dKhz ASV is %duV\n", dvfs_table[i].clock*1000, dvfs_table[i].voltage);
}
#endif
return 0;
}
static void __init set_volt_table_CA57(void)
{
unsigned int i;
unsigned int asv_volt = 0;
for (i = 0; i < CPUFREQ_LEVEL_END_CA57; i++) {
asv_volt = get_match_volt(ID_CL1, exynos7420_freq_table_CA57[i].frequency);
if (!asv_volt)
exynos7420_volt_table_CA57[i] = asv_voltage_7420_CA57[i];
else
exynos7420_volt_table_CA57[i] = asv_volt;
pr_info("CPUFREQ of CA57 L%d : %d uV\n", i,
exynos7420_volt_table_CA57[i]);
exynos7420_abb_table_CA57[i] =
get_match_abb(ID_CL1, exynos7420_freq_table_CA57[i].frequency);
pr_info("CPUFREQ of CA57 L%d : ABB %d\n", i,
exynos7420_abb_table_CA57[i]);
}
#if defined(CONFIG_CPU_THERMAL) && defined(CONFIG_EXYNOS5_DYNAMIC_CPU_HOTPLUG)
switch (exynos_get_table_ver()) {
case 0 :
case 1 :
case 4 :
max_support_idx_CA57 = L7; break; /* 1.8GHz */
case 5 :
max_support_idx_CA57 = L10; break; /* 1.5GHz */
default :
max_support_idx_CA57 = L4; /* 2.1GHz */
}
#else
max_support_idx_CA57 = L13; /* 1.2 GHz */
#endif
#ifdef CONFIG_S6_LOW_IDLE
min_support_idx_CA57 = L21; /* 400 MHz */
#else
min_support_idx_CA57 = L17; /* 800 MHz */
#endif
pr_info("CPUFREQ of CA57 max_freq : L%d %u khz\n", max_support_idx_CA57,
exynos7420_freq_table_CA57[max_support_idx_CA57].frequency);
pr_info("CPUFREQ of CA57 min_freq : L%d %u khz\n", min_support_idx_CA57,
exynos7420_freq_table_CA57[min_support_idx_CA57].frequency);
}
static void __init set_volt_table_CA53(void)
{
unsigned int i;
unsigned int asv_volt = 0;
for (i = 0; i < CPUFREQ_LEVEL_END_CA53; i++) {
asv_volt = get_match_volt(ID_CL0, exynos7420_freq_table_CA53[i].frequency);
if (!asv_volt)
exynos7420_volt_table_CA53[i] = asv_voltage_7420_CA53[i];
else
exynos7420_volt_table_CA53[i] = asv_volt;
pr_info("CPUFREQ of CA53 L%d : %d uV\n", i,
exynos7420_volt_table_CA53[i]);
exynos7420_abb_table_CA53[i] =
get_match_abb(ID_CL0, exynos7420_freq_table_CA53[i].frequency);
pr_info("CPUFREQ of CA53 L%d : ABB %d\n", i,
exynos7420_abb_table_CA53[i]);
}
switch (exynos_get_table_ver()) {
case 0 :
case 1 :
case 4 :
max_support_idx_CA53 = L6; break; /* 1.4GHz */
case 5 :
max_support_idx_CA53 = L8; break; /* 1.2GHz */
case 12 :
max_support_idx_CA53 = L7; break; /* 1.3GHz */
default :
max_support_idx_CA53 = EXYNOS7420_CPU_MAX_FREQ_LITTLE;
}
min_support_idx_CA53 = EXYNOS7420_CPU_MIN_FREQ_LITTLE;
pr_info("CPUFREQ of CA53 max_freq : L%d %u khz\n", max_support_idx_CA53,
exynos7420_freq_table_CA53[max_support_idx_CA53].frequency);
pr_info("CPUFREQ of CA53 min_freq : L%d %u khz\n", min_support_idx_CA53,
exynos7420_freq_table_CA53[min_support_idx_CA53].frequency);
}
static int gpu_dvfs_update_asv_table(struct exynos_context *platform)
{
int i, voltage, dvfs_table_size;
gpu_dvfs_info *dvfs_table;
DVFS_ASSERT(platform);
dvfs_table = platform->table;
dvfs_table_size = platform->table_size;
for (i = 0; i < dvfs_table_size; i++) {
if (platform->dynamic_abb_status) {
dvfs_table[i].asv_abb = get_match_abb(ID_G3D, dvfs_table[i].clock*1000);
GPU_LOG(DVFS_WARNING, DUMMY, 0u, 0u, "DEVFREQ: %uKhz, ABB %u\n", dvfs_table[i].clock*1000, dvfs_table[i].asv_abb);
}
voltage = get_match_volt(ID_G3D, dvfs_table[i].clock*1000);
if (voltage > 0)
dvfs_table[i].voltage = voltage;
GPU_LOG(DVFS_WARNING, DUMMY, 0u, 0u, "G3D %dKhz ASV is %duV\n", dvfs_table[i].clock*1000, dvfs_table[i].voltage);
}
return 0;
}
static int gpu_dvfs_update_asv_table(struct exynos_context *platform, int governor_type)
{
int i, voltage;
#if SOC_NAME == 5260
unsigned int asv_abb = 0;
#endif /* SOC_NAME */
for (i = 0; i < platform->table_size; i++) {
#if SOC_NAME == 5260
asv_abb = get_match_abb(ID_G3D, platform->table[i].clock*1000);
if (!asv_abb) {
platform->devfreq_g3d_asv_abb[i] = ABB_BYPASS;
} else {
platform->devfreq_g3d_asv_abb[i] = asv_abb;
}
GPU_LOG(DVFS_INFO, "DEVFREQ(G3D) : %uKhz, ABB %u\n", platform->table[i].clock*1000, platform->devfreq_g3d_asv_abb[i]);
#endif /* SOC_NAME */
voltage = get_match_volt(ID_G3D, platform->table[i].clock*1000);
if (voltage > 0)
platform->table[i].voltage = voltage;
GPU_LOG(DVFS_INFO, "G3D %dKhz ASV is %duV\n", platform->table[i].clock*1000, platform->table[i].voltage);
}
return 0;
}
static mali_bool init_mali_clock(void)
{
mali_bool ret = MALI_TRUE;
nPowermode = MALI_POWER_MODE_DEEP_SLEEP;
if (mali_clock != 0)
return ret; /* already initialized */
mali_dvfs_lock = _mali_osk_lock_init(_MALI_OSK_LOCKFLAG_NONINTERRUPTABLE
| _MALI_OSK_LOCKFLAG_ONELOCK, 0, 0);
if (mali_dvfs_lock == NULL)
return _MALI_OSK_ERR_FAULT;
if (!mali_clk_get())
{
MALI_PRINT(("Error: Failed to get Mali clock\n"));
goto err_clk;
}
clk_set_parent(vpll_src_clock, ext_xtal_clock);
clk_set_parent(sclk_vpll_clock, fout_vpll_clock);
clk_set_parent(mali_parent_clock, sclk_vpll_clock);
clk_set_parent(mali_clock, mali_parent_clock);
if (!atomic_read(&clk_active)) {
if (clk_enable(mali_clock) < 0) {
MALI_PRINT(("Error: Failed to enable clock\n"));
goto err_clk;
}
atomic_set(&clk_active, 1);
}
mali_clk_set_rate((unsigned int)mali_gpu_clk, GPU_MHZ);
MALI_PRINT(("init_mali_clock mali_clock %x\n", mali_clock));
#ifdef CONFIG_REGULATOR
g3d_regulator = regulator_get(NULL, "vdd_g3d");
if (IS_ERR(g3d_regulator))
{
MALI_PRINT( ("MALI Error : failed to get vdd_g3d\n"));
ret = MALI_FALSE;
goto err_regulator;
}
mali_gpu_vol = get_match_volt(ID_G3D, mali_gpu_clk * GPU_ASV_VOLT);
mali_runtime_resume.vol = get_match_volt(ID_G3D, mali_runtime_resume.clk * GPU_ASV_VOLT);
regulator_enable(g3d_regulator);
mali_regulator_set_voltage(mali_gpu_vol, mali_gpu_vol);
exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_runtime_resume.clk * GPU_ASV_VOLT));
#endif
#if defined(CONFIG_MALI400_PROFILING)
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE|
MALI_PROFILING_EVENT_CHANNEL_GPU|
MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
mali_gpu_clk, mali_gpu_vol/1000, 0, 0, 0);
#endif
mali_clk_put(MALI_FALSE);
return MALI_TRUE;
#ifdef CONFIG_REGULATOR
err_regulator:
regulator_put(g3d_regulator);
#endif
err_clk:
mali_clk_put(MALI_TRUE);
return ret;
}
static int mali_devfreq_target(struct device *dev, unsigned long *freq, u32 flags)
{
unsigned int nextStatus = (unsigned int)*freq;
unsigned int curStatus = 0;
curStatus = maliDvfsStatus.currentStep;
MALI_DEBUG_PRINT(4, ("= curStatus %d, nextStatus %d, maliDvfsStatus.currentStep %d\n", curStatus, nextStatus, maliDvfsStatus.currentStep));
/*if next status is same with current status, don't change anything*/
if (curStatus != nextStatus) {
#if MALI_DVFS_CLK_DEBUG
unsigned int *pRegMaliClkDiv;
unsigned int *pRegMaliMpll;
#endif
if (nextStatus > curStatus) {
#ifdef CONFIG_MALI_DVFS
update_time_in_state(curStatus);
#endif
#ifdef CONFIG_REGULATOR
/*change the voltage*/
mali_regulator_set_voltage(get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT), get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
#endif
/*change the clock*/
mali_clk_set_rate(mali_dvfs[nextStatus].clock, mali_dvfs[nextStatus].freq);
} else if (nextStatus < curStatus) {
#ifdef CONFIG_MALI_DVFS
update_time_in_state(curStatus);
#endif
/*change the clock*/
mali_clk_set_rate(mali_dvfs[nextStatus].clock, mali_dvfs[nextStatus].freq);
#ifdef CONFIG_REGULATOR
/*change the voltage*/
mali_regulator_set_voltage(get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT), get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
#endif
} else
return 0;
#if defined(CONFIG_MALI400_PROFILING)
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE|
MALI_PROFILING_EVENT_CHANNEL_GPU|
MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
mali_gpu_clk, mali_gpu_vol/1000, 0, 0, 0);
#endif
mali_clk_put(MALI_FALSE);
#if MALI_DVFS_CLK_DEBUG
pRegMaliClkDiv = ioremap(0x1003c52c, 32);
pRegMaliMpll = ioremap(0x1003c22c, 32);
MALI_PRINT(("Mali MPLL reg:%d, CLK DIV: %d \n", *pRegMaliMpll, *pRegMaliClkDiv));
#endif
set_mali_dvfs_current_step(nextStatus);
/*for future use*/
maliDvfsStatus.pCurrentDvfs = &mali_dvfs[nextStatus];
#if CPUFREQ_LOCK_DURING_440
/* lock/unlock CPU freq by Mali */
if (mali_dvfs[nextStatus].clock >= 440)
cpufreq_lock_by_mali(400);
else
cpufreq_unlock_by_mali();
#endif
/*wait until clock and voltage is stablized*/
mali_platform_wating(MALI_DVFS_WATING); /*msec*/
}
return 0;
}