unsigned long rtc_time_s3c2410(unsigned base) { struct tm tm; hwi_add_device(HWI_ITEM_BUS_UNKNOWN, HWI_ITEM_DEVCLASS_RTC, "s3c2410", 0); hwi_add_location(base, S3C2410_RTC_SIZE, 0, hwi_find_as(base, 1)); // get the current time from the RTC, and convert it to seconds since epoch chip_access(base, 0, 0, S3C2410_RTC_SIZE); // enable RTC chip_write8(S3C2410_RTCCON, chip_read8(S3C2410_RTCCON) | 1); // convert BCD to binary tm.tm_sec = bcd2bin(chip_read8(S3C2410_BCDSEC) & 0xff); // seconds tm.tm_min = bcd2bin(chip_read8(S3C2410_BCDMIN) & 0xff); // minutes tm.tm_hour = bcd2bin(chip_read8(S3C2410_BCDHOUR) & 0xff); // hours tm.tm_mday = bcd2bin(chip_read8(S3C2410_BCDDAY) & 0xff); // day tm.tm_mon = bcd2bin(chip_read8(S3C2410_BCDMON) & 0xff) -1; // month tm.tm_year = (bcd2bin(chip_read8(S3C2410_BCDYEAR) & 0xff))+100; // year chip_done(); return(calc_time_t(&tm)); }
unsigned long rtc_time_omap(unsigned base) { struct tm tm; hwi_add_device(HWI_ITEM_BUS_UNKNOWN, HWI_ITEM_DEVCLASS_RTC, "omap", 0); hwi_add_location(base, OMAP_RTC_SIZE, 0, hwi_find_as(base, 1)); // get the current time from the RTC, and convert it to seconds since epoch chip_access(base, 0, 0, OMAP_RTC_SIZE); // start the RTC, if it's not already running chip_write32(OMAP_RTC_CTRL, 0x01); // convert BCD to binary tm.tm_sec = bcd2bin(chip_read32(OMAP_RTC_SECONDS) & 0xff); // seconds tm.tm_min = bcd2bin(chip_read32(OMAP_RTC_MINUTES) & 0xff); // minutes tm.tm_hour = bcd2bin(chip_read32(OMAP_RTC_HOURS) & 0xff); // hours tm.tm_mday = bcd2bin(chip_read32(OMAP_RTC_DAYS) & 0xff); // day tm.tm_mon = bcd2bin(chip_read32(OMAP_RTC_MONTHS) & 0xff); // month tm.tm_year = (bcd2bin(chip_read32(OMAP_RTC_YEARS) & 0xff))+100; // year chip_done(); return(calc_time_t(&tm)); }
unsigned long rtc_time_primecell(unsigned base) { hwi_add_device(HWI_ITEM_BUS_UNKNOWN, HWI_ITEM_DEVCLASS_RTC, "primecell", 0); hwi_add_location(base, PRIMECELL_RTC_SIZE, 0, hwi_find_as(base, 1)); /* * Read counter register. * The manual says the RTSR interrupts bits are cleared on reset. */ return in32(base + PRIMECELL_RTC_DR); }
void hwi_add_rtc(const char *name, paddr_t base, unsigned reg_shift, unsigned len, int mmap, int cent_reg) { hwi_add_device(HWI_ITEM_BUS_UNKNOWN, HWI_ITEM_DEVCLASS_RTC, name, 0); hwi_add_location(base, len << reg_shift, reg_shift, hwi_find_as(base, mmap)); if(cent_reg != -1) { hwi_tag *cent = hwi_alloc_tag(HWI_TAG_INFO(regname)); cent->regname.regname = 0; cent->regname.offset = cent_reg; } }
void init_wdt_omap3530(void) { unsigned hwi_off; hwiattr_timer_t attr = HWIATTR_TIMER_T_INITIALIZER; const struct hwi_inputclk clksrc_kick = { .clk = 10, .div = 1 }; /* add the WATCHDOG device */ kprintf("Adding OMAP3530 watchdog timer\n"); HWIATTR_TIMER_SET_NUM_CLK(&attr, 1); HWIATTR_TIMER_SET_LOCATION(&attr, OMAP3530_WDT2_BASE, OMAP3530_WDT_SIZE, 0, hwi_find_as( OMAP3530_WDT2_BASE, 1)); hwi_off = hwidev_add_timer("wdog", &attr, HWI_NULL_OFF); ASSERT(hwi_off != HWI_NULL_OFF); hwitag_set_inputclk(hwi_off, 0, (struct hwi_inputclk *) &clksrc_kick); } __SRCVERSION( "$URL$ $Rev$" )
void hwi_imx51() { unsigned hwi_bus_internal = 0; /* add I2C (unless directed not to) */ { unsigned hwi_off; hwiattr_i2c_t attr = HWIATTR_I2C_T_INITIALIZER; HWIATTR_I2C_SET_NUM_IRQ(&attr, 1); /* create i2c0 and set the clock source */ HWIATTR_I2C_SET_LOCATION(&attr, MX51_I2C1_BASE, MX51_I2C_SIZE, 0, hwi_find_as(MX51_I2C1_BASE, 1)); hwi_off = hwibus_add_i2c(hwi_bus_internal, &attr); ASSERT(hwi_find_unit(hwi_off) == 0); hwitag_set_ivec(hwi_off, 0, MX51_I2C1_IRQ); /* create i2c1 and set the clock source */ HWIATTR_I2C_SET_LOCATION(&attr, MX51_I2C2_BASE, MX51_I2C_SIZE, 0, hwi_find_as(MX51_I2C2_BASE, 1)); hwi_off = hwibus_add_i2c(hwi_bus_internal, &attr); ASSERT(hwi_find_unit(hwi_off) == 1); hwitag_set_ivec(hwi_off, 0, MX51_I2C2_IRQ); } /* add UART */ { unsigned hwi_off; hwiattr_uart_t attr = HWIATTR_UART_T_INITIALIZER; struct hwi_inputclk clksrc = {.clk = uart_clock, .div = 16}; HWIATTR_UART_SET_NUM_IRQ(&attr, 1); HWIATTR_UART_SET_NUM_CLK(&attr, 1); /* create uart0 */ HWIATTR_UART_SET_LOCATION(&attr, MX51_UART1_BASE, MX51_UART_SIZE, 0, hwi_find_as(MX51_UART1_BASE, 1)); hwi_off = hwidev_add_uart(IMX51_HWI_UART, &attr, hwi_bus_internal); ASSERT(hwi_find_unit(hwi_off) == 0); hwitag_set_ivec(hwi_off, 0, MX51_UART1_INTR); hwitag_set_inputclk(hwi_off, 0, &clksrc); /* historically the UART's were called 'mxl' so add these synonyms */ hwi_add_synonym(hwi_find_device(IMX51_HWI_UART, 0), "sermxl"); } /*add the FEC */ { unsigned hwi_off; hwiattr_enet_t attr = HWIATTR_ENET_T_INITIALIZER; HWIATTR_USB_SET_NUM_IRQ(&attr, 1); /* create eTSEC0 and set the PHY address */ HWIATTR_ENET_SET_LOCATION(&attr, MX51_FEC_BASE, 0x4000, 0, hwi_find_as(MX51_FEC_BASE, 1)); hwi_off = hwidev_add_enet("fec", &attr, hwi_bus_internal); ASSERT(hwi_find_unit(hwi_off) == 0); hwitag_set_avail_ivec(hwi_off, 0, MX51_FEC_INTR); } /* add 1 USB controller */ { unsigned hwi_off; hwiattr_usb_t attr = HWIATTR_USB_T_INITIALIZER; HWIATTR_USB_SET_NUM_IRQ(&attr, 1); /* create usb0 */ HWIATTR_USB_SET_LOCATION(&attr, MX51_USBH1_BASE, MX51_USB_SIZE, 0, hwi_find_as(MX51_USBH1_BASE, 1)); hwi_off = hwibus_add_usb(hwi_bus_internal, &attr); ASSERT(hwi_off != HWI_NULL_OFF); hwitag_set_avail_ivec(hwi_off, 0, MX51_USB_INTR); } /* add 1 sdma controllers */ { unsigned hwi_off; hwiattr_dma_t attr = HWIATTR_DMA_T_INITIALIZER; HWIATTR_DMA_SET_NUM_IRQ(&attr, 1); /* create DMA controller 0 */ HWIATTR_USB_SET_LOCATION(&attr, MX51_SDMA_BASE, MX51_SDMA_SIZE, 0, hwi_find_as(MX51_SDMA_BASE, 1)); hwi_off = hwidev_add_dma(IMX51_HWI_DMA, &attr, hwi_bus_internal); ASSERT(hwi_find_unit(hwi_off) == 0); hwitag_set_avail_ivec(hwi_off, 0, MX51_SDMA_INTRU); } /* add the SSI device */ { unsigned hwi_off = hwidev_add("ssi", hwi_devclass_NONE, HWI_NULL_OFF); hwiattr_common_t attr = HWIATTR_COMMON_INITIALIZER; ASSERT(hwi_off != HWI_NULL_OFF); HWIATTR_SET_LOCATION(&attr, MX51_SSI1_BASE, MX51_SSI_SIZE, 0, hwi_find_as(MX51_SSI1_BASE, 1)); hwitag_add_common(hwi_off, &attr); } /*add the SDRAM */ { unsigned hwi_off = hwidev_add("sdram", hwi_devclass_NONE, HWI_NULL_OFF); hwiattr_common_t attr = HWIATTR_COMMON_INITIALIZER; ASSERT(hwi_off != HWI_NULL_OFF); HWIATTR_SET_LOCATION(&attr, MX51_SDRAM_BASE, MX51_SDRAM_SIZE, 0, hwi_find_as(MX51_SDRAM_BASE, 1)); hwitag_add_common(hwi_off, &attr); } /* add the WATCHDOG device */ { unsigned hwi_off; hwiattr_timer_t attr = HWIATTR_TIMER_T_INITIALIZER; const struct hwi_inputclk clksrc_kick = {.clk = 10, .div = 1}; HWIATTR_TIMER_SET_NUM_CLK(&attr, 1); HWIATTR_TIMER_SET_LOCATION(&attr, MX51_WDOG1_BASE, MX51_WDOG_SIZE, 0, hwi_find_as(MX51_WDOG1_BASE, 1)); hwi_off = hwidev_add_timer("wdog", &attr, HWI_NULL_OFF); ASSERT(hwi_off != HWI_NULL_OFF); hwitag_set_inputclk(hwi_off, 0, (struct hwi_inputclk *)&clksrc_kick); } } #if defined(__QNXNTO__) && defined(__USESRCVERSION) #include <sys/srcversion.h> __SRCVERSION("$URL: http://svn/product/branches/6.6.0/trunk/hardware/startup/lib/arm/hwi_imx51.c $ $Rev: 680332 $")