int imx_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count)
{
int i;
for (i = 0; i < count; i++)
imx_iomux_mode(pin_list[i]);
return 0;
}
static void pcm037_usb_init(void)
{
u32 tmp;
/* enable clock */
tmp = readl(0x53f80000);
tmp |= (1 << 9);
writel(tmp, 0x53f80000);
/* Host 1 */
tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600);
tmp &= ~((3 << 21) | 1);
tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 11) | (1 << 20);
writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600);
tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x184);
tmp &= ~(3 << 30);
tmp |= 2 << 30;
writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x184);
imx_iomux_mode(MX31_PIN_USBOTG_DATA0__USBOTG_DATA0);
imx_iomux_mode(MX31_PIN_USBOTG_DATA1__USBOTG_DATA1);
imx_iomux_mode(MX31_PIN_USBOTG_DATA2__USBOTG_DATA2);
imx_iomux_mode(MX31_PIN_USBOTG_DATA3__USBOTG_DATA3);
imx_iomux_mode(MX31_PIN_USBOTG_DATA4__USBOTG_DATA4);
imx_iomux_mode(MX31_PIN_USBOTG_DATA5__USBOTG_DATA5);
imx_iomux_mode(MX31_PIN_USBOTG_DATA6__USBOTG_DATA6);
imx_iomux_mode(MX31_PIN_USBOTG_DATA7__USBOTG_DATA7);
imx_iomux_mode(MX31_PIN_USBOTG_CLK__USBOTG_CLK);
imx_iomux_mode(MX31_PIN_USBOTG_DIR__USBOTG_DIR);
imx_iomux_mode(MX31_PIN_USBOTG_NXT__USBOTG_NXT);
imx_iomux_mode(MX31_PIN_USBOTG_STP__USBOTG_STP);
mdelay(50);
ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x170), 1);
/* Host 2 */
tmp = readl(MX31_IOMUXC_GPR);
tmp |= 1 << 11; /* IOMUX GPR: enable USBH2 signals */
writel(tmp, MX31_IOMUXC_GPR);
imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC));
#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
imx_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
imx_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
imx_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
imx_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
imx_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
imx_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
imx_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
imx_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
imx_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
imx_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
imx_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
imx_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600);
tmp &= ~((3 << 21) | 1);
tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20);
writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600);
tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x584);
tmp &= ~(3 << 30);
tmp |= 2 << 30;
writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x584);
mdelay(50);
ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x570), 1);
/* Set to Host mode */
tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x1a8);
writel(tmp | 0x3, MX31_USB_OTG_BASE_ADDR + 0x1a8);
}