/* * Initialize CPU control registers */ void initializecpu(void) { uint64_t msr; uint32_t cr4; cr4 = rcr4(); if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { cr4 |= CR4_FXSR | CR4_XMM; cpu_fxsr = hw_instruction_sse = 1; } if (cpu_stdext_feature & CPUID_STDEXT_FSGSBASE) cr4 |= CR4_FSGSBASE; /* * Postpone enabling the SMEP on the boot CPU until the page * tables are switched from the boot loader identity mapping * to the kernel tables. The boot loader enables the U bit in * its tables. */ if (!IS_BSP() && (cpu_stdext_feature & CPUID_STDEXT_SMEP)) cr4 |= CR4_SMEP; load_cr4(cr4); if ((amd_feature & AMDID_NX) != 0) { msr = rdmsr(MSR_EFER) | EFER_NXE; wrmsr(MSR_EFER, msr); pg_nx = PG_NX; } switch (cpu_vendor_id) { case CPU_VENDOR_AMD: init_amd(); break; case CPU_VENDOR_CENTAUR: init_via(); break; } }
AMD create_amd ( int run, int buff_size, float *in_buff, float *out_buff, int mode, int levelfade, int sbmode, int sample_rate, float fmin, float fmax, float zeta, float omegaN, float tauR, float tauI ) { AMD a = (AMD) malloc0 (sizeof(amd)); a->run = run; a->buff_size = buff_size; a->in_buff = in_buff; a->out_buff = out_buff; a->mode = mode; a->levelfade = levelfade; a->sbmode = sbmode; a->sample_rate = (float)sample_rate; a->fmin = fmin; a->fmax = fmax; a->zeta = zeta; a->omegaN = omegaN; a->tauR = tauR; a->tauI = tauI; init_amd(a); return a; }