static int mixer_ioctl(struct inode *inode, struct file *file, uint cmd, ulong arg) { /* * We only accept mixer (type 'M') ioctls. */ if (_IOC_TYPE(cmd) != 'M') return -EINVAL; return l3_command(&uda1341, cmd, (void *)arg); }
/* * FIXME: what about SFRM going high when SSP is disabled? */ static void assabet_set_samplerate(long val) { struct uda1341_cfg cfg; u_int clk_ref, clk_div; /* We don't want to mess with clocks when frames are in flight */ Ser4SSCR0 &= ~SSCR0_SSE; /* wait for any frame to complete */ udelay(125); /* * Our clock source is derived from the CPLD on which we don't have * much control unfortunately. This was intended for a fixed 48000 Hz * samplerate assuming a core clock of 221.2 MHz. The CPLD appears * to divide the memory clock so there is a ratio of 4608 between * the core clock and the resulting samplerate (obtained by * measurements, the CPLD equations should confirm that). * * Still we can play with the SA1110's clock divisor for the SSP port * to get half the samplerate as well. * * Apparently the clock sent to the SA1110 for the SSP port is further * more divided from the clock sent to the UDA1341 (some people tried * to be too clever in their design, or simply failed to read the * SA1110 manual). If it was the same clock we would have been able * to support a third samplerate with the UDA1341's 384FS mode. * * At least it would have been a minimum acceptable solution to be * able to set the CPLD divisor by software. The iPAQ design is * certainly a better example to follow for a new design. */ clk_ref = cpufreq_get(0) * 1000 / 4608; if (val > clk_ref*4/7) { audio_samplerate = clk_ref; cfg.fs = 256; clk_div = SSCR0_SerClkDiv(2); } else { audio_samplerate = clk_ref/2; cfg.fs = 512; clk_div = SSCR0_SerClkDiv(4); } cfg.format = FMT_LSB16; l3_command(&uda1341, L3_UDA1341_CONFIGURE, &cfg); Ser4SSCR0 = (Ser4SSCR0 & ~0xff00) + clk_div + SSCR0_SSE; }
static int __init sa1111_uda1341_init(void) { struct uda1341_cfg cfg; int ret; if ( !( (machine_is_assabet() && machine_has_neponset()) || machine_is_jornada720() )) return -ENODEV; ret = l3_attach_client(&uda1341, "l3-sa1111", "uda1341"); if (ret) goto out; /* Acquire and initialize DMA */ ret = sa1111_sac_request_dma(&output_stream.dma_ch, "SA1111 audio out", SA1111_SAC_XMT_CHANNEL); if (ret < 0) goto release_l3; ret = sa1111_sac_request_dma(&input_stream.dma_ch, "SA1111 audio in", SA1111_SAC_RCV_CHANNEL); if (ret < 0) goto release_dma; cfg.fs = 256; cfg.format = FMT_I2S; l3_command(&uda1341, L3_UDA1341_CONFIGURE, &cfg); /* register devices */ audio_dev_id = register_sound_dsp(&sa1111_audio_fops, -1); mixer_dev_id = register_sound_mixer(&uda1341_mixer_fops, -1); printk(KERN_INFO "SA1111 UDA1341 audio driver initialized\n"); return 0; release_dma: sa1100_free_dma(output_stream.dma_ch); release_l3: l3_detach_client(&uda1341); out: return ret; }
static void pangolin_set_samplerate(long val) { struct uda1341_cfg cfg; int clk_div; /* We don't want to mess with clocks when frames are in flight */ Ser4SSCR0 &= ~SSCR0_SSE; /* wait for any frame to complete */ udelay(125); /* * Our clock source is derived from the CPLD on which we don't have * much control unfortunately. This was intended for a fixed 44100Hz * samplerate assuming a core clock of 206 MHz. Still we can play * with the SA1110's clock divisor for the SSP port to get a 22050Hz * samplerate. * * Apparently the clock sent to the SA1110 for the SSP port is * divided from the clock sent to the UDA1341 (some people tried to * be too clever in their design, or simply failed to read the SA1110 * manual). If it was the same source we would have been able to * support a third samplerate. * * At least it would have been a minimum acceptable solution to be * able to set the CPLD divisor by software. The iPAQ design is * certainly a better example to follow for a new design. */ if (val >= 44100) { audio_samplerate = 44100; cfg.fs = 256; clk_div = SSCR0_SerClkDiv(2); } else { audio_samplerate = 22050; cfg.fs = 512; clk_div = SSCR0_SerClkDiv(4); } cfg.format = FMT_LSB16; l3_command(&uda1341, L3_UDA1341_CONFIGURE, &cfg); Ser4SSCR0 = (Ser4SSCR0 & ~0xff00) + clk_div + SSCR0_SSE; }
static void h3600_set_samplerate(long val) { struct uda1341_cfg cfg; int clk_div = 0; /* We don't want to mess with clocks when frames are in flight */ Ser4SSCR0 &= ~SSCR0_SSE; /* wait for any frame to complete */ udelay(125); /* * We have the following clock sources: * 4.096 MHz, 5.6245 MHz, 11.2896 MHz, 12.288 MHz * Those can be divided either by 256, 384 or 512. * This makes up 12 combinations for the following samplerates... */ if (val >= 48000) val = 48000; else if (val >= 44100) val = 44100; else if (val >= 32000) val = 32000; else if (val >= 29400) val = 29400; else if (val >= 24000) val = 24000; else if (val >= 22050) val = 22050; else if (val >= 21970) val = 21970; else if (val >= 16000) val = 16000; else if (val >= 14647) val = 14647; else if (val >= 10985) val = 10985; else if (val >= 10666) val = 10666; else val = 8000; /* Set the external clock generator */ h3600_set_audio_clock(val); /* Select the clock divisor */ switch (val) { case 8000: case 10985: case 22050: case 24000: cfg.fs = 512; clk_div = SSCR0_SerClkDiv(16); break; case 16000: case 21970: case 44100: case 48000: cfg.fs = 256; clk_div = SSCR0_SerClkDiv(8); break; case 10666: case 14647: case 29400: case 32000: cfg.fs = 384; clk_div = SSCR0_SerClkDiv(12); break; } cfg.format = FMT_LSB16; l3_command(&uda1341, L3_UDA1341_CONFIGURE, &cfg); Ser4SSCR0 = (Ser4SSCR0 & ~0xff00) + clk_div + SSCR0_SSE; audio_samplerate = val; }
static void omap1510_set_samplerate(long val) { struct uda1341_cfg cfg; u8 fpga; printk(__FUNCTION__ "called\n"); /* We don't want to mess with clocks when frames are in flight */ // TODO - could call omap1510_dma_flush_all, or could poll on // enable bit to wait for DMA writes to stop. /* wait for any frame to complete */ udelay(125); /* * We have the following clock sources: * 12.288 MHz and 16.9344 MHz. * We have dividers in the FPGA (1, 2, 4), and in * the codec. * clock epld div codec_div freq * 12.288 1 256 48K * " 4 384 8K * 16.9344 1 384 44.1K * " 2 384 22.05K * " 4 384 11.025K */ if (val >= 48000) val = 48000; else if (val >= 44100) val = 44100; else if (val >= 22050) val = 22050; else if (val >= 11025) val = 11025; else val = 8000; /* Set the external clock generator */ switch (val) { case 48000: case 8000: /* 12.288 MHz */ fpga = fpga_read(OMAP1510P1_FPGA_AUDIO); if (fpga & 0x4) { fpga &= ~0x4; fpga_write(fpga, OMAP1510P1_FPGA_AUDIO); } break; default: /* 16.3944 MHz */ fpga = fpga_read(OMAP1510P1_FPGA_AUDIO); if ((fpga & 0x4) == 0) { fpga |= 0x4; fpga_write(fpga, OMAP1510P1_FPGA_AUDIO); } break; } /* Select the clock divisor */ switch (val) { #if 0 case case cfg.fs = 512; break; #endif case 48000: cfg.fs = 256; break; default: cfg.fs = 384; break; } cfg.format = FMT_I2S; l3_command(&uda1341, L3_UDA1341_CONFIGURE, &cfg); audio_samplerate = val; }