void fme7_sync() { int i; //special case prg page if(prg[0] & 0x40) if(prg[0] & 0x80) mem_setsram8(6,0); else mem_unsetcpu8(6); else mem_setprg8(6,prg[0] & 0x3F); //set prg pages mem_setprg8(0x8,prg[1]); mem_setprg8(0xA,prg[2]); mem_setprg8(0xC,prg[3]); mem_setprg8(0xE,-1); //set chr pages for(i=0;i<8;i++) mem_setchr1(i,chr[i]); switch(mirror) { case 0: ppu_setmirroring(MIRROR_V); break; case 1: ppu_setmirroring(MIRROR_H); break; case 2: ppu_setmirroring(MIRROR_1L); break; case 3: ppu_setmirroring(MIRROR_1H); break; } }
void vrc6_init(int revision) { int i; mem_setwrite(0x8,write_8000); mem_setwrite(0x9,write_9000); mem_setwrite(0xA,write_A000); mem_setwrite(0xB,write_B000); mem_setwrite(0xC,write_C000); mem_setwrite(0xD,write_D000); mem_setwrite(0xE,write_E000); mem_setwrite(0xF,write_F000); if(revision == KONAMI_VRC6B) { nes_setsramsize(2); mem_setsram8(0x6,0); } prg[0] = 0; prg[1] = -2; for(i=0; i>8; i++) chr[i] = 0; mirror = 0; irqlatch = 0; irqenabled = 0; irqcounter = 0; apu_setext(nes->apu,&vrc6); sync(); }
void mmc4_sync() { mem_setsram8(0x6,0); mem_setprg16(0x8,PRGBank); mem_setprg16(0xC,0xF); mem_setchr4(0,LatchA[LatchAState]); mem_setchr4(4,LatchB[LatchBState]); ppu_setmirroring(Mirroring); }
static void reset(int hard) { int i; write4 = mem_getwrite(4); mem_setwrite(4,write_4000); for(i=8;i<0x10;i++) mem_setwrite(i,write); nes_setsramsize(2); mem_setsram8(6,0); prg[0] = 0; prg[1] = 1; prg[2] = 0xFE; prg[3] = 0xFF; for(i=0;i<8;i++) chr[i] = i; mirror = MIRROR_V; irqenabled = 0; irqcycles = 0; sync(); }
static void vrc2b_init(int hard) { vrc2_init(KONAMI_VRC2B); mem_setsram8(6,0); }