void tiva_adc_clock(uint32_t freq)
{
#if defined(CONFIG_ARCH_CHIP_TM4C123)
/* For the TM4C123, the ADC clock source does not affect the frequency, it
* runs at 16 MHz regardless. You end up selecting between the MOSC (default)
* or the PIOSC. The PIOSC allows the ADC to operate even in deep sleep mode.
* Since this is the case, the clock value for the TM4C123 is always 16 MHz
*/
uintptr_t ccreg = (TIVA_ADC0_BASE + TIVA_ADC_CC_OFFSET);
modifyreg32(ccreg, ADC_CC_CS_MASK, (ADC_CC_CS_PIOSC & ADC_CC_CS_MASK));
#elif defined (CONFIG_ARCH_CHIP_TM4C129)
/* check clock bounds and specific match cases */
uint32_t clk_src = 0;
uint32_t div = 0;
if (freq > TIVA_ADC_CLOCK_MAX)
{
clk_src = ADC_CC_CS_SYSPLL;
div = (BOARD_FVCO_FREQUENCY / TIVA_ADC_CLOCK_MAX);
}
else if (freq < TIVA_ADC_CLOCK_MIN)
{
clk_src = ADC_CC_CS_PIOSC;
div = 1;
}
else if (freq == XTAL_FREQUENCY)
{
clk_src = ADC_CC_CS_MOSC;
div = 1;
}
else
{
clk_src = ADC_CC_CS_SYSPLL;
div = (BOARD_FVCO_FREQUENCY / freq);
}
uintptr_t ccreg = (TIVA_ADC0_BASE + TIVA_ADC_CC_OFFSET);
modifyreg32(ccreg, ADC_CC_CLKDIV_MASK, CLOCK_CONFIG(div, clk_src));
#else
# error Unsupported architecture reported
#endif
}
void lc823450_mtm_stop_oneshot(void)
{
/* Clear the interrupt (BEVT) */
putreg32(1 << 1, rMT01STS);
/* Disable MTM0-ch1 */
modifyreg32(rMT0OPR, 1 << 1, 0);
}
void tiva_adc_sse_trigger(uint8_t adc, uint8_t sse, uint32_t trigger)
{
uintptr_t emuxreg = (TIVA_ADC_EMUX(adc));
uint32_t trig = ((trigger << ADC_EMUX_SHIFT(sse)) & ADC_EMUX_MASK(sse));
modifyreg32(emuxreg, ADC_EMUX_MASK(sse), trig);
/* NOTE: PWM triggering needs an additional register to be set (ADC_TSSEL)
* A platform specific IOCTL command is provided to configure the triggering.
*/
}
void tiva_adc_sse_register_chn(uint8_t adc, uint8_t sse, uint8_t chn,
uint32_t ain)
{
/* Configure SSE mux (SSMUX) with step number */
uintptr_t ssmuxreg = (TIVA_ADC_BASE(adc) + TIVA_ADC_SSMUX(sse));
uint32_t step = 0;
step = ((ain << ADC_SSMUX_MUX_SHIFT(chn)) & ADC_SSMUX_MUX_MASK(chn));
modifyreg32(ssmuxreg, ADC_SSMUX_MUX_MASK(chn), step);
#ifdef CONFIG_ARCH_CHIP_TM4C129
/* Configure SSE extended mux (SSEMUX) with step number and configuration */
ssmuxreg = (TIVA_ADC_BASE(adc) + TIVA_ADC_SSEMUX(sse));
step = ((1 << ADC_SSEMUX_MUX_SHIFT(chn)) & ADC_SSEMUX_MUX_MASK(chn));
modifyreg32(ssmuxreg, ADC_SSEMUX_MUX_MASK(chn), step);
#endif
}
void stm32_rcc_disablelsi(void)
{
/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
* bit the RCC CSR register.
*/
modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0);
/* LSIRDY should go low after 3 LSI clock cycles */
}
static void sdb_fixups(void)
{
/**
* DETECT_IN is not working on both GPBridges on the SDB. The workaround
* is to pull up GPIO24.
*
* Documentation related to this fix (items 33 and 44)
* https://docs.google.com/spreadsheets/d/1BBVHjFZu6GEUDCua8WlXHl9TmGYdpUwQXF82NXWEI-o/edit#gid=779323147
*
* This change will have no impact on BDB2{A,B} since the GPIO24 is
* only connected to a test point.
*/
if (tsb_get_product_id() == tsb_pid_gpbridge) {
modifyreg32(TSB_IO_PULL_UPDOWN_ENABLE0, TSB_IO_PULL_UPDOWN_GPIO(24), 0);
modifyreg32(TSB_IO_PULL_UPDOWN0, 0, TSB_IO_PULL_UPDOWN_GPIO(24));
}
/**
* When attached to the 96Boards Expansion Header on the SDB, Helium is
* held in reset unless HELIUM_EXT_NRST_BTN_GPIO is pulled high or
* driven high on APBridgeA.
*
* Rob Herring indicates that this behavior is the opposite of the
* 96Boards specification, which would suggest active low.
*
* We'll pull the pin high, as that's less aggressive and avoids
* the need to enable the GPIO subsystem at this point in the boot
* sequence.
*
* This change should have no impact on BDB2{A,B} since on APBridgeA,
* HELIUM_EXT_NRST_BTN_GPIO is only connected to a test point.
*/
#ifdef CONFIG_APBRIDGEA
if (tsb_get_product_id() == tsb_pid_apbridge) {
modifyreg32(TSB_IO_PULL_UPDOWN_ENABLE0,
TSB_IO_PULL_UPDOWN_GPIO(HELIUM_EXT_NRST_BTN_GPIO),
0);
modifyreg32(TSB_IO_PULL_UPDOWN0,
0,
TSB_IO_PULL_UPDOWN_GPIO(HELIUM_EXT_NRST_BTN_GPIO));
}
#endif
}
void tiva_adc_sample_rate(uint8_t rate)
{
uintptr_t pcreg = (TIVA_ADC0_BASE + TIVA_ADC_PC_OFFSET);
/* NOTE: ADC_PC_SR_MASK is intended for use with the TM4C123, the
* alternative is ADC_PC_MCR_MASK for the TM4C129. However both masks
* mask off the first 4 bits (0xF) so there is no need to distinguish
* between the two.
*/
modifyreg32(pcreg, ADC_PC_SR_MASK, (rate & ADC_PC_SR_MASK));
}
void stm32_rcc_enablelsi(void)
{
/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
* bit the RCC CSR register.
*/
modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION);
/* Wait for the internal RC 40 kHz oscillator to be stable. */
while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0);
}
void tiva_adc_sse_differential(uint8_t adc, uint8_t sse, uint8_t chn, uint32_t diff)
{
#ifdef CONFIG_TIVA_ADC_DIFFERENTIAL
# error CONFIG_TIVA_ADC_DIFFERENTIAL unsupported!!
#else
/* for now, ensure the FIFO is used and differential sampling is disabled */
uintptr_t ssopreg = (TIVA_ADC_BASE(adc) + TIVA_ADC_SSOP(sse));
uint32_t sdcopcfg = (1 << chn);
modifyreg32(ssopreg, sdcopcfg, 0);
#endif
}
int stm32_exti_pvd(bool risingedge, bool fallingedge, bool event,
xcpt_t func, void *arg)
{
/* Get the previous GPIO IRQ handler; Save the new IRQ handler. */
g_pvd_callback = func;
g_callback_arg = arg;
/* Install external interrupt handlers (if not already attached) */
if (func)
{
irq_attach(STM32_IRQ_PVD, stm32_exti_pvd_isr, NULL);
up_enable_irq(STM32_IRQ_PVD);
}
else
{
up_disable_irq(STM32_IRQ_PVD);
}
/* Configure rising/falling edges */
modifyreg32(STM32_EXTI_RTSR,
risingedge ? 0 : EXTI_PVD_LINE,
risingedge ? EXTI_PVD_LINE : 0);
modifyreg32(STM32_EXTI_FTSR,
fallingedge ? 0 : EXTI_PVD_LINE,
fallingedge ? EXTI_PVD_LINE : 0);
/* Enable Events and Interrupts */
modifyreg32(STM32_EXTI_EMR,
event ? 0 : EXTI_PVD_LINE,
event ? EXTI_PVD_LINE : 0);
modifyreg32(STM32_EXTI_IMR,
func ? 0 : EXTI_PVD_LINE,
func ? EXTI_PVD_LINE : 0);
return OK;
}
static void hrt_usleep_setup(void)
{
uint32_t count;
struct hrt_s *head;
irqstate_t flags;
flags = spin_lock_irqsave();
head = container_of(hrt_timer_queue.head, struct hrt_s, ent);
if (head == NULL)
{
/* MTM2: disable clocking */
modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2C_CLKEN, 0x0);
modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2_CLKEN, 0x0);
spin_unlock_irqrestore(flags);
return;
}
/* MTM2: enable clocking */
modifyreg32(MCLKCNTEXT1, 0x0, MCLKCNTEXT1_MTM2_CLKEN);
modifyreg32(MCLKCNTEXT1, 0x0, MCLKCNTEXT1_MTM2C_CLKEN);
count = (uint64_t)XT1OSC_CLK * head->usec / (1000 * 1000) / 10;
if (count >= 0x8000)
{
count = 0x7fff;
}
putreg32(0, rMT20CNT); /* counter */
putreg32(count, rMT20A); /* AEVT counter */
/* Enable MTM2-Ch0 */
putreg32(1, rMT2OPR);
spin_unlock_irqrestore(flags);
}
void tiva_adc_sse_int_enable(uint8_t adc, uint8_t sse, bool state)
{
irqstate_t flags;
uintptr_t imreg = TIVA_ADC_IM(adc);
int irq = tiva_adc_getirq(adc, sse);
flags = enter_critical_section();
up_disable_irq(irq);
tiva_adc_sse_clear_int(adc, sse);
if (state == true)
{
modifyreg32(imreg, 0, (1 << sse));
}
else
{
modifyreg32(imreg, (1 << sse), 0);
}
up_enable_irq(irq);
leave_critical_section(flags);
}
int imxrt_gpioirq_disable(int irq)
{
uintptr_t regaddr;
unsigned int pin;
int ret;
ret = imxrt_gpio_info(irq, ®addr, &pin);
if (ret >= 0)
{
modifyreg32(regaddr, 1 << pin, 0);
}
return ret;
}
/** \todo Detach interrupts, and close down all TIM Channels */
int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
{
ASSERT(dev);
/* Disable power */
switch( ((struct stm32_tim_priv_s *)dev)->base ) {
#if CONFIG_STM32_TIM2
case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); break;
#endif
#if CONFIG_STM32_TIM3
case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); break;
#endif
#if CONFIG_STM32_TIM4
case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); break;
#endif
#if CONFIG_STM32_TIM5
case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); break;
#endif
#if STM32_NBTIM > 0
#if CONFIG_STM32_TIM6
case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); break;
#endif
#endif
#if STM32_NBTIM > 1
#if CONFIG_STM32_TIM7
case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); break;
#endif
#endif
#if STM32_NATIM > 0
#if CONFIG_STM32_TIM1
case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break;
#endif
#if CONFIG_STM32_TIM8
case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break;
#endif
#endif
default: return ERROR;
}
/* Mark it as free */
((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED;
return OK;
}
int
ToneAlarm::init()
{
int ret;
ret = CDev::init();
if (ret != OK) {
return ret;
}
/* configure the GPIO to the idle state */
px4_arch_configgpio(GPIO_TONE_ALARM_IDLE);
#ifdef GPIO_TONE_ALARM_NEG
px4_arch_configgpio(GPIO_TONE_ALARM_NEG);
#endif
/* clock/power on our timer */
modifyreg32(TONE_ALARM_CLOCK_POWER_REG, 0, TONE_ALARM_CLOCK_ENABLE);
/* initialise the timer */
rCR1 = 0;
rCR2 = 0;
rSMCR = 0;
rDIER = 0;
rCCER &= TONE_CCER; /* unlock CCMR* registers */
rCCMR1 = TONE_CCMR1;
rCCMR2 = TONE_CCMR2;
rCCER = TONE_CCER;
rDCR = 0;
#ifdef rBDTR // If using an advanced timer, you need to activate the output
rBDTR = ATIM_BDTR_MOE; // enable the main output of the advanced timer
#endif
/* toggle the CC output each time the count passes 1 */
TONE_rCCR = 1;
/* default the timer to a prescale value of 1; playing notes will change this */
rPSC = 0;
/* make sure the timer is running */
rCR1 = GTIM_CR1_CEN;
DEVICE_DEBUG("ready");
return OK;
}
static void led_pwm_timer_init_timer(unsigned timer)
{
irqstate_t flags = px4_enter_critical_section();
/* enable the timer clock before we try to talk to it */
modifyreg32(led_pwm_timers[timer].clock_register, 0, led_pwm_timers[timer].clock_bit);
/* disable and configure the timer */
rCR1(timer) = 0;
rCR2(timer) = 0;
rSMCR(timer) = 0;
rDIER(timer) = 0;
rCCER(timer) = 0;
rCCMR1(timer) = 0;
rCCMR2(timer) = 0;
rCCR1(timer) = 0;
rCCR2(timer) = 0;
rCCR3(timer) = 0;
rCCR4(timer) = 0;
rCCER(timer) = 0;
rDCR(timer) = 0;
if ((led_pwm_timers[timer].base == STM32_TIM1_BASE) || (led_pwm_timers[timer].base == STM32_TIM8_BASE)) {
/* master output enable = on */
rBDTR(timer) = ATIM_BDTR_MOE;
}
/* If the timer clock source provided as clock_freq is the STM32_APBx_TIMx_CLKIN
* then configure the timer to free-run at 1MHz.
* Otherwise, other frequencies are attainable by adjusting .clock_freq accordingly.
*/
rPSC(timer) = (led_pwm_timers[timer].clock_freq / 1000000) - 1;
/* configure the timer to update at the desired rate */
rARR(timer) = (1000000 / LED_PWM_RATE) - 1;
/* generate an update event; reloads the counter and all registers */
rEGR(timer) = GTIM_EGR_UG;
px4_leave_critical_section(flags);
}
/**
* @brief initialize FLASH for QUAD IO in 80Mhz
* @param void
* @return void
* @note
*/
void s5j_sflash_init(void)
{
s5j_sflash_disable_wp();
modifyreg32(S5J_SFLASH_SFCON, 0, SFLASH_SFCON_ERASE_WAIT_ON);
putreg32(SFLASH_PERF_MODE_DUAL_QUAD, S5J_SFLASH_PERF_MODE);
putreg32(SFLASH_IO_MODE_QUAD_FAST_READ, S5J_SFLASH_IO_MODE);
/* Check FLASH has Quad Enabled */
while (!(s5j_sflash_read_status() & (0x1 << 6))) ;
lldbg("FLASH Quad Enabled\n");
s5j_sflash_enable_wp();
/* Set FLASH clk 80Mhz for Max performance */
s5j_clk_set_rate(CLK_SPL_SFLASH, 80000000);
}
static inline void stm32_dac_modify_cr(FAR struct stm32_chan_s *chan,
uint32_t clearbits, uint32_t setbits)
{
unsigned int shift;
/* DAC1 channels 1 and 2 share the STM32_DAC[1]_CR control register. DAC2
* channel 1 (and perhaps channel 2) uses the STM32_DAC2_CR control
* register. In either case, bit 0 of the interface number provides the
* correct shift.
*
* Bit 0 = 0: Shift = 0
* Bit 0 = 1: Shift = 16
*/
shift = (chan->intf & 1) << 4;
modifyreg32(chan->cr, clearbits << shift, setbits << shift);
}
void stm32_rcc_enablelse(void)
{
/* The LSE is in the RTC domain and write access is denied to this domain
* after reset, you have to enable write access using DBP bit in the PWR CR
* register before to configuring the LSE.
*/
stm32_pwr_enablebkp(true);
#if defined(CONFIG_STM32_STM32L15XX)
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit
* the RCC CSR register.
*/
modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSEON);
/* Wait for the LSE clock to be ready */
while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSERDY) == 0)
{
up_waste();
}
#else
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit
* the RCC BDCR register.
*/
modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON);
/* Wait for the LSE clock to be ready */
while ((getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) == 0)
{
up_waste();
}
#endif
/* Disable backup domain access if it was disabled on entry */
stm32_pwr_enablebkp(false);
}
int
ToneAlarm::init()
{
int ret;
ret = CDev::init();
if (ret != OK)
return ret;
#if defined(CONFIG_ARCH_BOARD_PX4FMU_V1) || defined(CONFIG_ARCH_BOARD_PX4FMU_V2)
/* configure the GPIO to the idle state */
stm32_configgpio(GPIO_TONE_ALARM_IDLE);
/* clock/power on our timer */
modifyreg32(STM32_RCC_APB1ENR, 0, TONE_ALARM_CLOCK_ENABLE);
/* initialise the timer */
rCR1 = 0;
rCR2 = 0;
rSMCR = 0;
rDIER = 0;
rCCER &= TONE_CCER; /* unlock CCMR* registers */
rCCMR1 = TONE_CCMR1;
rCCMR2 = TONE_CCMR2;
rCCER = TONE_CCER;
rDCR = 0;
/* toggle the CC output each time the count passes 1 */
TONE_rCCR = 1;
/* default the timer to a prescale value of 1; playing notes will change this */
rPSC = 0;
/* make sure the timer is running */
rCR1 = GTIM_CR1_CEN;
#endif
debug("ready");
return OK;
}
int
ToneAlarm::init()
{
int ret;
ret = CDev::init();
if (ret != OK)
return ret;
/* configure the GPIO to the idle state */
stm32_configgpio(GPIO_TONE_ALARM_IDLE);
/* clock/power on our timer */
modifyreg32(TONE_ALARM_CLOCK_POWER_REG, 0, TONE_ALARM_CLOCK_ENABLE);
/* initialise the timer */
rCR1 = 0;
rCR2 = 0;
rSMCR = 0;
rDIER = 0;
rCCER &= TONE_CCER; /* unlock CCMR* registers */
rCCMR1 = TONE_CCMR1;
rCCMR2 = TONE_CCMR2;
rCCER = TONE_CCER;
rDCR = 0;
/* toggle the CC output each time the count passes 1 */
TONE_rCCR = 1;
/* default the timer to a prescale value of 1; playing notes will change this */
rPSC = 0;
/* make sure the timer is running */
rCR1 = GTIM_CR1_CEN;
DEVICE_DEBUG("ready");
return OK;
}
/**
* Initialise the timer we are going to use.
*
* We expect that we'll own one of the reduced-function STM32 general
* timers, and that we can use channel 1 in compare mode.
*/
static void
hrt_tim_init(void)
{
/* claim our interrupt vector */
irq_attach(HRT_TIMER_VECTOR, hrt_tim_isr);
/* clock/power on our timer */
modifyreg32(HRT_TIMER_POWER_REG, 0, HRT_TIMER_POWER_BIT);
/* disable and configure the timer */
rCR1 = 0;
rCR2 = 0;
rSMCR = 0;
rDIER = DIER_HRT | DIER_PPM;
rCCER = 0; /* unlock CCMR* registers */
rCCMR1 = CCMR1_PPM;
rCCMR2 = CCMR2_PPM;
rCCER = CCER_PPM;
rDCR = 0;
/* configure the timer to free-run at 1MHz */
rPSC = (HRT_TIMER_CLOCK / 1000000) - 1; /* this really only works for whole-MHz clocks */
/* run the full span of the counter */
rARR = 0xffff;
/* set an initial capture a little ways off */
rCCR_HRT = 1000;
/* generate an update event; reloads the counter, all registers */
rEGR = GTIM_EGR_UG;
/* enable the timer */
rCR1 = GTIM_CR1_CEN;
/* enable interrupts */
up_enable_irq(HRT_TIMER_VECTOR);
}
void imxrt_wdog_disable_all(void)
{
uint32_t reg;
reg = getreg32(IMXRT_WDOG1_WCR);
if (reg & WDOG_WCR_WDE)
{
reg &= ~WDOG_WCR_WDE;
putreg32(reg, IMXRT_WDOG1_WCR);
}
reg = getreg32(IMXRT_WDOG2_WCR);
if (reg & WDOG_WCR_WDE)
{
reg &= ~WDOG_WCR_WDE;
putreg32(reg, IMXRT_WDOG2_WCR);
}
putreg32(RTWDOG_UPDATE_KEY, IMXRT_RTWDOG_CNT);
putreg32(0xFFFF, IMXRT_RTWDOG_TOVAL);
modifyreg32(IMXRT_RTWDOG_CS, RTWDOG_CS_EN, RTWDOG_CS_UPDATE);
}
void up_disable_irq(int irq)
{
DEBUGASSERT((unsigned)irq < NR_IRQS);
/* Check for an external interrupt */
if (irq >= SAM_IRQ_INTERRUPT && irq < SAM_IRQ_INTERRUPT + SAM_IRQ_NINTS)
{
/* Set the appropriate bit in the ICER register to disable the
* interrupt
*/
putreg32((1 << (irq - SAM_IRQ_INTERRUPT)), ARMV6M_NVIC_ICER);
}
/* Handle processor exceptions. Only SysTick can be disabled */
else if (irq == SAM_IRQ_SYSTICK)
{
modifyreg32(ARMV6M_SYSTICK_CSR, SYSTICK_CSR_ENABLE, 0);
}
sam_dumpnvic("disable", irq);
}
void stm32_pwr_enablebkp(void)
{
modifyreg32(STM32_PWR_BASE + (uint32_t)STM32_PWR_CR_OFFSET, (uint32_t)0, (uint32_t)PWR_CR_DBP);
}
void tiva_adc_sse_sample_hold_time(uint8_t adc, uint8_t sse,
uint8_t chn, uint32_t shold)
{
uintptr_t sstshreg = (TIVA_ADC_BASE(adc) + TIVA_ADC_SSTSH(sse));
modifyreg32(sstshreg, ADC_SSTSH_MASK(sse), (shold << ADC_SSTSH_SHIFT(sse)));
}
void tiva_adc_sse_clear_int(uint8_t adc, uint8_t sse)
{
uintptr_t iscreg = TIVA_ADC_ISC(adc);
modifyreg32(iscreg, 0, (1 << sse));
}
static inline int stm32_cap_set_rcc(FAR const struct stm32_cap_priv_s *priv,
bool on)
{
uint32_t offset = 0;
uint32_t mask = 0;
switch (priv->base)
{
#ifdef CONFIG_STM32F7_TIM1_CAP
case STM32_TIM1_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM1EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM2_CAP
case STM32_TIM2_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM2EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM3_CAP
case STM32_TIM3_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM3EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM4_CAP
case STM32_TIM4_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM4EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM5_CAP
case STM32_TIM5_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM5EN;
break;
#endif
/* TIM6 and TIM7 cannot be used in capture */
#ifdef CONFIG_STM32F7_TIM8_CAP
case STM32_TIM8_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM8EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM9_CAP
case STM32_TIM9_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM9EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM10_CAP
case STM32_TIM10_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM10EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM11_CAP
case STM32_TIM11_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM11EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM12_CAP
case STM32_TIM12_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM12EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM13_CAP
case STM32_TIM13_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM13EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM14_CAP
case STM32_TIM14_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM14EN;
break;
#endif
}
if (mask == 0)
{
return ERROR;
}
if (on)
{
modifyreg32(offset, 0, mask);
}
else
{
modifyreg32(offset, mask, 0);
}
return OK;
}
void tiva_adc_vref(uint8_t vref)
{
uintptr_t ctlreg = (TIVA_ADC0_BASE + TIVA_ADC_CTL_OFFSET);
modifyreg32(ctlreg, ADC_CTL_VREF_MASK, (vref & ADC_CTL_VREF_MASK));
}
void tiva_adc_sse_step_cfg(uint8_t adc, uint8_t sse, uint8_t chn, uint8_t cfg)
{
uintptr_t ssctlreg = (TIVA_ADC_BASE(adc) + TIVA_ADC_SSCTL(sse));
uint32_t ctlcfg = cfg << ADC_SSCTL_SHIFT(chn) & ADC_SSCTL_MASK(chn);
modifyreg32(ssctlreg, ADC_SSCTL_MASK(chn), ctlcfg);
}