static void msm_hsl_set_mctrl_irda(struct uart_port *port, unsigned int mctrl)
{
unsigned int vid = UART_TO_MSM(port)->ver_id;
unsigned int mr;
unsigned int loop_mode;
mr = msm_hsl_read(port, regmap[vid][UARTDM_MR1]);
if (!(mctrl & TIOCM_RTS)) {
mr &= ~UARTDM_MR1_RX_RDY_CTL_BMSK;
msm_hsl_write(port, mr, regmap[vid][UARTDM_MR1]);
msm_hsl_write(port, RFR_HIGH, regmap[vid][UARTDM_CR]);
} else {
mr |= UARTDM_MR1_RX_RDY_CTL_BMSK;
msm_hsl_write(port, mr, regmap[vid][UARTDM_MR1]);
}
loop_mode = TIOCM_LOOP & mctrl;
if (loop_mode) {
mr = msm_hsl_read(port, regmap[vid][UARTDM_MR2]);
mr |= UARTDM_MR2_LOOP_MODE_BMSK;
msm_hsl_write(port, mr, regmap[vid][UARTDM_MR2]);
/* Reset TX */
msm_hsl_reset(port);
/* Turn on Uart Receiver & Transmitter*/
msm_hsl_write(port, UARTDM_CR_RX_EN_BMSK
| UARTDM_CR_TX_EN_BMSK, regmap[vid][UARTDM_CR]);
}
}
static void msm_hsl_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
unsigned int mr;
unsigned int loop_mode;
clk_en(port, 1);
mr = msm_hsl_read(port, UARTDM_MR1_ADDR);
if (!(mctrl & TIOCM_RTS)) {
mr &= ~UARTDM_MR1_RX_RDY_CTL_BMSK;
msm_hsl_write(port, mr, UARTDM_MR1_ADDR);
msm_hsl_write(port, RFR_HIGH, UARTDM_CR_ADDR);
} else {
mr |= UARTDM_MR1_RX_RDY_CTL_BMSK;
msm_hsl_write(port, mr, UARTDM_MR1_ADDR);
}
loop_mode = TIOCM_LOOP & mctrl;
if (loop_mode) {
mr = msm_hsl_read(port, UARTDM_MR2_ADDR);
mr |= UARTDM_MR2_LOOP_MODE_BMSK;
msm_hsl_write(port, mr, UARTDM_MR2_ADDR);
/* Reset TX */
msm_hsl_reset(port);
/* Turn on Uart Receiver & Transmitter*/
msm_hsl_write(port, UARTDM_CR_RX_EN_BMSK
| UARTDM_CR_TX_EN_BMSK, UARTDM_CR_ADDR);
}
clk_en(port, 0);
}
static int msm_hsl_console_setup(struct console *co, char *options)
{
struct uart_port *port;
unsigned int vid;
int baud = 0, flow, bits, parity;
int ret;
pr_info("%s: ir\n", __func__);
if (unlikely(co->index >= UART_NR || co->index < 0))
return -ENXIO;
port = get_port_from_line(co->index);
vid = UART_TO_MSM(port)->ver_id;
pr_info("%s ():port->line %d, ir\n", __func__, port->line);
if (unlikely(!port->membase))
return -ENXIO;
port->cons = co;
pm_runtime_get_noresume(port->dev);
#ifndef CONFIG_PM_RUNTIME
msm_hsl_init_clock(port);
#endif
pm_runtime_resume(port->dev);
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
bits = 8;
parity = 'n';
flow = 'n';
msm_hsl_write(port, UARTDM_MR2_BITS_PER_CHAR_8 | STOP_BIT_ONE,
regmap[vid][UARTDM_MR2]);
if (baud < 300 || baud > 115200)
baud = 115200;
msm_hsl_set_baud_rate(port, baud);
pr_info("%s: cir port[%d] set baud=%d\n", __func__, port->line, baud);
ret = uart_set_options(port, co, baud, parity, bits, flow);
msm_hsl_reset(port);
msm_hsl_write(port, CR_PROTECTION_EN, regmap[vid][UARTDM_CR]);
msm_hsl_write(port, UARTDM_CR_TX_EN_BMSK, regmap[vid][UARTDM_CR]);
printk(KERN_INFO "msm_serial_hsl: console setup on port #%d\n",
port->line);
pr_info("%s ():port->line %d, ok, ir\n", __func__, port->line);
return ret;
}
static int __init msm_hsl_console_setup(struct console *co, char *options)
{
struct uart_port *port;
int baud, flow, bits, parity;
int ret;
if (unlikely(co->index >= UART_NR || co->index < 0))
return -ENXIO;
port = get_port_from_line(co->index);
if (unlikely(!port->membase))
return -ENXIO;
port->cons = co;
pm_runtime_get_noresume(port->dev);
#ifndef CONFIG_PM_RUNTIME
msm_hsl_init_clock(port);
#endif
pm_runtime_resume(port->dev);
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
bits = 8;
parity = 'n';
flow = 'n';
msm_hsl_write(port, UARTDM_MR2_BITS_PER_CHAR_8 | STOP_BIT_ONE,
UARTDM_MR2_ADDR); /* 8N1 */
if (baud < 300 || baud > 115200)
baud = 115200;
msm_hsl_set_baud_rate(port, baud);
ret = uart_set_options(port, co, baud, parity, bits, flow);
msm_hsl_reset(port);
/* Enable transmitter */
msm_hsl_write(port, CR_PROTECTION_EN, UARTDM_CR_ADDR);
msm_hsl_write(port, UARTDM_CR_TX_EN_BMSK, UARTDM_CR_ADDR);
printk(KERN_INFO "msm_serial_hsl: console setup on port #%d\n",
port->line);
console_uart_port = port;
b_terminal_onoff = 0;
return ret;
}
static void msm_hsl_set_mctrl_cir(struct uart_port *port, unsigned int mctrl)
{
unsigned int vid = UART_TO_MSM(port)->ver_id;
unsigned int mr;
unsigned int loop_mode;
clk_en(port, 1);
mr = msm_hsl_read(port, regmap[vid][UARTDM_MR1]);
if (!(mctrl & TIOCM_RTS)) {
pr_info("%s ()mctrl & TIOCM_RTS:port->line %d, ir\n", __func__, port->line);
mr &= ~UARTDM_MR1_RX_RDY_CTL_BMSK;
msm_hsl_write(port, mr, regmap[vid][UARTDM_MR1]);
msm_hsl_write(port, RFR_HIGH, regmap[vid][UARTDM_CR]);
} else {
mr |= UARTDM_MR1_RX_RDY_CTL_BMSK;
msm_hsl_write(port, mr, regmap[vid][UARTDM_MR1]);
pr_info("%s () TIOCM_RTS:port->line %d, ir\n", __func__, port->line);
}
loop_mode = TIOCM_LOOP & mctrl;
if (loop_mode) {
pr_info("%s ()loop_mode:port->line %d, ir\n", __func__, port->line);
mr = msm_hsl_read(port, regmap[vid][UARTDM_MR2]);
mr |= UARTDM_MR2_LOOP_MODE_BMSK;
msm_hsl_write(port, mr, regmap[vid][UARTDM_MR2]);
msm_hsl_reset(port);
msm_hsl_write(port, UARTDM_CR_RX_EN_BMSK
| UARTDM_CR_TX_EN_BMSK, regmap[vid][UARTDM_CR]);
}
clk_en(port, 0);
}
static void msm_hsl_set_baud_rate(struct uart_port *port, unsigned int baud)
{
unsigned int baud_code, rxstale, watermark;
unsigned int data;
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
switch (baud) {
#ifdef CONFIG_LGE_FELICA
case 300:
baud_code = UARTDM_CSR_75;
rxstale = 1;
break;
case 600:
baud_code = UARTDM_CSR_150;
rxstale = 1;
break;
case 1200:
baud_code = UARTDM_CSR_300;
rxstale = 1;
break;
case 2400:
baud_code = UARTDM_CSR_600;
rxstale = 1;
break;
case 4800:
baud_code = UARTDM_CSR_1200;
rxstale = 1;
break;
case 9600:
baud_code = UARTDM_CSR_2400;
rxstale = 2;
break;
case 14400:
baud_code = UARTDM_CSR_3600;
rxstale = 3;
break;
case 19200:
baud_code = UARTDM_CSR_4800;
rxstale = 4;
break;
case 28800:
baud_code = UARTDM_CSR_7200;
rxstale = 6;
break;
case 38400:
baud_code = UARTDM_CSR_9600;
rxstale = 8;
break;
case 57600:
baud_code = UARTDM_CSR_14400;
rxstale = 16;
break;
case 230400:
baud_code = 0xee;
rxstale = 31;
break;
case 460800:
baud_code = 0xff;
rxstale = 31;
break;
case 115200:
default:
baud_code = UARTDM_CSR_28800;
rxstale = 31;
break;
#else
case 300:
baud_code = UARTDM_CSR_75;
rxstale = 1;
break;
case 600:
baud_code = UARTDM_CSR_150;
rxstale = 1;
break;
case 1200:
baud_code = UARTDM_CSR_300;
rxstale = 1;
break;
case 2400:
baud_code = UARTDM_CSR_600;
rxstale = 1;
break;
case 4800:
baud_code = UARTDM_CSR_1200;
rxstale = 1;
break;
case 9600:
baud_code = UARTDM_CSR_2400;
rxstale = 2;
break;
case 14400:
baud_code = UARTDM_CSR_3600;
rxstale = 3;
break;
case 19200:
baud_code = UARTDM_CSR_4800;
rxstale = 4;
break;
case 28800:
baud_code = UARTDM_CSR_7200;
rxstale = 6;
break;
case 38400:
baud_code = UARTDM_CSR_9600;
rxstale = 8;
break;
case 57600:
baud_code = UARTDM_CSR_14400;
rxstale = 16;
break;
case 115200:
baud_code = UARTDM_CSR_28800;
rxstale = 31;
break;
case 230400:
baud_code = UARTDM_CSR_57600;
rxstale = 31;
break;
case 460800:
baud_code = UARTDM_CSR_115200;
rxstale = 31;
break;
default: /* 115200 baud rate */
baud_code = UARTDM_CSR_28800;
rxstale = 31;
break;
#endif
}
msm_hsl_write(port, baud_code, UARTDM_CSR_ADDR);
/* RX stale watermark */
watermark = UARTDM_IPR_STALE_LSB_BMSK & rxstale;
watermark |= UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK & (rxstale << 2);
msm_hsl_write(port, watermark, UARTDM_IPR_ADDR);
/* set RX watermark
* Configure Rx Watermark as 3/4 size of Rx FIFO.
* RFWR register takes value in Words for UARTDM Core
* whereas it is consider to be in Bytes for UART Core.
* Hence configuring Rx Watermark as 12 Words.
*/
watermark = (port->fifosize * 3) / (4 * 4);
msm_hsl_write(port, watermark, UARTDM_RFWR_ADDR);
/* set TX watermark */
msm_hsl_write(port, 0, UARTDM_TFWR_ADDR);
msm_hsl_write(port, CR_PROTECTION_EN, UARTDM_CR_ADDR);
msm_hsl_reset(port);
data = UARTDM_CR_TX_EN_BMSK;
data |= UARTDM_CR_RX_EN_BMSK;
/* enable TX & RX */
msm_hsl_write(port, data, UARTDM_CR_ADDR);
msm_hsl_write(port, RESET_STALE_INT, UARTDM_CR_ADDR);
/* turn on RX and CTS interrupts */
msm_hsl_port->imr = UARTDM_ISR_RXSTALE_BMSK
| UARTDM_ISR_DELTA_CTS_BMSK | UARTDM_ISR_RXLEV_BMSK;
msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
msm_hsl_write(port, 6500, UARTDM_DMRX_ADDR);
msm_hsl_write(port, STALE_EVENT_ENABLE, UARTDM_CR_ADDR);
}
static int msm_hsl_startup(struct uart_port *port)
{
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
unsigned int data, rfr_level;
int ret;
unsigned long flags;
snprintf(msm_hsl_port->name, sizeof(msm_hsl_port->name),
"msm_serial_hsl%d", port->line);
#ifndef CONFIG_PM_RUNTIME
msm_hsl_init_clock(port);
#endif
pm_runtime_get_sync(port->dev);
if (likely(port->fifosize > 12))
rfr_level = port->fifosize - 12;
else
rfr_level = port->fifosize;
spin_lock_irqsave(&port->lock, flags);
/* set automatic RFR level */
data = msm_hsl_read(port, UARTDM_MR1_ADDR);
data &= ~UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK;
data &= ~UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK;
data |= UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK & (rfr_level << 2);
data |= UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK & rfr_level;
msm_hsl_write(port, data, UARTDM_MR1_ADDR);
/* Make sure IPR is not 0 to start with*/
msm_hsl_write(port, UARTDM_IPR_STALE_LSB_BMSK, UARTDM_IPR_ADDR);
data = 0;
if (!(is_console(port)) || (!port->cons) ||
(port->cons && (!(port->cons->flags & CON_ENABLED)))) {
msm_hsl_write(port, CR_PROTECTION_EN, UARTDM_CR_ADDR);
msm_hsl_write(port, UARTDM_MR2_BITS_PER_CHAR_8 | STOP_BIT_ONE,
UARTDM_MR2_ADDR); /* 8N1 */
msm_hsl_reset(port);
data = UARTDM_CR_TX_EN_BMSK;
}
if(b_terminal_onoff == 0 && console_uart_port && (port == console_uart_port)){
msm_hsl_write(port, data, UARTDM_CR_ADDR); /* enable TX */
}else{
data |= UARTDM_CR_RX_EN_BMSK;
msm_hsl_write(port, data, UARTDM_CR_ADDR); /* enable TX & RX */
}
/* turn on RX and CTS interrupts */
msm_hsl_port->imr = UARTDM_ISR_RXSTALE_BMSK
| UARTDM_ISR_DELTA_CTS_BMSK | UARTDM_ISR_RXLEV_BMSK;
spin_unlock_irqrestore(&port->lock, flags);
ret = request_irq(port->irq, msm_hsl_irq, IRQF_TRIGGER_HIGH,
msm_hsl_port->name, port);
if (unlikely(ret)) {
printk(KERN_ERR "%s: failed to request_irq\n", __func__);
return ret;
}
spin_lock_irqsave(&port->lock, flags);
msm_hsl_write(port, RESET_STALE_INT, UARTDM_CR_ADDR);
msm_hsl_write(port, 6500, UARTDM_DMRX_ADDR);
msm_hsl_write(port, STALE_EVENT_ENABLE, UARTDM_CR_ADDR);
msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
spin_unlock_irqrestore(&port->lock, flags);
return 0;
}
static int msm_hsl_startup(struct uart_port *port)
{
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
struct platform_device *pdev = to_platform_device(port->dev);
struct msm_serial_hslite_platform_data *pdata = pdev->dev.platform_data;
unsigned int data, rfr_level;
int ret;
unsigned long flags;
snprintf(msm_hsl_port->name, sizeof(msm_hsl_port->name),
"msm_serial_hsl%d", port->line);
if (!(is_console(port)) || (!port->cons) ||
(port->cons && (!(port->cons->flags & CON_ENABLED)))) {
if (msm_serial_hsl_has_gsbi())
if ((ioread32(msm_hsl_port->mapped_gsbi +
GSBI_CONTROL_ADDR) & GSBI_PROTOCOL_I2C_UART)
!= GSBI_PROTOCOL_I2C_UART)
iowrite32(GSBI_PROTOCOL_I2C_UART,
msm_hsl_port->mapped_gsbi +
GSBI_CONTROL_ADDR);
if (pdata && pdata->config_gpio) {
ret = gpio_request(pdata->uart_tx_gpio,
"UART_TX_GPIO");
if (unlikely(ret)) {
pr_err("%s: gpio request failed for:%d\n",
__func__, pdata->uart_tx_gpio);
return ret;
}
ret = gpio_request(pdata->uart_rx_gpio, "UART_RX_GPIO");
if (unlikely(ret)) {
pr_err("%s: gpio request failed for:%d\n",
__func__, pdata->uart_rx_gpio);
gpio_free(pdata->uart_tx_gpio);
return ret;
}
}
}
#ifndef CONFIG_PM_RUNTIME
msm_hsl_init_clock(port);
#endif
pm_runtime_get_sync(port->dev);
if (likely(port->fifosize > 12))
rfr_level = port->fifosize - 12;
else
rfr_level = port->fifosize;
spin_lock_irqsave(&port->lock, flags);
/* set automatic RFR level */
data = msm_hsl_read(port, UARTDM_MR1_ADDR);
data &= ~UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK;
data &= ~UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK;
data |= UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK & (rfr_level << 2);
data |= UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK & rfr_level;
msm_hsl_write(port, data, UARTDM_MR1_ADDR);
/* Make sure IPR is not 0 to start with*/
msm_hsl_write(port, UARTDM_IPR_STALE_LSB_BMSK, UARTDM_IPR_ADDR);
data = 0;
if (!(is_console(port)) || (!port->cons) ||
(port->cons && (!(port->cons->flags & CON_ENABLED)))) {
msm_hsl_write(port, CR_PROTECTION_EN, UARTDM_CR_ADDR);
msm_hsl_write(port, UARTDM_MR2_BITS_PER_CHAR_8 | STOP_BIT_ONE,
UARTDM_MR2_ADDR); /* 8N1 */
msm_hsl_reset(port);
data = UARTDM_CR_TX_EN_BMSK;
}
data |= UARTDM_CR_RX_EN_BMSK;
msm_hsl_write(port, data, UARTDM_CR_ADDR); /* enable TX & RX */
/* turn on RX and CTS interrupts */
msm_hsl_port->imr = UARTDM_ISR_RXSTALE_BMSK
| UARTDM_ISR_DELTA_CTS_BMSK | UARTDM_ISR_RXLEV_BMSK;
spin_unlock_irqrestore(&port->lock, flags);
ret = request_irq(port->irq, msm_hsl_irq, IRQF_TRIGGER_HIGH,
msm_hsl_port->name, port);
if (unlikely(ret)) {
printk(KERN_ERR "%s: failed to request_irq\n", __func__);
return ret;
}
spin_lock_irqsave(&port->lock, flags);
msm_hsl_write(port, RESET_STALE_INT, UARTDM_CR_ADDR);
msm_hsl_write(port, 6500, UARTDM_DMRX_ADDR);
msm_hsl_write(port, STALE_EVENT_ENABLE, UARTDM_CR_ADDR);
msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
spin_unlock_irqrestore(&port->lock, flags);
return 0;
}
static void msm_hsl_set_baud_rate(struct uart_port *port, unsigned int baud)
{
unsigned int baud_code, rxstale, watermark;
unsigned int data;
unsigned int vid;
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
if (port->line == 2) {
/*D("%s: irda baud is %d,\n", __func__, baud);*/
if (force_baud_1 == 96)
baud = 9600;
else if (force_baud_1 == 1152)
baud = 115200;
/*D("%s: irda change_baud is %d,\n", __func__, baud);*/
}
D("%s ()baud %d:port->line %d, ir\n", __func__, baud, port->line);
switch (baud) {
case 300:
baud_code = UARTDM_CSR_75;
rxstale = 1;
break;
case 600:
baud_code = UARTDM_CSR_150;
rxstale = 1;
break;
case 1200:
baud_code = UARTDM_CSR_300;
rxstale = 1;
break;
case 2400:
baud_code = UARTDM_CSR_600;
rxstale = 1;
break;
case 4800:
baud_code = UARTDM_CSR_1200;
rxstale = 1;
break;
case 9600:
baud_code = UARTDM_CSR_2400;
rxstale = 2;
break;
case 14400:
baud_code = UARTDM_CSR_3600;
rxstale = 3;
break;
case 19200:
baud_code = UARTDM_CSR_4800;
rxstale = 4;
break;
case 28800:
baud_code = UARTDM_CSR_7200;
rxstale = 6;
break;
case 38400:
baud_code = UARTDM_CSR_9600;
rxstale = 8;
break;
case 57600:
baud_code = UARTDM_CSR_14400;
rxstale = 16;
break;
case 115200:
baud_code = UARTDM_CSR_28800;
rxstale = 31;
break;
case 230400:
baud_code = UARTDM_CSR_57600;
rxstale = 31;
break;
case 460800:
baud_code = UARTDM_CSR_115200;
rxstale = 31;
break;
default: /* 115200 baud rate */
baud_code = UARTDM_CSR_28800;
rxstale = 31;
break;
}
vid = msm_hsl_port->ver_id;
msm_hsl_write(port, baud_code, regmap[vid][UARTDM_CSR]);
//if (vid == UARTDM_VERSION_14)
//rxstale = 5000;
/* RX stale watermark */
watermark = UARTDM_IPR_STALE_LSB_BMSK & rxstale;
watermark |= UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK & (rxstale << 2);
msm_hsl_write(port, watermark, regmap[vid][UARTDM_IPR]);
/* Set RX watermark
* Configure Rx Watermark as 3/4 size of Rx FIFO.
* RFWR register takes value in Words for UARTDM Core
* whereas it is consider to be in Bytes for UART Core.
* Hence configuring Rx Watermark as 12 Words.
*/
watermark = (port->fifosize * 3) / (4*4);
msm_hsl_write(port, watermark, regmap[vid][UARTDM_RFWR]);
/* set TX watermark */
msm_hsl_write(port, 0, regmap[vid][UARTDM_TFWR]);
msm_hsl_write(port, CR_PROTECTION_EN, regmap[vid][UARTDM_CR]);
msm_hsl_reset(port);
data = UARTDM_CR_TX_EN_BMSK;
data |= UARTDM_CR_RX_EN_BMSK;
/* enable TX & RX */
msm_hsl_write(port, data, regmap[vid][UARTDM_CR]);
msm_hsl_write(port, RESET_STALE_INT, regmap[vid][UARTDM_CR]);
/* turn on RX and CTS interrupts */
msm_hsl_port->imr = UARTDM_ISR_RXSTALE_BMSK
| UARTDM_ISR_DELTA_CTS_BMSK | UARTDM_ISR_RXLEV_BMSK;
msm_hsl_write(port, msm_hsl_port->imr, regmap[vid][UARTDM_IMR]);
msm_hsl_write(port, 6500, regmap[vid][UARTDM_DMRX]);
msm_hsl_write(port, STALE_EVENT_ENABLE, regmap[vid][UARTDM_CR]);
}
static void msm_hsl_set_baud_rate(struct uart_port *port, unsigned int baud)
{
unsigned int baud_code, rxstale, watermark;
unsigned int data;
unsigned int vid;
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
if (port->line == 2) {
if (force_baud_1 == 96)
baud = 9600;
else if (force_baud_1 == 1152)
baud = 115200;
}
D("%s ()baud %d:port->line %d, ir\n", __func__, baud, port->line);
switch (baud) {
case 300:
baud_code = UARTDM_CSR_75;
rxstale = 1;
break;
case 600:
baud_code = UARTDM_CSR_150;
rxstale = 1;
break;
case 1200:
baud_code = UARTDM_CSR_300;
rxstale = 1;
break;
case 2400:
baud_code = UARTDM_CSR_600;
rxstale = 1;
break;
case 4800:
baud_code = UARTDM_CSR_1200;
rxstale = 1;
break;
case 9600:
baud_code = UARTDM_CSR_2400;
rxstale = 2;
break;
case 14400:
baud_code = UARTDM_CSR_3600;
rxstale = 3;
break;
case 19200:
baud_code = UARTDM_CSR_4800;
rxstale = 4;
break;
case 28800:
baud_code = UARTDM_CSR_7200;
rxstale = 6;
break;
case 38400:
baud_code = UARTDM_CSR_9600;
rxstale = 8;
break;
case 57600:
baud_code = UARTDM_CSR_14400;
rxstale = 16;
break;
case 115200:
baud_code = UARTDM_CSR_28800;
rxstale = 31;
break;
case 230400:
baud_code = UARTDM_CSR_57600;
rxstale = 31;
break;
case 460800:
baud_code = UARTDM_CSR_115200;
rxstale = 31;
break;
default:
baud_code = UARTDM_CSR_28800;
rxstale = 31;
break;
}
vid = msm_hsl_port->ver_id;
msm_hsl_write(port, baud_code, regmap[vid][UARTDM_CSR]);
watermark = UARTDM_IPR_STALE_LSB_BMSK & rxstale;
watermark |= UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK & (rxstale << 2);
msm_hsl_write(port, watermark, regmap[vid][UARTDM_IPR]);
watermark = (port->fifosize * 3) / (4*4);
msm_hsl_write(port, watermark, regmap[vid][UARTDM_RFWR]);
msm_hsl_write(port, 0, regmap[vid][UARTDM_TFWR]);
msm_hsl_write(port, CR_PROTECTION_EN, regmap[vid][UARTDM_CR]);
msm_hsl_reset(port);
data = UARTDM_CR_TX_EN_BMSK;
data |= UARTDM_CR_RX_EN_BMSK;
msm_hsl_write(port, data, regmap[vid][UARTDM_CR]);
msm_hsl_write(port, RESET_STALE_INT, regmap[vid][UARTDM_CR]);
msm_hsl_port->imr = UARTDM_ISR_RXSTALE_BMSK
| UARTDM_ISR_DELTA_CTS_BMSK | UARTDM_ISR_RXLEV_BMSK;
msm_hsl_write(port, msm_hsl_port->imr, regmap[vid][UARTDM_IMR]);
msm_hsl_write(port, 6500, regmap[vid][UARTDM_DMRX]);
msm_hsl_write(port, STALE_EVENT_ENABLE, regmap[vid][UARTDM_CR]);
}