static int
fm801_pci_probe( device_t dev )
{
int id;
if ((id = pci_get_devid(dev)) == PCI_DEVICE_FORTEMEDIA1 ) {
device_set_desc(dev, "Forte Media FM801 Audio Controller");
return BUS_PROBE_DEFAULT;
}
/*
if ((id = pci_get_devid(dev)) == PCI_DEVICE_FORTEMEDIA2 ) {
device_set_desc(dev, "Forte Media FM801 Joystick (Not Supported)");
return ENXIO;
}
*/
return ENXIO;
}
static int
intsmb_probe(device_t dev)
{
const struct intsmb_device *isd;
uint32_t devid;
size_t i;
devid = pci_get_devid(dev);
for (i = 0; i < nitems(intsmb_products); i++) {
isd = &intsmb_products[i];
if (isd->devid == devid) {
device_set_desc(dev, isd->description);
return (BUS_PROBE_DEFAULT);
}
}
return (ENXIO);
}
static int
isci_probe (device_t device)
{
u_int32_t type = pci_get_devid(device);
struct _pcsid *ep = pci_ids;
while (ep->type && ep->type != type)
++ep;
if (ep->desc)
{
device_set_desc(device, ep->desc);
return (BUS_PROBE_DEFAULT);
}
else
return (ENXIO);
}
static int
xrpu_probe(device_t self)
{
char *desc;
desc = NULL;
switch (pci_get_devid(self)) {
case 0x6216133e:
desc = "VCC Hotworks-I xc6216";
break;
}
if (desc == NULL)
return ENXIO;
device_set_desc(self, desc);
return 0;
}
static int
ntb_attach(device_t device)
{
struct ntb_softc *ntb;
struct ntb_hw_info *p;
int error;
ntb = DEVICE2SOFTC(device);
p = ntb_get_device_info(pci_get_devid(device));
ntb->device = device;
ntb->type = p->type;
ntb->features = p->features;
/* Heartbeat timer for NTB_SOC since there is no link interrupt */
callout_init(&ntb->heartbeat_timer, 1);
callout_init(&ntb->lr_timer, 1);
if (ntb->type == NTB_SOC)
error = ntb_detect_soc(ntb);
else
error = ntb_detect_xeon(ntb);
if (error)
goto out;
error = ntb_map_pci_bars(ntb);
if (error)
goto out;
if (ntb->type == NTB_SOC)
error = ntb_setup_soc(ntb);
else
error = ntb_setup_xeon(ntb);
if (error)
goto out;
error = ntb_setup_interrupts(ntb);
if (error)
goto out;
pci_enable_busmaster(ntb->device);
out:
if (error != 0)
ntb_detach(device);
return (error);
}
static struct ida_board *
ida_pci_match(device_t dev)
{
int i;
u_int32_t id, sub_id;
id = pci_get_devid(dev);
sub_id = pci_get_subdevice(dev) << 16 | pci_get_subvendor(dev);
if (id == IDA_DEVICEID_SMART ||
id == IDA_DEVICEID_DEC_SMART ||
id == IDA_DEVICEID_NCR_53C1510) {
for (i = 0; board_id[i].board; i++)
if (board_id[i].board == sub_id)
return (&board_id[i]);
}
return (NULL);
}
static int
piix_probe (device_t dev)
{
u_int32_t d;
switch (pci_get_devid(dev)) {
case 0x71138086:
d = pci_read_config(dev, 0x4, 2);
if (!(d & 1))
return 0; /* IO space not mapped */
d = pci_read_config(dev, 0x40, 4);
piix_timecounter_address = (d & 0xffc0) + 8;
piix_timecounter.tc_frequency = piix_freq;
init_timecounter(&piix_timecounter);
return (ENXIO);
};
return (ENXIO);
}
static int
fwohci_pci_init(device_t self)
{
int olatency, latency, ocache_line, cache_line;
uint16_t cmd;
cmd = pci_read_config(self, PCIR_COMMAND, 2);
cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MWRICEN;
#if 1 /* for broken hardware */
cmd &= ~PCIM_CMD_MWRICEN;
#endif
pci_write_config(self, PCIR_COMMAND, cmd, 2);
/*
* Some Sun PCIO-2 FireWire controllers have their intpin register
* bogusly set to 0, although it should be 3. Correct that.
*/
if (pci_get_devid(self) == (FW_VENDORID_SUN | FW_DEVICE_PCIO2FW) &&
pci_get_intpin(self) == 0)
pci_set_intpin(self, 3);
latency = olatency = pci_read_config(self, PCIR_LATTIMER, 1);
#define DEF_LATENCY 0x20
if (olatency < DEF_LATENCY) {
latency = DEF_LATENCY;
pci_write_config(self, PCIR_LATTIMER, latency, 1);
}
cache_line = ocache_line = pci_read_config(self, PCIR_CACHELNSZ, 1);
#define DEF_CACHE_LINE 8
if (ocache_line < DEF_CACHE_LINE) {
cache_line = DEF_CACHE_LINE;
pci_write_config(self, PCIR_CACHELNSZ, cache_line, 1);
}
if (firewire_debug) {
device_printf(self, "latency timer %d -> %d.\n",
olatency, latency);
device_printf(self, "cache size %d -> %d.\n",
ocache_line, cache_line);
}
return 0;
}
static int
intsmb_probe(device_t dev)
{
switch (pci_get_devid(dev)) {
case 0x71138086: /* Intel 82371AB */
case 0x719b8086: /* Intel 82443MX */
#if 0
/* Not a good idea yet, this stops isab0 functioning */
case 0x02001166: /* ServerWorks OSB4 */
#endif
device_set_desc(dev, "Intel PIIX4 SMBUS Interface");
break;
default:
return (ENXIO);
}
return (BUS_PROBE_DEFAULT);
}
static const char *
ohci_pci_match(device_t self)
{
u_int32_t device_id = pci_get_devid(self);
switch (device_id) {
case PCI_OHCI_DEVICEID_ALADDIN_V:
return (ohci_device_aladdin_v);
case PCI_OHCI_DEVICEID_AMD756:
return (ohci_device_amd756);
case PCI_OHCI_DEVICEID_AMD766:
return (ohci_device_amd766);
case PCI_OHCI_DEVICEID_CS5536:
return (ohci_device_cs5536);
case PCI_OHCI_DEVICEID_SB400_1:
case PCI_OHCI_DEVICEID_SB400_2:
return (ohci_device_sb400);
case PCI_OHCI_DEVICEID_USB0670:
return (ohci_device_usb0670);
case PCI_OHCI_DEVICEID_USB0673:
return (ohci_device_usb0673);
case PCI_OHCI_DEVICEID_FIRELINK:
return (ohci_device_firelink);
case PCI_OHCI_DEVICEID_NEC:
return (ohci_device_nec);
case PCI_OHCI_DEVICEID_NFORCE3:
return (ohci_device_nforce3);
case PCI_OHCI_DEVICEID_SIS5571:
return (ohci_device_sis5571);
case PCI_OHCI_DEVICEID_KEYLARGO:
return (ohci_device_keylargo);
case PCI_OHCI_DEVICEID_PCIO2USB:
return (ohci_device_pcio2usb);
default:
if (pci_get_class(self) == PCIC_SERIALBUS
&& pci_get_subclass(self) == PCIS_SERIALBUS_USB
&& pci_get_progif(self) == PCI_INTERFACE_OHCI) {
return (ohci_device_generic);
}
}
return NULL; /* dunno */
}
static void
ofw_pcib_setup_device(device_t bus, device_t child)
{
int i;
uint16_t reg;
switch (pci_get_vendor(bus)) {
/*
* For PLX PEX 8532 issue 64 TLPs to the child from the downstream
* port to the child device in order to work around a hardware bug.
*/
case PCI_VENDOR_PLX:
for (i = 0, reg = 0; i < 64; i++)
reg |= pci_get_devid(child);
break;
}
OFW_PCI_SETUP_DEVICE(device_get_parent(bus), child);
}
static int
si_pci_probe(device_t dev)
{
const char *desc = NULL;
switch (pci_get_devid(dev)) {
case 0x400011cb:
desc = "Specialix SI/XIO PCI host card";
break;
case 0x200011cb:
if (pci_read_config(dev, SIJETSSIDREG, 4) == 0x020011cb)
desc = "Specialix SX PCI host card";
break;
}
if (desc) {
device_set_desc(dev, desc);
return 0;
}
return ENXIO;
}
/*
* Cypress chipset support functions
*/
static int
ata_cypress_probe(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(dev);
/*
* the Cypress chip is a mess, it contains two ATA functions, but
* both channels are visible on the first one.
* simply ignore the second function for now, as the right
* solution (ignoring the second channel on the first function)
* doesn't work with the crappy ATA interrupt setup on the alpha.
*/
if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
pci_get_function(dev) == 1 &&
pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
device_set_desc(dev, "Cypress 82C693 ATA controller");
ctlr->chipinit = ata_cypress_chipinit;
return (BUS_PROBE_LOW_PRIORITY);
}
return ENXIO;
}
static int
ed_pci_attach(device_t dev)
{
struct ed_softc *sc = device_get_softc(dev);
int error = ENXIO;
/*
* Probe RTL8029 cards, but allow failure and try as a generic
* ne-2000. QEMU 0.9 and earlier use the RTL8029 PCI ID, but
* are areally just generic ne-2000 cards.
*/
if (pci_get_devid(dev) == ED_RTL8029_PCI_ID)
error = ed_probe_RTL80x9(dev, PCIR_BAR(0), 0);
if (error)
error = ed_probe_Novell(dev, PCIR_BAR(0),
ED_FLAGS_FORCE_16BIT_MODE);
if (error) {
ed_release_resources(dev);
return (error);
}
ed_Novell_read_mac(sc);
error = ed_alloc_irq(dev, 0, RF_SHAREABLE);
if (error) {
ed_release_resources(dev);
return (error);
}
if (sc->sc_media_ioctl == NULL)
ed_gen_ifmedia_init(sc);
error = ed_attach(dev);
if (error) {
ed_release_resources(dev);
return (error);
}
error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE,
NULL, edintr, sc, &sc->irq_handle);
if (error)
ed_release_resources(dev);
return (error);
}
static int
piix_probe(device_t dev)
{
u_int32_t d;
if (devclass_get_device(devclass_find("acpi"), 0) != NULL)
return (ENXIO);
switch (pci_get_devid(dev)) {
case 0x71138086:
device_set_desc(dev, "PIIX Timecounter");
break;
default:
return (ENXIO);
}
d = pci_read_config(dev, PCIR_COMMAND, 2);
if (!(d & PCIM_CMD_PORTEN)) {
device_printf(dev, "PIIX I/O space not mapped\n");
return (ENXIO);
}
return (0);
}
static int
ismt_probe(device_t dev)
{
const char *desc;
switch (pci_get_devid(dev)) {
case ID_INTEL_S1200_SMT0:
desc = "Atom Processor S1200 SMBus 2.0 Controller 0";
break;
case ID_INTEL_S1200_SMT1:
desc = "Atom Processor S1200 SMBus 2.0 Controller 1";
break;
case ID_INTEL_C2000_SMT:
desc = "Atom Processor C2000 SMBus 2.0";
break;
default:
return (ENXIO);
}
device_set_desc(dev, desc);
return (BUS_PROBE_DEFAULT);
}
static boolean_t
ioat_model_resets_msix(struct ioat_softc *ioat)
{
u_int32_t pciid;
pciid = pci_get_devid(ioat->device);
switch (pciid) {
/* BWD: */
case 0x0c508086:
case 0x0c518086:
case 0x0c528086:
case 0x0c538086:
/* BDXDE: */
case 0x6f508086:
case 0x6f518086:
case 0x6f528086:
case 0x6f538086:
return (TRUE);
}
return (FALSE);
}
static int
intsmb_probe(device_t dev)
{
switch (pci_get_devid(dev)) {
case 0x71138086: /* Intel 82371AB */
case 0x719b8086: /* Intel 82443MX */
#if 0
/* Not a good idea yet, this stops isab0 functioning */
case 0x02001166: /* ServerWorks OSB4 */
#endif
device_set_desc(dev, "Intel PIIX4 SMBUS Interface");
break;
case 0x43851002:
device_set_desc(dev, "AMD SB600/700/710/750 SMBus Controller");
/* XXX Maybe force polling right here? */
break;
default:
return (ENXIO);
}
return (BUS_PROBE_DEFAULT);
}
static int
ntb_attach(device_t device)
{
struct ntb_softc *ntb = DEVICE2SOFTC(device);
struct ntb_hw_info *p = ntb_get_device_info(pci_get_devid(device));
int error;
ntb->device = device;
ntb->type = p->type;
ntb->features = p->features;
/* Heartbeat timer for NTB_SOC since there is no link interrupt */
callout_init(&ntb->heartbeat_timer, CALLOUT_MPSAFE);
callout_init(&ntb->lr_timer, CALLOUT_MPSAFE);
DETACH_ON_ERROR(ntb_map_pci_bars(ntb));
DETACH_ON_ERROR(ntb_initialize_hw(ntb));
DETACH_ON_ERROR(ntb_setup_interrupts(ntb));
pci_enable_busmaster(ntb->device);
return (error);
}
static int
ichsmb_pci_probe(device_t dev)
{
/* Check PCI identifier */
switch (pci_get_devid(dev)) {
case ID_82801AA:
device_set_desc(dev, "Intel 82801AA (ICH) SMBus controller");
break;
case ID_82801AB:
device_set_desc(dev, "Intel 82801AB (ICH0) SMBus controller");
break;
case ID_82801BA:
device_set_desc(dev, "Intel 82801BA (ICH2) SMBus controller");
break;
case ID_82801CA:
device_set_desc(dev, "Intel 82801CA (ICH3) SMBus controller");
break;
case ID_82801DC:
device_set_desc(dev, "Intel 82801DC (ICH4) SMBus controller");
break;
case ID_82801EB:
device_set_desc(dev, "Intel 82801EB (ICH5) SMBus controller");
break;
default:
if (pci_get_class(dev) == PCIC_SERIALBUS
&& pci_get_subclass(dev) == PCIS_SERIALBUS_SMBUS
&& pci_get_progif(dev) == PCIS_SERIALBUS_SMBUS_PROGIF) {
device_set_desc(dev, "SMBus controller");
return (-2); /* XXX */
}
return (ENXIO);
}
/* Done */
return (ichsmb_probe(dev));
}
const struct ata_chip_id *
ata_find_chip(device_t dev, const struct ata_chip_id *index, int slot)
{
device_t *children;
int nchildren, i;
if (device_get_children(device_get_parent(dev), &children, &nchildren))
return NULL;
while (index->chipid != 0) {
for (i = 0; i < nchildren; i++) {
if (((slot >= 0 && pci_get_slot(children[i]) == slot) ||
(slot < 0 && pci_get_slot(children[i]) <= -slot)) &&
pci_get_devid(children[i]) == index->chipid &&
pci_get_revid(children[i]) >= index->chiprev) {
kfree(children, M_TEMP);
return index;
}
}
index++;
}
kfree(children, M_TEMP);
return NULL;
}
static int
ofw_pcib_attach(device_t dev)
{
struct ofw_pcib_gen_softc *sc;
sc = device_get_softc(dev);
switch (pci_get_devid(dev)) {
/*
* The ALi M5249 found in Fire-based machines by definition must me
* subtractive as they have a ISA bridge on their secondary side but
* don't indicate this in the class code although the ISA I/O range
* isn't included in their bridge decode.
*/
case PCI_DEVID_ALI_M5249:
sc->ops_pcib_sc.flags |= PCIB_SUBTRACTIVE;
break;
}
switch (pci_get_vendor(dev)) {
/*
* Concurrently write the primary and secondary bus numbers in order
* to work around a bug in PLX PEX 8114 causing the internal shadow
* copies of these not to be updated when setting them bytewise.
*/
case PCI_VENDOR_PLX:
pci_write_config(dev, PCIR_PRIBUS_1,
pci_read_config(dev, PCIR_SECBUS_1, 1) << 8 |
pci_read_config(dev, PCIR_PRIBUS_1, 1), 2);
break;
}
ofw_pcib_gen_setup(dev);
pcib_attach_common(dev);
return (pcib_attach_child(dev));
}
static const char *
xhci_pci_match(device_t self)
{
uint32_t device_id = pci_get_devid(self);
switch (device_id) {
case 0x70231b6f:
return ("Etron EJ168 USB 3.0 Host Controller");
case 0x01941033:
return ("NEC uPD720200 USB 3.0 controller");
case 0x1e318086:
return ("Intel Panther Point USB 3.0 controller");
case 0x8c318086:
return ("Intel Lynx Point USB 3.0 controller");
default:
break;
}
if ((pci_get_class(self) == PCIC_SERIALBUS)
&& (pci_get_subclass(self) == PCIS_SERIALBUS_USB)
&& (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) {
return ("XHCI (generic) USB 3.0 controller");
}
return (NULL); /* dunno */
}
static int
ehci_pci_attach(device_t self)
{
ehci_softc_t *sc = device_get_softc(self);
int err;
int rid;
/* initialise some bus fields */
sc->sc_bus.parent = self;
sc->sc_bus.devices = sc->sc_devices;
sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
/* get all DMA memory */
if (usb_bus_mem_alloc_all(&sc->sc_bus,
USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) {
return (ENOMEM);
}
pci_enable_busmaster(self);
switch (pci_read_config(self, PCI_USBREV, 1) & PCI_USB_REV_MASK) {
case PCI_USB_REV_PRE_1_0:
case PCI_USB_REV_1_0:
case PCI_USB_REV_1_1:
/*
* NOTE: some EHCI USB controllers have the wrong USB
* revision number. It appears those controllers are
* fully compliant so we just ignore this value in
* some common cases.
*/
device_printf(self, "pre-2.0 USB revision (ignored)\n");
/* fallthrough */
case PCI_USB_REV_2_0:
break;
default:
/* Quirk for Parallels Desktop 4.0 */
device_printf(self, "USB revision is unknown. Assuming v2.0.\n");
break;
}
rid = PCI_CBMEM;
sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (!sc->sc_io_res) {
device_printf(self, "Could not map memory\n");
goto error;
}
sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
sc->sc_io_size = rman_get_size(sc->sc_io_res);
rid = 0;
sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
if (sc->sc_irq_res == NULL) {
device_printf(self, "Could not allocate irq\n");
goto error;
}
sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
if (!sc->sc_bus.bdev) {
device_printf(self, "Could not add USB device\n");
goto error;
}
device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
/*
* ehci_pci_match will never return NULL if ehci_pci_probe
* succeeded
*/
device_set_desc(sc->sc_bus.bdev, ehci_pci_match(self));
switch (pci_get_vendor(self)) {
case PCI_EHCI_VENDORID_ACERLABS:
sprintf(sc->sc_vendor, "AcerLabs");
break;
case PCI_EHCI_VENDORID_AMD:
sprintf(sc->sc_vendor, "AMD");
break;
case PCI_EHCI_VENDORID_APPLE:
sprintf(sc->sc_vendor, "Apple");
break;
case PCI_EHCI_VENDORID_ATI:
sprintf(sc->sc_vendor, "ATI");
break;
case PCI_EHCI_VENDORID_CMDTECH:
sprintf(sc->sc_vendor, "CMDTECH");
break;
case PCI_EHCI_VENDORID_INTEL:
sprintf(sc->sc_vendor, "Intel");
break;
case PCI_EHCI_VENDORID_NEC:
sprintf(sc->sc_vendor, "NEC");
break;
case PCI_EHCI_VENDORID_OPTI:
sprintf(sc->sc_vendor, "OPTi");
break;
case PCI_EHCI_VENDORID_PHILIPS:
sprintf(sc->sc_vendor, "Philips");
break;
case PCI_EHCI_VENDORID_SIS:
sprintf(sc->sc_vendor, "SiS");
break;
case PCI_EHCI_VENDORID_NVIDIA:
case PCI_EHCI_VENDORID_NVIDIA2:
sprintf(sc->sc_vendor, "nVidia");
break;
case PCI_EHCI_VENDORID_VIA:
sprintf(sc->sc_vendor, "VIA");
break;
default:
if (bootverbose)
device_printf(self, "(New EHCI DeviceId=0x%08x)\n",
pci_get_devid(self));
sprintf(sc->sc_vendor, "(0x%04x)", pci_get_vendor(self));
}
#if (__FreeBSD_version >= 700031)
err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl);
#else
err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
(driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl);
#endif
if (err) {
device_printf(self, "Could not setup irq, %d\n", err);
sc->sc_intr_hdl = NULL;
goto error;
}
ehci_pci_take_controller(self);
/* Undocumented quirks taken from Linux */
switch (pci_get_vendor(self)) {
case PCI_EHCI_VENDORID_ATI:
/* SB600 and SB700 EHCI quirk */
switch (pci_get_device(self)) {
case 0x4386:
ehci_pci_ati_quirk(self, 0);
break;
case 0x4396:
ehci_pci_ati_quirk(self, 1);
break;
default:
break;
}
break;
case PCI_EHCI_VENDORID_VIA:
ehci_pci_via_quirk(self);
break;
default:
break;
}
/* Dropped interrupts workaround */
switch (pci_get_vendor(self)) {
case PCI_EHCI_VENDORID_ATI:
case PCI_EHCI_VENDORID_VIA:
sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG;
if (bootverbose)
device_printf(self,
"Dropped interrupts workaround enabled\n");
break;
default:
break;
}
/* Doorbell feature workaround */
switch (pci_get_vendor(self)) {
case PCI_EHCI_VENDORID_NVIDIA:
case PCI_EHCI_VENDORID_NVIDIA2:
sc->sc_flags |= EHCI_SCFLG_IAADBUG;
if (bootverbose)
device_printf(self,
"Doorbell workaround enabled\n");
break;
default:
break;
}
err = ehci_init(sc);
if (!err) {
err = device_probe_and_attach(sc->sc_bus.bdev);
}
if (err) {
device_printf(self, "USB init failed err=%d\n", err);
goto error;
}
return (0);
error:
ehci_pci_detach(self);
return (ENXIO);
}
static const char *
ehci_pci_match(device_t self)
{
uint32_t device_id = pci_get_devid(self);
switch (device_id) {
case 0x523910b9:
return "ALi M5239 USB 2.0 controller";
case 0x10227463:
return "AMD 8111 USB 2.0 controller";
case 0x20951022:
return ("AMD CS5536 (Geode) USB 2.0 controller");
case 0x43451002:
return "ATI SB200 USB 2.0 controller";
case 0x43731002:
return "ATI SB400 USB 2.0 controller";
case 0x43961002:
return ("AMD SB7x0/SB8x0/SB9x0 USB 2.0 controller");
case 0x1e268086:
return ("Intel Panther Point USB 2.0 controller");
case 0x1e2d8086:
return ("Intel Panther Point USB 2.0 controller");
case 0x1f2c8086:
return ("Intel Avoton USB 2.0 controller");
case 0x25ad8086:
return "Intel 6300ESB USB 2.0 controller";
case 0x24cd8086:
return "Intel 82801DB/L/M (ICH4) USB 2.0 controller";
case 0x24dd8086:
return "Intel 82801EB/R (ICH5) USB 2.0 controller";
case 0x265c8086:
return "Intel 82801FB (ICH6) USB 2.0 controller";
case 0x268c8086:
return ("Intel 63XXESB USB 2.0 controller");
case 0x27cc8086:
return "Intel 82801GB/R (ICH7) USB 2.0 controller";
case 0x28368086:
return "Intel 82801H (ICH8) USB 2.0 controller USB2-A";
case 0x283a8086:
return "Intel 82801H (ICH8) USB 2.0 controller USB2-B";
case 0x293a8086:
return "Intel 82801I (ICH9) USB 2.0 controller";
case 0x293c8086:
return "Intel 82801I (ICH9) USB 2.0 controller";
case 0x3a3a8086:
return "Intel 82801JI (ICH10) USB 2.0 controller USB-A";
case 0x3a3c8086:
return "Intel 82801JI (ICH10) USB 2.0 controller USB-B";
case 0x3b348086:
return ("Intel PCH USB 2.0 controller USB-A");
case 0x3b3c8086:
return ("Intel PCH USB 2.0 controller USB-B");
case 0x8c268086:
return ("Intel Lynx Point USB 2.0 controller USB-A");
case 0x8c2d8086:
return ("Intel Lynx Point USB 2.0 controller USB-B");
case 0x00e01033:
return ("NEC uPD 720100 USB 2.0 controller");
case 0x006810de:
return "NVIDIA nForce2 USB 2.0 controller";
case 0x008810de:
return "NVIDIA nForce2 Ultra 400 USB 2.0 controller";
case 0x00d810de:
return "NVIDIA nForce3 USB 2.0 controller";
case 0x00e810de:
return "NVIDIA nForce3 250 USB 2.0 controller";
case 0x005b10de:
return "NVIDIA nForce CK804 USB 2.0 controller";
case 0x036d10de:
return "NVIDIA nForce MCP55 USB 2.0 controller";
case 0x03f210de:
return "NVIDIA nForce MCP61 USB 2.0 controller";
case 0x0aa610de:
return "NVIDIA nForce MCP79 USB 2.0 controller";
case 0x0aa910de:
return "NVIDIA nForce MCP79 USB 2.0 controller";
case 0x0aaa10de:
return "NVIDIA nForce MCP79 USB 2.0 controller";
case 0x15621131:
return "Philips ISP156x USB 2.0 controller";
case 0x31041106:
return ("VIA VT6202 USB 2.0 controller");
default:
break;
}
if ((pci_get_class(self) == PCIC_SERIALBUS)
&& (pci_get_subclass(self) == PCIS_SERIALBUS_USB)
&& (pci_get_progif(self) == PCI_INTERFACE_EHCI)) {
return ("EHCI (generic) USB 2.0 controller");
}
return (NULL); /* dunno */
}
static int
cs4281_pci_attach(device_t dev)
{
struct sc_info *sc;
struct ac97_info *codec = NULL;
char status[SND_STATUSLEN];
sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
sc->dev = dev;
sc->type = pci_get_devid(dev);
pci_enable_busmaster(dev);
#if __FreeBSD_version > 500000
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
/* Reset the power state. */
device_printf(dev, "chip is in D%d power mode "
"-- setting to D0\n", pci_get_powerstate(dev));
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
}
#else
data = pci_read_config(dev, CS4281PCI_PMCS_OFFSET, 4);
if (data & CS4281PCI_PMCS_PS_MASK) {
/* Reset the power state. */
device_printf(dev, "chip is in D%d power mode "
"-- setting to D0\n",
data & CS4281PCI_PMCS_PS_MASK);
pci_write_config(dev, CS4281PCI_PMCS_OFFSET,
data & ~CS4281PCI_PMCS_PS_MASK, 4);
}
#endif
sc->regid = PCIR_BAR(0);
sc->regtype = SYS_RES_MEMORY;
sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE);
if (!sc->reg) {
sc->regtype = SYS_RES_IOPORT;
sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE);
if (!sc->reg) {
device_printf(dev, "unable to allocate register space\n");
goto bad;
}
}
sc->st = rman_get_bustag(sc->reg);
sc->sh = rman_get_bushandle(sc->reg);
sc->memid = PCIR_BAR(1);
sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->memid, 0,
~0, CS4281PCI_BA1_SIZE, RF_ACTIVE);
if (sc->mem == NULL) {
device_printf(dev, "unable to allocate fifo space\n");
goto bad;
}
sc->irqid = 0;
sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
RF_ACTIVE | RF_SHAREABLE);
if (!sc->irq) {
device_printf(dev, "unable to allocate interrupt\n");
goto bad;
}
if (snd_setup_intr(dev, sc->irq, 0, cs4281_intr, sc, &sc->ih)) {
device_printf(dev, "unable to setup interrupt\n");
goto bad;
}
sc->bufsz = pcm_getbuffersize(dev, 4096, CS4281_DEFAULT_BUFSZ, 65536);
if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
/*boundary*/0,
/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
/*maxsize*/sc->bufsz, /*nsegments*/1,
/*maxsegz*/0x3ffff,
/*flags*/0, /*lockfunc*/busdma_lock_mutex,
/*lockarg*/&Giant, &sc->parent_dmat) != 0) {
device_printf(dev, "unable to create dma tag\n");
goto bad;
}
/* power up */
cs4281_power(sc, 0);
/* init chip */
if (cs4281_init(sc) == -1) {
device_printf(dev, "unable to initialize the card\n");
goto bad;
}
/* create/init mixer */
codec = AC97_CREATE(dev, sc, cs4281_ac97);
if (codec == NULL)
goto bad;
mixer_init(dev, ac97_getmixerclass(), codec);
if (pcm_register(dev, sc, 1, 1))
goto bad;
pcm_addchan(dev, PCMDIR_PLAY, &cs4281chan_class, sc);
pcm_addchan(dev, PCMDIR_REC, &cs4281chan_class, sc);
snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s",
(sc->regtype == SYS_RES_IOPORT)? "io" : "memory",
rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cs4281));
pcm_setstatus(dev, status);
return 0;
bad:
if (codec)
ac97_destroy(codec);
if (sc->reg)
bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
if (sc->mem)
bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
if (sc->ih)
bus_teardown_intr(dev, sc->irq, sc->ih);
if (sc->irq)
bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
if (sc->parent_dmat)
bus_dma_tag_destroy(sc->parent_dmat);
free(sc, M_DEVBUF);
return ENXIO;
}
static int
adv_pci_attach(device_t dev)
{
struct adv_softc *adv;
u_int32_t id;
int error, rid, irqrid;
void *ih;
struct resource *iores, *irqres;
/*
* Determine the chip version.
*/
id = pci_get_devid(dev);
pci_enable_busmaster(dev);
/*
* Early chips can't handle non-zero latency timer settings.
*/
if (id == PCI_DEVICE_ID_ADVANSYS_1200A
|| id == PCI_DEVICE_ID_ADVANSYS_1200B) {
pci_write_config(dev, PCIR_LATTIMER, /*value*/0, /*bytes*/1);
}
rid = PCI_BASEADR0;
iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
RF_ACTIVE);
if (iores == NULL)
return ENXIO;
if (adv_find_signature(iores) == 0) {
bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
return ENXIO;
}
adv = adv_alloc(dev, iores, 0);
if (adv == NULL) {
bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
return ENXIO;
}
/* Allocate a dmatag for our transfer DMA maps */
error = bus_dma_tag_create(
/* parent */ bus_get_dma_tag(dev),
/* alignment */ 1,
/* boundary */ 0,
/* lowaddr */ ADV_PCI_MAX_DMA_ADDR,
/* highaddr */ BUS_SPACE_MAXADDR,
/* filter */ NULL,
/* filterarg */ NULL,
/* maxsize */ BUS_SPACE_MAXSIZE_32BIT,
/* nsegments */ ~0,
/* maxsegsz */ ADV_PCI_MAX_DMA_COUNT,
/* flags */ 0,
/* lockfunc */ NULL,
/* lockarg */ NULL,
&adv->parent_dmat);
if (error != 0) {
device_printf(dev, "Could not allocate DMA tag - error %d\n",
error);
adv_free(adv);
bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
return ENXIO;
}
adv->init_level++;
if (overrun_buf == NULL) {
/* Need to allocate our overrun buffer */
if (bus_dma_tag_create(
/* parent */ adv->parent_dmat,
/* alignment */ 8,
/* boundary */ 0,
/* lowaddr */ ADV_PCI_MAX_DMA_ADDR,
/* highaddr */ BUS_SPACE_MAXADDR,
/* filter */ NULL,
/* filterarg */ NULL,
/* maxsize */ ADV_OVERRUN_BSIZE,
/* nsegments */ 1,
/* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT,
/* flags */ 0,
/* lockfunc */ NULL,
/* lockarg */ NULL,
&overrun_dmat) != 0) {
bus_dma_tag_destroy(adv->parent_dmat);
adv_free(adv);
bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
return ENXIO;
}
if (bus_dmamem_alloc(overrun_dmat,
&overrun_buf,
BUS_DMA_NOWAIT,
&overrun_dmamap) != 0) {
bus_dma_tag_destroy(overrun_dmat);
bus_dma_tag_destroy(adv->parent_dmat);
adv_free(adv);
bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
return ENXIO;
}
/* And permanently map it in */
bus_dmamap_load(overrun_dmat, overrun_dmamap,
overrun_buf, ADV_OVERRUN_BSIZE,
adv_map, &overrun_physbase,
/*flags*/0);
}
adv->overrun_physbase = overrun_physbase;
/*
* Stop the chip.
*/
ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_HALT);
ADV_OUTW(adv, ADV_CHIP_STATUS, 0);
adv->chip_version = ADV_INB(adv, ADV_NONEISA_CHIP_REVISION);
adv->type = ADV_PCI;
/*
* Setup active negation and signal filtering.
*/
{
u_int8_t extra_cfg;
if (adv->chip_version >= ADV_CHIP_VER_PCI_ULTRA_3150)
adv->type |= ADV_ULTRA;
if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050)
extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_WR_EN_FILTER;
else
extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_SLEW_RATE;
ADV_OUTB(adv, ADV_REG_IFC, extra_cfg);
}
if (adv_init(adv) != 0) {
adv_free(adv);
bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
return ENXIO;
}
adv->max_dma_count = ADV_PCI_MAX_DMA_COUNT;
adv->max_dma_addr = ADV_PCI_MAX_DMA_ADDR;
#if defined(CC_DISABLE_PCI_PARITY_INT) && CC_DISABLE_PCI_PARITY_INT
{
u_int16_t config_msw;
config_msw = ADV_INW(adv, ADV_CONFIG_MSW);
config_msw &= 0xFFC0;
ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw);
}
#endif
if (id == PCI_DEVICE_ID_ADVANSYS_1200A
|| id == PCI_DEVICE_ID_ADVANSYS_1200B) {
adv->bug_fix_control |= ADV_BUG_FIX_IF_NOT_DWB;
adv->bug_fix_control |= ADV_BUG_FIX_ASYN_USE_SYN;
adv->fix_asyn_xfer = ~0;
}
irqrid = 0;
irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irqrid,
RF_SHAREABLE | RF_ACTIVE);
if (irqres == NULL ||
bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE,
NULL, adv_intr, adv, &ih) != 0) {
if (irqres != NULL)
bus_release_resource(dev, SYS_RES_IRQ, irqrid, irqres);
adv_free(adv);
bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
return ENXIO;
}
if (adv_attach(adv) != 0) {
bus_teardown_intr(dev, irqres, ih);
bus_release_resource(dev, SYS_RES_IRQ, irqrid, irqres);
adv_free(adv);
bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
return ENXIO;
}
return 0;
}
static int
intsmb_attach(device_t dev)
{
struct intsmb_softc *sc = device_get_softc(dev);
int error, rid, value;
int intr;
char *str;
sc->dev = dev;
mtx_init(&sc->lock, device_get_nameunit(dev), "intsmb", MTX_DEF);
sc->cfg_irq9 = 0;
switch (pci_get_devid(dev)) {
#ifndef NO_CHANGE_PCICONF
case 0x71138086: /* Intel 82371AB */
case 0x719b8086: /* Intel 82443MX */
/* Changing configuration is allowed. */
sc->cfg_irq9 = 1;
break;
#endif
case 0x43851002:
case 0x780b1022:
if (pci_get_revid(dev) >= 0x40)
sc->sb8xx = 1;
break;
}
if (sc->sb8xx) {
error = sb8xx_attach(dev);
if (error != 0)
goto fail;
else
goto no_intr;
}
sc->io_rid = PCI_BASE_ADDR_SMB;
sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->io_rid,
RF_ACTIVE);
if (sc->io_res == NULL) {
device_printf(dev, "Could not allocate I/O space\n");
error = ENXIO;
goto fail;
}
if (sc->cfg_irq9) {
pci_write_config(dev, PCIR_INTLINE, 0x9, 1);
pci_write_config(dev, PCI_HST_CFG_SMB,
PCI_INTR_SMB_IRQ9 | PCI_INTR_SMB_ENABLE, 1);
}
value = pci_read_config(dev, PCI_HST_CFG_SMB, 1);
sc->poll = (value & PCI_INTR_SMB_ENABLE) == 0;
intr = value & PCI_INTR_SMB_MASK;
switch (intr) {
case PCI_INTR_SMB_SMI:
str = "SMI";
break;
case PCI_INTR_SMB_IRQ9:
str = "IRQ 9";
break;
case PCI_INTR_SMB_IRQ_PCI:
str = "PCI IRQ";
break;
default:
str = "BOGUS";
}
device_printf(dev, "intr %s %s ", str,
sc->poll == 0 ? "enabled" : "disabled");
printf("revision %d\n", pci_read_config(dev, PCI_REVID_SMB, 1));
if (!sc->poll && intr == PCI_INTR_SMB_SMI) {
device_printf(dev,
"using polling mode when configured interrupt is SMI\n");
sc->poll = 1;
}
if (sc->poll)
goto no_intr;
if (intr != PCI_INTR_SMB_IRQ9 && intr != PCI_INTR_SMB_IRQ_PCI) {
device_printf(dev, "Unsupported interrupt mode\n");
error = ENXIO;
goto fail;
}
/* Force IRQ 9. */
rid = 0;
if (sc->cfg_irq9)
bus_set_resource(dev, SYS_RES_IRQ, rid, 9, 1);
sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
if (sc->irq_res == NULL) {
device_printf(dev, "Could not allocate irq\n");
error = ENXIO;
goto fail;
}
error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
NULL, intsmb_rawintr, sc, &sc->irq_hand);
if (error) {
device_printf(dev, "Failed to map intr\n");
goto fail;
}
no_intr:
sc->isbusy = 0;
sc->smbus = device_add_child(dev, "smbus", -1);
if (sc->smbus == NULL) {
error = ENXIO;
goto fail;
}
error = device_probe_and_attach(sc->smbus);
if (error)
goto fail;
#ifdef ENABLE_ALART
/* Enable Arart */
bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN);
#endif
return (0);
fail:
intsmb_detach(dev);
return (error);
}
/*
* The probe routine.
*/
static int
fwohci_pci_probe( device_t dev )
{
#if 1
uint32_t id;
id = pci_get_devid(dev);
if (id == (FW_VENDORID_NATSEMI | FW_DEVICE_CS4210)) {
device_set_desc(dev, "National Semiconductor CS4210");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_NEC | FW_DEVICE_UPD861)) {
device_set_desc(dev, "NEC uPD72861");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_NEC | FW_DEVICE_UPD871)) {
device_set_desc(dev, "NEC uPD72871/2");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_NEC | FW_DEVICE_UPD72870)) {
device_set_desc(dev, "NEC uPD72870");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_NEC | FW_DEVICE_UPD72873)) {
device_set_desc(dev, "NEC uPD72873");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_NEC | FW_DEVICE_UPD72874)) {
device_set_desc(dev, "NEC uPD72874");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_SIS | FW_DEVICE_7007)) {
/* It has no real identifier, using device id. */
device_set_desc(dev, "SiS 7007");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_TI | FW_DEVICE_TITSB22)) {
device_set_desc(dev, "Texas Instruments TSB12LV22");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_TI | FW_DEVICE_TITSB23)) {
device_set_desc(dev, "Texas Instruments TSB12LV23");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_TI | FW_DEVICE_TITSB26)) {
device_set_desc(dev, "Texas Instruments TSB12LV26");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_TI | FW_DEVICE_TITSB43)) {
device_set_desc(dev, "Texas Instruments TSB43AA22");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_TI | FW_DEVICE_TITSB43A)) {
device_set_desc(dev, "Texas Instruments TSB43AB22/A");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_TI | FW_DEVICE_TITSB43AB21)) {
device_set_desc(dev, "Texas Instruments TSB43AB21/A/AI/A-EP");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_TI | FW_DEVICE_TITSB43AB23)) {
device_set_desc(dev, "Texas Instruments TSB43AB23");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_TI | FW_DEVICE_TITSB82AA2)) {
device_set_desc(dev, "Texas Instruments TSB82AA2");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_TI | FW_DEVICE_TIPCI4450)) {
device_set_desc(dev, "Texas Instruments PCI4450");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_TI | FW_DEVICE_TIPCI4410A)) {
device_set_desc(dev, "Texas Instruments PCI4410A");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_TI | FW_DEVICE_TIPCI4451)) {
device_set_desc(dev, "Texas Instruments PCI4451");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_SONY | FW_DEVICE_CXD1947)) {
device_printf(dev, "Sony i.LINK (CXD1947) not supported\n");
return ENXIO;
}
if (id == (FW_VENDORID_SONY | FW_DEVICE_CXD3222)) {
device_set_desc(dev, "Sony i.LINK (CXD3222)");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_VIA | FW_DEVICE_VT6306)) {
device_set_desc(dev, "VIA Fire II (VT6306)");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_RICOH | FW_DEVICE_R5C551)) {
device_set_desc(dev, "Ricoh R5C551");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_RICOH | FW_DEVICE_R5C552)) {
device_set_desc(dev, "Ricoh R5C552");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_APPLE | FW_DEVICE_PANGEA)) {
device_set_desc(dev, "Apple Pangea");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_APPLE | FW_DEVICE_UNINORTH)) {
device_set_desc(dev, "Apple UniNorth");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_LUCENT | FW_DEVICE_FW322)) {
device_set_desc(dev, "Lucent FW322/323");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_INTEL | FW_DEVICE_82372FB)) {
device_set_desc(dev, "Intel 82372FB");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_ADAPTEC | FW_DEVICE_AIC5800)) {
device_set_desc(dev, "Adaptec AHA-894x/AIC-5800");
return BUS_PROBE_DEFAULT;
}
if (id == (FW_VENDORID_SUN | FW_DEVICE_PCIO2FW)) {
device_set_desc(dev, "Sun PCIO-2");
return BUS_PROBE_DEFAULT;
}
#endif
if (pci_get_class(dev) == PCIC_SERIALBUS
&& pci_get_subclass(dev) == PCIS_SERIALBUS_FW
&& pci_get_progif(dev) == PCI_INTERFACE_OHCI) {
if (bootverbose)
device_printf(dev, "vendor=%x, dev=%x\n",
pci_get_vendor(dev), pci_get_device(dev));
device_set_desc(dev, "1394 Open Host Controller Interface");
return BUS_PROBE_DEFAULT;
}
return ENXIO;
}
static int
si_pci_attach(device_t dev)
{
struct si_softc *sc;
void *ih;
int error;
error = 0;
ih = NULL;
sc = device_get_softc(dev);
switch (pci_get_devid(dev)) {
case 0x400011cb:
sc->sc_type = SIPCI;
sc->sc_mem_rid = SIPCIBADR;
break;
case 0x200011cb:
sc->sc_type = SIJETPCI;
sc->sc_mem_rid = SIJETBADR;
break;
}
sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY,
&sc->sc_mem_rid,
0, ~0, 1, RF_ACTIVE);
if (!sc->sc_mem_res) {
device_printf(dev, "couldn't map memory\n");
goto fail;
}
sc->sc_paddr = (caddr_t)rman_get_start(sc->sc_mem_res);
sc->sc_maddr = rman_get_virtual(sc->sc_mem_res);
sc->sc_irq_rid = 0;
sc->sc_irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->sc_irq_rid,
0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
if (!sc->sc_irq_res) {
device_printf(dev, "couldn't map interrupt\n");
goto fail;
}
sc->sc_irq = rman_get_start(sc->sc_irq_res);
error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, si_intr, sc, &ih, NULL);
if (error) {
device_printf(dev, "could not activate interrupt\n");
goto fail;
}
error = siattach(dev);
if (error)
goto fail;
return (0); /* success */
fail:
if (error == 0)
error = ENXIO;
if (sc->sc_irq_res) {
if (ih)
bus_teardown_intr(dev, sc->sc_irq_res, ih);
bus_release_resource(dev, SYS_RES_IRQ,
sc->sc_irq_rid, sc->sc_irq_res);
sc->sc_irq_res = 0;
}
if (sc->sc_mem_res) {
bus_release_resource(dev, SYS_RES_MEMORY,
sc->sc_mem_rid, sc->sc_mem_res);
sc->sc_mem_res = 0;
}
return (error);
}
