static void fdt_add_uart_nodes(VersalVirt *s) { uint64_t addrs[] = { MM_UART1, MM_UART0 }; unsigned int irqs[] = { VERSAL_UART1_IRQ_0, VERSAL_UART0_IRQ_0 }; const char compat[] = "arm,pl011\0arm,sbsa-uart"; const char clocknames[] = "uartclk\0apb_pclk"; int i; for (i = 0; i < ARRAY_SIZE(addrs); i++) { char *name = g_strdup_printf("/uart@%" PRIx64, addrs[i]); qemu_fdt_add_subnode(s->fdt, name); qemu_fdt_setprop_cell(s->fdt, name, "current-speed", 115200); qemu_fdt_setprop_cells(s->fdt, name, "clocks", s->phandle.clk_125Mhz, s->phandle.clk_125Mhz); qemu_fdt_setprop(s->fdt, name, "clock-names", clocknames, sizeof(clocknames)); qemu_fdt_setprop_cells(s->fdt, name, "interrupts", GIC_FDT_IRQ_TYPE_SPI, irqs[i], GIC_FDT_IRQ_FLAGS_LEVEL_HI); qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 2, addrs[i], 2, 0x1000); qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0); if (addrs[i] == MM_UART0) { /* Select UART0. */ qemu_fdt_setprop_string(s->fdt, "/chosen", "stdout-path", name); } g_free(name); } }
static void fdt_add_gem_nodes(VersalVirt *s) { uint64_t addrs[] = { MM_GEM1, MM_GEM0 }; unsigned int irqs[] = { VERSAL_GEM1_IRQ_0, VERSAL_GEM0_IRQ_0 }; const char clocknames[] = "pclk\0hclk\0tx_clk\0rx_clk"; const char compat_gem[] = "cdns,zynqmp-gem\0cdns,gem"; int i; for (i = 0; i < ARRAY_SIZE(addrs); i++) { char *name = g_strdup_printf("/ethernet@%" PRIx64, addrs[i]); qemu_fdt_add_subnode(s->fdt, name); fdt_add_fixed_link_nodes(s, name, s->phandle.ethernet_phy[i]); qemu_fdt_setprop_string(s->fdt, name, "phy-mode", "rgmii-id"); qemu_fdt_setprop_cell(s->fdt, name, "phy-handle", s->phandle.ethernet_phy[i]); qemu_fdt_setprop_cells(s->fdt, name, "clocks", s->phandle.clk_25Mhz, s->phandle.clk_25Mhz, s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); qemu_fdt_setprop(s->fdt, name, "clock-names", clocknames, sizeof(clocknames)); qemu_fdt_setprop_cells(s->fdt, name, "interrupts", GIC_FDT_IRQ_TYPE_SPI, irqs[i], GIC_FDT_IRQ_FLAGS_LEVEL_HI, GIC_FDT_IRQ_TYPE_SPI, irqs[i], GIC_FDT_IRQ_FLAGS_LEVEL_HI); qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 2, addrs[i], 2, 0x1000); qemu_fdt_setprop(s->fdt, name, "compatible", compat_gem, sizeof(compat_gem)); qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1); qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 0); g_free(name); } }
static void e500plat_fixup_devtree(PPCE500Params *params, void *fdt) { const char model[] = "QEMU ppce500"; const char compatible[] = "fsl,qemu-e500"; qemu_fdt_setprop(fdt, "/", "model", model, sizeof(model)); qemu_fdt_setprop(fdt, "/", "compatible", compatible, sizeof(compatible)); }
static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, hwaddr addr, hwaddr size, uint32_t intc, int irq) { /* Add a virtio_mmio node to the device tree blob: * virtio_mmio@ADDRESS { * compatible = "virtio,mmio"; * reg = <ADDRESS, SIZE>; * interrupt-parent = <&intc>; * interrupts = <0, irq, 1>; * } * (Note that the format of the interrupts property is dependent on the * interrupt controller that interrupt-parent points to; these are for * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.) */ int rc; char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr); rc = qemu_fdt_add_subnode(fdt, nodename); rc |= qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio"); rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, addr, scells, size); qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc); qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); g_free(nodename); if (rc) { return -1; } return 0; }
static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) { hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; int irq0 = MPC8XXX_GPIO_IRQ; gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); gchar *poweroff = g_strdup_printf("%s/power-off", soc); int gpio_ph; qemu_fdt_add_subnode(fdt, node); qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); gpio_ph = qemu_fdt_alloc_phandle(fdt); qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); /* Power Off Pin */ qemu_fdt_add_subnode(fdt, poweroff); qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); g_free(node); g_free(poweroff); }
static void fdt_add_clk_node(VersalVirt *s, const char *name, unsigned int freq_hz, uint32_t phandle) { qemu_fdt_add_subnode(s->fdt, name); qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle); qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz); qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0); qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock"); qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0); }
static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname, uint32_t phandle) { char *name = g_strdup_printf("%s/fixed-link", gemname); qemu_fdt_add_subnode(s->fdt, name); qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle); qemu_fdt_setprop(s->fdt, name, "full-duplex", NULL, 0); qemu_fdt_setprop_cell(s->fdt, name, "speed", 1000); g_free(name); }
static void fdt_add_timer_nodes(VersalVirt *s) { const char compat[] = "arm,armv8-timer"; uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; qemu_fdt_add_subnode(s->fdt, "/timer"); qemu_fdt_setprop_cells(s->fdt, "/timer", "interrupts", GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_S_EL1_IRQ, irqflags, GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL1_IRQ, irqflags, GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_VIRT_IRQ, irqflags, GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL2_IRQ, irqflags); qemu_fdt_setprop(s->fdt, "/timer", "compatible", compat, sizeof(compat)); }
static void fdt_add_gic_nodes(VersalVirt *s) { char *nodename; nodename = g_strdup_printf("/gic@%x", MM_GIC_APU_DIST_MAIN); qemu_fdt_add_subnode(s->fdt, nodename); qemu_fdt_setprop_cell(s->fdt, nodename, "phandle", s->phandle.gic); qemu_fdt_setprop_cells(s->fdt, nodename, "interrupts", GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ, GIC_FDT_IRQ_FLAGS_LEVEL_HI); qemu_fdt_setprop(s->fdt, nodename, "interrupt-controller", NULL, 0); qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg", 2, MM_GIC_APU_DIST_MAIN, 2, MM_GIC_APU_DIST_MAIN_SIZE, 2, MM_GIC_APU_REDIST_0, 2, MM_GIC_APU_REDIST_0_SIZE); qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3); qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3"); g_free(nodename); }
static void create_virtio_regions(VersalVirt *s) { int virtio_mmio_size = 0x200; int i; for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { char *name = g_strdup_printf("virtio%d", i);; hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size; int irq = VERSAL_RSVD_IRQ_FIRST + i; MemoryRegion *mr; DeviceState *dev; qemu_irq pic_irq; pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq); dev = qdev_create(NULL, "virtio-mmio"); object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev), &error_fatal); qdev_init_nofail(dev); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq); mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); memory_region_add_subregion(&s->soc.mr_ps, base, mr); g_free(name); } for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size; int irq = VERSAL_RSVD_IRQ_FIRST + i; char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base); qemu_fdt_add_subnode(s->fdt, name); qemu_fdt_setprop(s->fdt, name, "dma-coherent", NULL, 0); qemu_fdt_setprop_cells(s->fdt, name, "interrupts", GIC_FDT_IRQ_TYPE_SPI, irq, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 2, base, 2, virtio_mmio_size); qemu_fdt_setprop_string(s->fdt, name, "compatible", "virtio,mmio"); g_free(name); } }
static void platform_bus_create_devtree(PPCE500Params *params, void *fdt, const char *mpic) { gchar *node = g_strdup_printf("/platform@%"PRIx64, params->platform_bus_base); const char platcomp[] = "qemu,platform\0simple-bus"; uint64_t addr = params->platform_bus_base; uint64_t size = params->platform_bus_size; int irq_start = params->platform_bus_first_irq; PlatformBusDevice *pbus; DeviceState *dev; /* Create a /platform node that we can put all devices into */ qemu_fdt_add_subnode(fdt, node); qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); /* Our platform bus region is less than 32bit big, so 1 cell is enough for address and size */ qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); dev = qdev_find_recursive(sysbus_get_default(), TYPE_PLATFORM_BUS_DEVICE); pbus = PLATFORM_BUS_DEVICE(dev); /* We can only create dt nodes for dynamic devices when they're ready */ if (pbus->done_gathering) { PlatformDevtreeData data = { .fdt = fdt, .mpic = mpic, .irq_start = irq_start, .node = node, .pbus = pbus, }; /* Loop through all dynamic sysbus devices and create nodes for them */ foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); }
int qemu_fdt_setprop_sized_cells_from_array(void *fdt, const char *node_path, const char *property, int numvalues, uint64_t *values) { uint32_t *propcells; uint64_t value; int cellnum, vnum, ncells; uint32_t hival; int ret; propcells = g_new0(uint32_t, numvalues * 2); cellnum = 0; for (vnum = 0; vnum < numvalues; vnum++) { ncells = values[vnum * 2]; if (ncells != 1 && ncells != 2) { ret = -1; goto out; } value = values[vnum * 2 + 1]; hival = cpu_to_be32(value >> 32); if (ncells > 1) { propcells[cellnum++] = hival; } else if (hival != 0) { ret = -1; goto out; } propcells[cellnum++] = cpu_to_be32(value); } ret = qemu_fdt_setprop(fdt, node_path, property, propcells, cellnum * sizeof(uint32_t)); out: g_free(propcells); return ret; }
static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) { eTSEC *etsec = ETSEC_COMMON(sbdev); PlatformBusDevice *pbus = data->pbus; hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0); gchar *group = g_strdup_printf("%s/queue-group", node); void *fdt = data->fdt; assert((int64_t)mmio0 >= 0); assert(irq0 >= 0); assert(irq1 >= 0); assert(irq2 >= 0); qemu_fdt_add_subnode(fdt, node); qemu_fdt_setprop_string(fdt, node, "device_type", "network"); qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); qemu_fdt_add_subnode(fdt, group); qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); qemu_fdt_setprop_cells(fdt, group, "interrupts", data->irq_start + irq0, 0x2, data->irq_start + irq1, 0x2, data->irq_start + irq2, 0x2); g_free(node); g_free(group); return 0; }
int qemu_fdt_setprop_u64(void *fdt, const char *node_path, const char *property, uint64_t val) { val = cpu_to_be64(val); return qemu_fdt_setprop(fdt, node_path, property, &val, sizeof(val)); }
/** * read_fstree: this function is inspired from dtc read_fstree * @fdt: preallocated fdt blob buffer, to be populated * @dirname: directory to scan under SYSFS_DT_BASEDIR * the search is recursive and the tree is searched down to the * leaves (property files). * * the function asserts in case of error */ static void read_fstree(void *fdt, const char *dirname) { DIR *d; struct dirent *de; struct stat st; const char *root_dir = SYSFS_DT_BASEDIR; const char *parent_node; if (strstr(dirname, root_dir) != dirname) { error_setg(&error_fatal, "%s: %s must be searched within %s", __func__, dirname, root_dir); } parent_node = &dirname[strlen(SYSFS_DT_BASEDIR)]; d = opendir(dirname); if (!d) { error_setg(&error_fatal, "%s cannot open %s", __func__, dirname); } while ((de = readdir(d)) != NULL) { char *tmpnam; if (!g_strcmp0(de->d_name, ".") || !g_strcmp0(de->d_name, "..")) { continue; } tmpnam = g_strdup_printf("%s/%s", dirname, de->d_name); if (lstat(tmpnam, &st) < 0) { error_setg(&error_fatal, "%s cannot lstat %s", __func__, tmpnam); } if (S_ISREG(st.st_mode)) { gchar *val; gsize len; if (!g_file_get_contents(tmpnam, &val, &len, NULL)) { error_setg(&error_fatal, "%s not able to extract info from %s", __func__, tmpnam); } if (strlen(parent_node) > 0) { qemu_fdt_setprop(fdt, parent_node, de->d_name, val, len); } else { qemu_fdt_setprop(fdt, "/", de->d_name, val, len); } g_free(val); } else if (S_ISDIR(st.st_mode)) { char *node_name; node_name = g_strdup_printf("%s/%s", parent_node, de->d_name); qemu_fdt_add_subnode(fdt, node_name); g_free(node_name); read_fstree(fdt, tmpnam); } g_free(tmpnam); } closedir(d); }
static int ppce500_load_device_tree(QEMUMachineInitArgs *args, PPCE500Params *params, hwaddr addr, hwaddr initrd_base, hwaddr initrd_size, bool dry_run) { CPUPPCState *env = first_cpu->env_ptr; int ret = -1; uint64_t mem_reg_property[] = { 0, cpu_to_be64(args->ram_size) }; int fdt_size; void *fdt; uint8_t hypercall[16]; uint32_t clock_freq = 400000000; uint32_t tb_freq = 400000000; int i; char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; char soc[128]; char mpic[128]; uint32_t mpic_ph; uint32_t msi_ph; char gutil[128]; char pci[128]; char msi[128]; uint32_t *pci_map = NULL; int len; uint32_t pci_ranges[14] = { 0x2000000, 0x0, 0xc0000000, 0x0, 0xc0000000, 0x0, 0x20000000, 0x1000000, 0x0, 0x0, 0x0, 0xe1000000, 0x0, 0x10000, }; QemuOpts *machine_opts = qemu_get_machine_opts(); const char *dtb_file = qemu_opt_get(machine_opts, "dtb"); const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); if (dtb_file) { char *filename; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); if (!filename) { goto out; } fdt = load_device_tree(filename, &fdt_size); if (!fdt) { goto out; } goto done; } fdt = create_device_tree(&fdt_size); if (fdt == NULL) { goto out; } /* Manipulate device tree in memory. */ qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); qemu_fdt_add_subnode(fdt, "/memory"); qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, sizeof(mem_reg_property)); qemu_fdt_add_subnode(fdt, "/chosen"); if (initrd_size) { ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base); if (ret < 0) { fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); } ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", (initrd_base + initrd_size)); if (ret < 0) { fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); } } ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", args->kernel_cmdline); if (ret < 0) fprintf(stderr, "couldn't set /chosen/bootargs\n"); if (kvm_enabled()) { /* Read out host's frequencies */ clock_freq = kvmppc_get_clockfreq(); tb_freq = kvmppc_get_tbfreq(); /* indicate KVM hypercall interface */ qemu_fdt_add_subnode(fdt, "/hypervisor"); qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", "linux,kvm"); kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", hypercall, sizeof(hypercall)); /* if KVM supports the idle hcall, set property indicating this */ if (kvmppc_get_hasidle(env)) { qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); } } /* Create CPU nodes */ qemu_fdt_add_subnode(fdt, "/cpus"); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); /* We need to generate the cpu nodes in reverse order, so Linux can pick the first node as boot node and be happy */ for (i = smp_cpus - 1; i >= 0; i--) { CPUState *cpu; PowerPCCPU *pcpu; char cpu_name[128]; uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20); cpu = qemu_get_cpu(i); if (cpu == NULL) { continue; } env = cpu->env_ptr; pcpu = POWERPC_CPU(cpu); snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", ppc_get_vcpu_dt_id(pcpu)); qemu_fdt_add_subnode(fdt, cpu_name); qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); qemu_fdt_setprop_cell(fdt, cpu_name, "reg", ppc_get_vcpu_dt_id(pcpu)); qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", env->dcache_line_size); qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", env->icache_line_size); qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); if (cpu->cpu_index) { qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", "spin-table"); qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", cpu_release_addr); } else { qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); } } qemu_fdt_add_subnode(fdt, "/aliases"); /* XXX These should go into their respective devices' code */ snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE); qemu_fdt_add_subnode(fdt, soc); qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, sizeof(compatible_sb)); qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE, MPC8544_CCSRBAR_SIZE); /* XXX should contain a reasonable value */ qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); qemu_fdt_add_subnode(fdt, mpic); qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 0x40000); qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); mpic_ph = qemu_fdt_alloc_phandle(fdt); qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); /* * We have to generate ser1 first, because Linux takes the first * device it finds in the dt as serial output device. And we generate * devices in reverse order to the dt. */ dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, soc, mpic, "serial1", 1, false); dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, soc, mpic, "serial0", 0, true); snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc, MPC8544_UTIL_OFFSET); qemu_fdt_add_subnode(fdt, gutil); qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); qemu_fdt_add_subnode(fdt, msi); qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); msi_ph = qemu_fdt_alloc_phandle(fdt); qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); qemu_fdt_setprop_cells(fdt, msi, "interrupts", 0xe0, 0x0, 0xe1, 0x0, 0xe2, 0x0, 0xe3, 0x0, 0xe4, 0x0, 0xe5, 0x0, 0xe6, 0x0, 0xe7, 0x0); qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE); qemu_fdt_add_subnode(fdt, pci); qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 0x0, 0x7); pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), params->pci_first_slot, params->pci_nr_slots, &len); qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); for (i = 0; i < 14; i++) { pci_ranges[i] = cpu_to_be32(pci_ranges[i]); } qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); qemu_fdt_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32, MPC8544_PCI_REGS_BASE, 0, 0x1000); qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); params->fixup_devtree(params, fdt); if (toplevel_compat) { qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, strlen(toplevel_compat) + 1); } done: if (!dry_run) { qemu_fdt_dumpdtb(fdt, fdt_size); cpu_physical_memory_write(addr, fdt, fdt_size); } ret = fdt_size; out: g_free(pci_map); return ret; }
static int bamboo_load_device_tree(hwaddr addr, uint32_t ramsize, hwaddr initrd_base, hwaddr initrd_size, const char *kernel_cmdline) { int ret = -1; uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) }; char *filename; int fdt_size; void *fdt; uint32_t tb_freq = 400000000; uint32_t clock_freq = 400000000; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); if (!filename) { goto out; } fdt = load_device_tree(filename, &fdt_size); g_free(filename); if (fdt == NULL) { goto out; } /* Manipulate device tree in memory. */ ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, sizeof(mem_reg_property)); if (ret < 0) fprintf(stderr, "couldn't set /memory/reg\n"); ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base); if (ret < 0) fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", (initrd_base + initrd_size)); if (ret < 0) fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline); if (ret < 0) fprintf(stderr, "couldn't set /chosen/bootargs\n"); /* Copy data from the host device tree into the guest. Since the guest can * directly access the timebase without host involvement, we must expose * the correct frequencies. */ if (kvm_enabled()) { tb_freq = kvmppc_get_tbfreq(); clock_freq = kvmppc_get_clockfreq(); } qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", clock_freq); qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", tb_freq); rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); g_free(fdt); return 0; out: return ret; }