static int __init rtlx_module_init(void)
{
struct device *dev;
int i, err;
if (!cpu_has_mipsmt) {
printk("VPE loader: not a MIPS MT capable processor\n");
return -ENODEV;
}
if (tclimit == 0) {
printk(KERN_WARNING "No TCs reserved for AP/SP, not "
"initializing RTLX.\nPass maxtcs=<n> argument as kernel "
"argument\n");
return -ENODEV;
}
major = register_chrdev(0, module_name, &rtlx_fops);
if (major < 0) {
printk(register_chrdev_failed);
return major;
}
/* initialise the wait queues */
for (i = 0; i < RTLX_CHANNELS; i++) {
init_waitqueue_head(&channel_wqs[i].rt_queue);
init_waitqueue_head(&channel_wqs[i].lx_queue);
atomic_set(&channel_wqs[i].in_open, 0);
mutex_init(&channel_wqs[i].mutex);
dev = device_create(mt_class, NULL, MKDEV(major, i),
"%s%d", module_name, i);
if (IS_ERR(dev)) {
err = PTR_ERR(dev);
goto out_chrdev;
}
}
/* set up notifiers */
notify.start = starting;
notify.stop = stopping;
vpe_notify(tclimit, ¬ify);
if (cpu_has_vint)
set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch);
else {
pr_err("APRP RTLX init on non-vectored-interrupt processor\n");
err = -ENODEV;
goto out_chrdev;
}
rtlx_irq.dev_id = rtlx;
setup_irq(rtlx_irq_num, &rtlx_irq);
return 0;
out_chrdev:
for (i = 0; i < RTLX_CHANNELS; i++)
device_destroy(mt_class, MKDEV(major, i));
return err;
}
void __init arch_init_irq(void)
{
int corehi_irq;
i8259_set_poll(mips_pcibios_iack);
irqchip_init();
switch (mips_revision_sconid) {
case MIPS_REVISION_SCON_SOCIT:
case MIPS_REVISION_SCON_ROCIT:
if (cpu_has_veic)
init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
MSC01E_INT_BASE, msc_eicirqmap,
msc_nr_eicirqs);
else
init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
MSC01C_INT_BASE, msc_irqmap,
msc_nr_irqs);
break;
case MIPS_REVISION_SCON_SOCITSC:
case MIPS_REVISION_SCON_SOCITSCP:
if (cpu_has_veic)
init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
MSC01E_INT_BASE, msc_eicirqmap,
msc_nr_eicirqs);
else
init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
MSC01C_INT_BASE, msc_irqmap,
msc_nr_irqs);
}
if (gic_present) {
corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
} else {
#if defined(CONFIG_MIPS_MT_SMP)
/* set up ipi interrupts */
if (cpu_has_veic) {
set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
cpu_ipi_resched_irq = MSC01E_INT_SW0;
cpu_ipi_call_irq = MSC01E_INT_SW1;
} else {
cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE +
MIPS_CPU_IPI_RESCHED_IRQ;
cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE +
MIPS_CPU_IPI_CALL_IRQ;
}
arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
#endif
if (cpu_has_veic) {
set_vi_handler(MSC01E_INT_COREHI,
corehi_irqdispatch);
corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI;
} else {
corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
}
}
setup_irq(corehi_irq, &corehi_irqaction);
}
void __init ip32_timer_setup(struct irqaction *irq)
{
irq->handler = no_action;
setup_irq(IP32_R4K_TIMER_IRQ, irq);
}
/*
* The clock management driver isn't initialized at this point, so the
* clocks need to be enabled here manually and then tagged as used in
* the clock driver initialization
*/
static void __init lpc32xx_timer_init(void)
{
u32 clkrate, pllreg;
/* Enable timer clock */
__raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN |
LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1);
/*
* The clock driver isn't initialized at this point. So determine if
* the SYSCLK is driven from the PLL397 or main oscillator and then use
* it to compute the PLL frequency and the PCLK divider to get the base
* timer rates. This rate is needed to compute the tick rate.
*/
if (clk_is_sysclk_mainosc() != 0)
clkrate = LPC32XX_MAIN_OSC_FREQ;
else
clkrate = 397 * LPC32XX_CLOCK_OSC_FREQ;
/* Get ARM HCLKPLL register and convert it into a frequency */
pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
clkrate = clk_get_pllrate_from_reg(clkrate, pllreg);
/* Get PCLK divider and divide ARM PLL clock by it to get timer rate */
clkrate = clkrate / clk_get_pclk_div();
/* Initial timer setup */
__raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
__raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
__raw_writel(1, LCP32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
__raw_writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) |
LCP32XX_TIMER_CNTR_MCR_STOP(0) |
LCP32XX_TIMER_CNTR_MCR_RESET(0),
LCP32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
/* Setup tick interrupt */
setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
/* Setup the clockevent structure. */
lpc32xx_clkevt.mult = div_sc(clkrate, NSEC_PER_SEC,
lpc32xx_clkevt.shift);
lpc32xx_clkevt.max_delta_ns = clockevent_delta2ns(-1,
&lpc32xx_clkevt);
lpc32xx_clkevt.min_delta_ns = clockevent_delta2ns(1,
&lpc32xx_clkevt) + 1;
lpc32xx_clkevt.cpumask = cpumask_of(0);
clockevents_register_device(&lpc32xx_clkevt);
/* Use timer1 as clock source. */
__raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
__raw_writel(0, LCP32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
__raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
__raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
lpc32xx_clksrc.mult = clocksource_hz2mult(clkrate,
lpc32xx_clksrc.shift);
clocksource_register(&lpc32xx_clksrc);
}
static void __init sec_dynamic_timer_init(void)
{
sec_dynamic_timer_setup();
setup_irq(IRQ_TIMER2, &sec_timer2_irq);
setup_irq(IRQ_TIMER4, &sec_tick_timer_irq);
}
void __init
time_init(void)
{
/* probe for the RTC and read it if it exists
* Before the RTC can be probed the loops_per_usec variable needs
* to be initialized to make usleep work. A better value for
* loops_per_usec is calculated by the kernel later once the
* clock has started.
*/
loops_per_usec = 50;
if(RTC_INIT() < 0) {
/* no RTC, start at 1980 */
xtime.tv_sec = 0;
xtime.tv_nsec = 0;
have_rtc = 0;
} else {
/* get the current time */
have_rtc = 1;
update_xtime_from_cmos();
}
/*
* Initialize wall_to_monotonic such that adding it to xtime will yield zero, the
* tv_nsec field must be normalized (i.e., 0 <= nsec < NSEC_PER_SEC).
*/
set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
/* Setup the etrax timers
* Base frequency is 25000 hz, divider 250 -> 100 HZ
* In normal mode, we use timer0, so timer1 is free. In cascade
* mode (which we sometimes use for debugging) both timers are used.
* Remember that linux/timex.h contains #defines that rely on the
* timer settings below (hz and divide factor) !!!
*/
#ifdef USE_CASCADE_TIMERS
*R_TIMER_CTRL =
IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
IO_STATE( R_TIMER_CTRL, i1, nop) |
IO_STATE( R_TIMER_CTRL, tm1, stop_ld) |
IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
IO_STATE( R_TIMER_CTRL, i0, nop) |
IO_STATE( R_TIMER_CTRL, tm0, stop_ld) |
IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
*R_TIMER_CTRL = r_timer_ctrl_shadow =
IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
IO_STATE( R_TIMER_CTRL, i1, nop) |
IO_STATE( R_TIMER_CTRL, tm1, run) |
IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
IO_STATE( R_TIMER_CTRL, i0, nop) |
IO_STATE( R_TIMER_CTRL, tm0, run) |
IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
#else
*R_TIMER_CTRL =
IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) |
IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) |
IO_STATE(R_TIMER_CTRL, i1, nop) |
IO_STATE(R_TIMER_CTRL, tm1, stop_ld) |
IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) |
IO_STATE(R_TIMER_CTRL, i0, nop) |
IO_STATE(R_TIMER_CTRL, tm0, stop_ld) |
IO_STATE(R_TIMER_CTRL, clksel0, flexible);
*R_TIMER_CTRL = r_timer_ctrl_shadow =
IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) |
IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) |
IO_STATE(R_TIMER_CTRL, i1, nop) |
IO_STATE(R_TIMER_CTRL, tm1, run) |
IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) |
IO_STATE(R_TIMER_CTRL, i0, nop) |
IO_STATE(R_TIMER_CTRL, tm0, run) |
IO_STATE(R_TIMER_CTRL, clksel0, flexible);
*R_TIMER_PRESCALE = PRESCALE_VALUE;
#endif
*R_IRQ_MASK0_SET =
IO_STATE(R_IRQ_MASK0_SET, timer0, set); /* unmask the timer irq */
/* now actually register the timer irq handler that calls timer_interrupt() */
setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */
/* enable watchdog if we should use one */
#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
printk("Enabling watchdog...\n");
start_watchdog();
/* If we use the hardware watchdog, we want to trap it as an NMI
and dump registers before it resets us. For this to happen, we
must set the "m" NMI enable flag (which once set, is unset only
when an NMI is taken).
The same goes for the external NMI, but that doesn't have any
driver or infrastructure support yet. */
asm ("setf m");
*R_IRQ_MASK0_SET =
IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
*R_VECT_MASK_SET =
IO_STATE(R_VECT_MASK_SET, nmi, set);
#endif
}
/*
* Set up timer interrupt.
*/
static void __init ioc_timer_init(void)
{
ioctime_init();
setup_irq(IRQ_TIMER, &ioc_timer_irq);
}
/* The decrementer counts at the system (internal) clock frequency divided by
* sixteen, or external oscillator divided by four. We force the processor
* to use system clock divided by sixteen.
*/
void __init mpc8xx_calibrate_decr(void)
{
struct device_node *cpu;
cark8xx_t __iomem *clk_r1;
car8xx_t __iomem *clk_r2;
sitk8xx_t __iomem *sys_tmr1;
sit8xx_t __iomem *sys_tmr2;
int irq, virq;
clk_r1 = immr_map(im_clkrstk);
/* Unlock the SCCR. */
out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY);
out_be32(&clk_r1->cark_sccrk, KAPWR_KEY);
immr_unmap(clk_r1);
/* Force all 8xx processors to use divide by 16 processor clock. */
clk_r2 = immr_map(im_clkrst);
setbits32(&clk_r2->car_sccr, 0x02000000);
immr_unmap(clk_r2);
/* Processor frequency is MHz.
*/
ppc_proc_freq = 50000000;
if (!get_freq("clock-frequency", &ppc_proc_freq))
printk(KERN_ERR "WARNING: Estimating processor frequency "
"(not found)\n");
ppc_tb_freq = ppc_proc_freq / 16;
printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq);
/* Perform some more timer/timebase initialization. This used
* to be done elsewhere, but other changes caused it to get
* called more than once....that is a bad thing.
*
* First, unlock all of the registers we are going to modify.
* To protect them from corruption during power down, registers
* that are maintained by keep alive power are "locked". To
* modify these registers we have to write the key value to
* the key location associated with the register.
* Some boards power up with these unlocked, while others
* are locked. Writing anything (including the unlock code?)
* to the unlocked registers will lock them again. So, here
* we guarantee the registers are locked, then we unlock them
* for our use.
*/
sys_tmr1 = immr_map(im_sitk);
out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY);
out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY);
out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY);
out_be32(&sys_tmr1->sitk_tbscrk, KAPWR_KEY);
out_be32(&sys_tmr1->sitk_rtcsck, KAPWR_KEY);
out_be32(&sys_tmr1->sitk_tbk, KAPWR_KEY);
immr_unmap(sys_tmr1);
init_internal_rtc();
/* Enabling the decrementer also enables the timebase interrupts
* (or from the other point of view, to get decrementer interrupts
* we have to enable the timebase). The decrementer interrupt
* is wired into the vector table, nothing to do here for that.
*/
cpu = of_find_node_by_type(NULL, "cpu");
virq= irq_of_parse_and_map(cpu, 0);
irq = virq_to_hw(virq);
sys_tmr2 = immr_map(im_sit);
out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) |
(TBSCR_TBF | TBSCR_TBE));
immr_unmap(sys_tmr2);
if (setup_irq(virq, &tbint_irqaction))
panic("Could not allocate timer IRQ!");
}
static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
{
struct sh_timer_config *cfg = pdev->dev.platform_data;
struct resource *res;
int irq, ret;
ret = -ENXIO;
memset(p, 0, sizeof(*p));
p->pdev = pdev;
if (!cfg) {
dev_err(&p->pdev->dev, "missing platform data\n");
goto err0;
}
platform_set_drvdata(pdev, p);
res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&p->pdev->dev, "failed to get I/O memory\n");
goto err0;
}
irq = platform_get_irq(p->pdev, 0);
if (irq < 0) {
dev_err(&p->pdev->dev, "failed to get irq\n");
goto err0;
}
/* map memory, let mapbase point to our channel */
p->mapbase = ioremap_nocache(res->start, resource_size(res));
if (p->mapbase == NULL) {
pr_err("sh_cmt: failed to remap I/O memory\n");
goto err0;
}
/* request irq using setup_irq() (too early for request_irq()) */
p->irqaction.name = cfg->name;
p->irqaction.handler = sh_cmt_interrupt;
p->irqaction.dev_id = p;
p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
ret = setup_irq(irq, &p->irqaction);
if (ret) {
pr_err("sh_cmt: failed to request irq %d\n", irq);
goto err1;
}
/* get hold of clock */
p->clk = clk_get(&p->pdev->dev, cfg->clk);
if (IS_ERR(p->clk)) {
pr_err("sh_cmt: cannot get clock \"%s\"\n", cfg->clk);
ret = PTR_ERR(p->clk);
goto err2;
}
if (resource_size(res) == 6) {
p->width = 16;
p->overflow_bit = 0x80;
p->clear_bits = ~0x80;
} else {
p->width = 32;
p->overflow_bit = 0x8000;
p->clear_bits = ~0xc000;
}
return sh_cmt_register(p, cfg->name,
cfg->clockevent_rating,
cfg->clocksource_rating);
err2:
remove_irq(irq, &p->irqaction);
err1:
iounmap(p->mapbase);
err0:
return ret;
}
void __init arch_init_irq(void)
{
int i;
for (i = 0; i < 256; i++) {
if (i & 0x80) {
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 7;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 7;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 7;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 7;
} else if (i & 0x40) {
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 6;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 6;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 6;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 6;
} else if (i & 0x20) {
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 5;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 5;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 5;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 5;
} else if (i & 0x10) {
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 4;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 4;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 4;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 4;
} else if (i & 0x08) {
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 3;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 3;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 3;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 3;
} else if (i & 0x04) {
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 2;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 2;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 2;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 2;
} else if (i & 0x02) {
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 1;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 1;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 1;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 1;
} else if (i & 0x01) {
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 0;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 0;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 0;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 0;
} else {
lc0msk_to_irqnr[i] = 0;
lc1msk_to_irqnr[i] = 0;
lc2msk_to_irqnr[i] = 0;
lc3msk_to_irqnr[i] = 0;
}
}
sgint->imask0 = 0;
sgint->imask1 = 0;
sgint->cmeimask0 = 0;
sgint->cmeimask1 = 0;
mips_cpu_irq_init();
for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) {
struct irq_chip *handler;
if (i < SGINT_LOCAL1)
handler = &ip22_local0_irq_type;
else if (i < SGINT_LOCAL2)
handler = &ip22_local1_irq_type;
else if (i < SGINT_LOCAL3)
handler = &ip22_local2_irq_type;
else
handler = &ip22_local3_irq_type;
irq_set_chip_and_handler(i, handler, handle_level_irq);
}
setup_irq(SGI_LOCAL_0_IRQ, &local0_cascade);
setup_irq(SGI_LOCAL_1_IRQ, &local1_cascade);
setup_irq(SGI_BUSERR_IRQ, &buserr);
setup_irq(SGI_MAP_0_IRQ, &map0_cascade);
#ifdef USE_LIO3_IRQ
setup_irq(SGI_MAP_1_IRQ, &map1_cascade);
#endif
#ifdef CONFIG_EISA
if (ip22_is_fullhouse())
ip22_eisa_init();
#endif
}
/*
* This sets up the system timers, clock source and clock event.
*/
static void __init u300_timer_init(void)
{
struct clk *clk;
unsigned long rate;
/* Clock the interrupt controller */
clk = clk_get_sys("apptimer", NULL);
BUG_ON(IS_ERR(clk));
clk_enable(clk);
rate = clk_get_rate(clk);
init_sched_clock(&cd, u300_update_sched_clock, 32, rate);
/*
* Disable the "OS" and "DD" timers - these are designed for Symbian!
* Example usage in cnh1601578 cpu subsystem pd_timer_app.c
*/
writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC);
writel(U300_TIMER_APP_ROST_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST);
writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST);
writel(U300_TIMER_APP_RDDT_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT);
writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT);
/* Reset the General Purpose timer 1. */
writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
/* Set up the IRQ handler */
setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq);
/* Reset the General Purpose timer 2 */
writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2);
/* Set this timer to run around forever */
writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC);
/* Set continuous mode so it wraps around */
writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M);
/* Disable timer interrupts */
writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE);
/* Then enable the GP2 timer to use as a free running us counter */
writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
/* Use general purpose timer 2 as clock source */
if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC,
"GPT2", rate, 300, 32, clocksource_mmio_readl_up))
pr_err("timer: failed to initialize U300 clock source\n");
clockevents_calc_mult_shift(&clockevent_u300_1mhz,
rate, APPTIMER_MIN_RANGE);
/* 32bit counter, so 32bits delta is max */
clockevent_u300_1mhz.max_delta_ns =
clockevent_delta2ns(0xffffffff, &clockevent_u300_1mhz);
/* This timer is slow enough to set for 1 cycle == 1 MHz */
clockevent_u300_1mhz.min_delta_ns =
clockevent_delta2ns(1, &clockevent_u300_1mhz);
clockevent_u300_1mhz.cpumask = cpumask_of(0);
clockevents_register_device(&clockevent_u300_1mhz);
/*
* TODO: init and register the rest of the timers too, they can be
* used by hrtimers!
*/
}
/*
* This sets up the system timers, clock source and clock event.
*/
void __init u300_timer_init(void)
{
struct clk *clk;
unsigned long rate;
/* Clock the interrupt controller */
clk = clk_get_sys("apptimer", NULL);
BUG_ON(IS_ERR(clk));
clk_prepare_enable(clk);
rate = clk_get_rate(clk);
setup_sched_clock(u300_read_sched_clock, 32, rate);
/*
* Disable the "OS" and "DD" timers - these are designed for Symbian!
* Example usage in cnh1601578 cpu subsystem pd_timer_app.c
*/
writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC);
writel(U300_TIMER_APP_ROST_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST);
writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST);
writel(U300_TIMER_APP_RDDT_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT);
writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT);
/* Reset the General Purpose timer 1. */
writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
/* Set up the IRQ handler */
setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq);
/* Reset the General Purpose timer 2 */
writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2);
/* Set this timer to run around forever */
writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC);
/* Set continuous mode so it wraps around */
writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M);
/* Disable timer interrupts */
writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE);
/* Then enable the GP2 timer to use as a free running us counter */
writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
/* Use general purpose timer 2 as clock source */
if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC,
"GPT2", rate, 300, 32, clocksource_mmio_readl_up))
pr_err("timer: failed to initialize U300 clock source\n");
/* Configure and register the clockevent */
clockevents_config_and_register(&clockevent_u300_1mhz, rate,
1, 0xffffffff);
/*
* TODO: init and register the rest of the timers too, they can be
* used by hrtimers!
*/
}
/*
* Set up timer interrupt.
*/
static void __init clps7500_timer_init(void)
{
ioctime_init();
setup_irq(IRQ_TIMER, &clps7500_timer_irq);
}
static void __init clps7500_init_irq(void)
{
unsigned int irq, flags;
iomd_writeb(0, IOMD_IRQMASKA);
iomd_writeb(0, IOMD_IRQMASKB);
iomd_writeb(0, IOMD_FIQMASK);
iomd_writeb(0, IOMD_DMAMASK);
for (irq = 0; irq < NR_IRQS; irq++) {
flags = IRQF_VALID;
if (irq <= 6 || (irq >= 9 && irq <= 15) ||
(irq >= 48 && irq <= 55))
flags |= IRQF_PROBE;
switch (irq) {
case 0 ... 7:
set_irq_chip(irq, &clps7500_a_chip);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;
case 8 ... 15:
set_irq_chip(irq, &clps7500_b_chip);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;
case 16 ... 22:
set_irq_chip(irq, &clps7500_dma_chip);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;
case 24 ... 31:
set_irq_chip(irq, &clps7500_c_chip);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;
case 40 ... 47:
set_irq_chip(irq, &clps7500_d_chip);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;
case 48 ... 55:
set_irq_chip(irq, &clps7500_no_chip);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;
case 64 ... 72:
set_irq_chip(irq, &clps7500_fiq_chip);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;
}
}
setup_irq(IRQ_ISA, &irq_isa);
}
void __init sunxi_timer_init(void)
{
#ifdef CONFIG_OF
struct device_node *node;
struct clk *clk;
#endif
unsigned long rate = 0;
int ret, irq;
u32 val;
#ifdef CONFIG_OF
node = of_find_matching_node(NULL, sunxi_timer_dt_ids);
if (!node)
panic("No sunxi timer node");
timer_base = of_iomap(node, 0);
if (!timer_base)
panic("Can't map registers");
irq = irq_of_parse_and_map(node, 0);
if (irq <= 0)
panic("Can't parse IRQ");
clk = of_clk_get(node, 0);
if (IS_ERR(clk))
panic("Can't get timer clock");
rate = clk_get_rate(clk);
#else
timer_base = (void __iomem *)SUNXI_TIMER_VBASE;
irq = SUNXI_IRQ_TIMER0;
#if defined(CONFIG_ARCH_SUN8IW3P1) && defined(CONFIG_FPGA_V4_PLATFORM)
rate = 32000; /* it is proved by test that clk-src=32000, prescale=1 on fpga */
#else
rate = 24000000;
#endif
#endif
writel(rate / (TIMER_SCAL * HZ),
timer_base + TIMER0_INTVAL_REG);
/* set clock source to HOSC, 16 pre-division */
val = readl(timer_base + TIMER0_CTL_REG);
val &= ~(0x07 << 4);
val &= ~(0x03 << 2);
val |= (4 << 4) | (1 << 2);
writel(val, timer_base + TIMER0_CTL_REG);
/* set mode to auto reload */
val = readl(timer_base + TIMER0_CTL_REG);
writel(val | TIMER0_CTL_AUTORELOAD, timer_base + TIMER0_CTL_REG);
ret = setup_irq(irq, &sunxi_timer_irq);
if (ret)
pr_warn("failed to setup irq %d\n", irq);
/* Enable timer0 interrupt */
val = readl(timer_base + TIMER_CTL_REG);
writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG);
sunxi_clockevent.mult = div_sc(rate / TIMER_SCAL,
NSEC_PER_SEC,
sunxi_clockevent.shift);
sunxi_clockevent.max_delta_ns = clockevent_delta2ns(0x7fffffff,
&sunxi_clockevent);
sunxi_clockevent.min_delta_ns = clockevent_delta2ns(0x10,
&sunxi_clockevent);
sunxi_clockevent.cpumask = cpumask_of(0);
clockevents_register_device(&sunxi_clockevent);
}
static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
{
struct sh_timer_config *cfg = pdev->dev.platform_data;
struct resource *res, *res2;
int irq, ret;
ret = -ENXIO;
memset(p, 0, sizeof(*p));
p->pdev = pdev;
if (!cfg) {
dev_err(&p->pdev->dev, "missing platform data\n");
goto err0;
}
res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&p->pdev->dev, "failed to get I/O memory\n");
goto err0;
}
/* optional resource for the shared timer start/stop register */
res2 = platform_get_resource(p->pdev, IORESOURCE_MEM, 1);
irq = platform_get_irq(p->pdev, 0);
if (irq < 0) {
dev_err(&p->pdev->dev, "failed to get irq\n");
goto err0;
}
/* map memory, let mapbase point to our channel */
p->mapbase = ioremap_nocache(res->start, resource_size(res));
if (p->mapbase == NULL) {
dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
goto err0;
}
/* map second resource for CMSTR */
p->mapbase_str = ioremap_nocache(res2 ? res2->start :
res->start - cfg->channel_offset,
res2 ? resource_size(res2) : 2);
if (p->mapbase_str == NULL) {
dev_err(&p->pdev->dev, "failed to remap I/O second memory\n");
goto err1;
}
/* request irq using setup_irq() (too early for request_irq()) */
p->irqaction.name = dev_name(&p->pdev->dev);
p->irqaction.handler = sh_cmt_interrupt;
p->irqaction.dev_id = p;
p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
IRQF_IRQPOLL | IRQF_NOBALANCING;
/* get hold of clock */
p->clk = clk_get(&p->pdev->dev, "cmt_fck");
if (IS_ERR(p->clk)) {
dev_err(&p->pdev->dev, "cannot get clock\n");
ret = PTR_ERR(p->clk);
goto err2;
}
ret = clk_prepare(p->clk);
if (ret < 0)
goto err3;
if (res2 && (resource_size(res2) == 4)) {
/* assume both CMSTR and CMCSR to be 32-bit */
p->read_control = sh_cmt_read32;
p->write_control = sh_cmt_write32;
} else {
p->read_control = sh_cmt_read16;
p->write_control = sh_cmt_write16;
}
if (resource_size(res) == 6) {
p->width = 16;
p->read_count = sh_cmt_read16;
p->write_count = sh_cmt_write16;
p->overflow_bit = 0x80;
p->clear_bits = ~0x80;
} else {
p->width = 32;
p->read_count = sh_cmt_read32;
p->write_count = sh_cmt_write32;
p->overflow_bit = 0x8000;
p->clear_bits = ~0xc000;
}
if (p->width == (sizeof(p->max_match_value) * 8))
p->max_match_value = ~0;
else
p->max_match_value = (1 << p->width) - 1;
p->match_value = p->max_match_value;
raw_spin_lock_init(&p->lock);
ret = sh_cmt_register(p, (char *)dev_name(&p->pdev->dev),
cfg->clockevent_rating,
cfg->clocksource_rating);
if (ret) {
dev_err(&p->pdev->dev, "registration failed\n");
goto err4;
}
p->cs_enabled = false;
ret = setup_irq(irq, &p->irqaction);
if (ret) {
dev_err(&p->pdev->dev, "failed to request irq %d\n", irq);
goto err4;
}
platform_set_drvdata(pdev, p);
return 0;
err4:
clk_unprepare(p->clk);
err3:
clk_put(p->clk);
err2:
iounmap(p->mapbase_str);
err1:
iounmap(p->mapbase);
err0:
return ret;
}
void __init nmdk_timer_init(void)
{
unsigned long rate;
struct clk *clk0;
struct clk *clk1;
u32 cr;
clk0 = clk_get_sys("mtu0", NULL);
BUG_ON(IS_ERR(clk0));
clk1 = clk_get_sys("mtu1", NULL);
BUG_ON(IS_ERR(clk1));
clk_enable(clk0);
clk_enable(clk1);
/*
* Tick rate is 2.4MHz for Nomadik and 110MHz for ux500:
* use a divide-by-16 counter if it's more than 16MHz
*/
cr = MTU_CRn_32BITS;;
rate = clk_get_rate(clk0);
if (rate > 16 << 20) {
rate /= 16;
cr |= MTU_CRn_PRESCALE_16;
} else {
cr |= MTU_CRn_PRESCALE_1;
}
clocksource_calc_mult_shift(&nmdk_clksrc, rate, MTU_MIN_RANGE);
/* Timer 0 is the free running clocksource */
writel(cr, mtu_base + MTU_CR(0));
writel(0, mtu_base + MTU_LR(0));
writel(0, mtu_base + MTU_BGLR(0));
writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
/* Now the scheduling clock is ready */
nmdk_clksrc.read = nmdk_read_timer;
if (clocksource_register(&nmdk_clksrc))
pr_err("timer: failed to initialize clock source %s\n",
nmdk_clksrc.name);
/* Timer 1 is used for events, fix according to rate */
cr = MTU_CRn_32BITS;
rate = clk_get_rate(clk1);
if (rate > 16 << 20) {
rate /= 16;
cr |= MTU_CRn_PRESCALE_16;
} else {
cr |= MTU_CRn_PRESCALE_1;
}
clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
nmdk_clkevt.max_delta_ns =
clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
nmdk_clkevt.min_delta_ns =
clockevent_delta2ns(0x00000002, &nmdk_clkevt);
nmdk_clkevt.cpumask = cpumask_of(0);
/* Register irq and clockevents */
setup_irq(IRQ_MTU0, &nmdk_timer_irq);
clockevents_register_device(&nmdk_clkevt);
}
void start_sched()
{
setup_irq(TIMER_IRQ,yield);
start_hw();
irq_enable();
}
void __init arch_init_irq(void)
{
unsigned int irq;
/* Install our interrupt handler, then clear and disable all
* CRIME and MACE interrupts. */
crime->imask = 0;
crime->hard_int = 0;
crime->soft_int = 0;
mace->perif.ctrl.istat = 0;
mace->perif.ctrl.imask = 0;
mips_cpu_irq_init();
for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
switch (irq) {
case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt,
handle_level_irq, "level");
break;
case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
set_irq_chip_and_handler_name(irq,
&ip32_macepci_interrupt, handle_level_irq,
"level");
break;
case CRIME_CPUERR_IRQ:
case CRIME_MEMERR_IRQ:
set_irq_chip_and_handler_name(irq,
&crime_level_interrupt, handle_level_irq,
"level");
break;
case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
case CRIME_VICE_IRQ:
set_irq_chip_and_handler_name(irq,
&crime_edge_interrupt, handle_edge_irq, "edge");
break;
case MACEISA_PARALLEL_IRQ:
case MACEISA_SERIAL1_TDMAPR_IRQ:
case MACEISA_SERIAL2_TDMAPR_IRQ:
set_irq_chip_and_handler_name(irq,
&ip32_maceisa_edge_interrupt, handle_edge_irq,
"edge");
break;
default:
set_irq_chip_and_handler_name(irq,
&ip32_maceisa_level_interrupt, handle_level_irq,
"level");
break;
}
}
setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
change_c0_status(ST0_IM, ALLINTS);
}
void __init nmdk_timer_init(void)
{
unsigned long rate;
struct clk *clk0;
unsigned long min_delta_ticks;
clk0 = clk_get_sys("mtu0", NULL);
BUG_ON(IS_ERR(clk0));
clk_enable(clk0);
/*
* Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
* for ux500.
* Use a divide-by-16 counter if the tick rate is more than 32MHz.
* At 32 MHz, the timer (with 32 bit counter) can be programmed
* to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
* with 16 gives too low timer resolution.
*/
rate = clk_get_rate(clk0);
if (rate > 32000000) {
rate /= 16;
clk_prescale = MTU_CRn_PRESCALE_16;
} else {
clk_prescale = MTU_CRn_PRESCALE_1;
}
nmdk_cycle = (rate + HZ/2) / HZ;
/* Timer 0 is the free running clocksource */
nmdk_clksrc_reset();
if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
rate, 200, 32, clocksource_mmio_readl_down))
pr_err("timer: failed to initialize clock source %s\n",
"mtu_0");
#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
setup_sched_clock(nomadik_read_sched_clock, 32, rate);
#endif
/* Timer 1 is used for events */
clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
nmdk_clkevt.max_delta_ns =
clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
/* When ulppll is disabled timer is working on 32kHz clock. */
min_delta_ticks = prcmu_is_ulppll_disabled()? 0x5 : 0x2;
nmdk_clkevt.min_delta_ns =
clockevent_delta2ns(min_delta_ticks, &nmdk_clkevt);
nmdk_clkevt.cpumask = cpumask_of(0);
/* Register irq and clockevents */
setup_irq(IRQ_MTU0, &nmdk_timer_irq);
clockevents_register_device(&nmdk_clkevt);
#ifdef ARCH_HAS_READ_CURRENT_TIMER
if (!prcmu_is_ulppll_disabled())
set_delay_fn(nmdk_timer_delay_loop);
#endif
}
void __init arch_init_irq(void)
{
int i;
if (insert_resource(&iomem_resource, <q_icu_resource) < 0)
panic("Failed to insert icu memory");
if (request_mem_region(ltq_icu_resource.start,
resource_size(<q_icu_resource), "icu") < 0)
panic("Failed to request icu memory");
ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start,
resource_size(<q_icu_resource));
if (!ltq_icu_membase)
panic("Failed to remap icu memory");
if (insert_resource(&iomem_resource, <q_eiu_resource) < 0)
panic("Failed to insert eiu memory");
if (request_mem_region(ltq_eiu_resource.start,
resource_size(<q_eiu_resource), "eiu") < 0)
panic("Failed to request eiu memory");
ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start,
resource_size(<q_eiu_resource));
if (!ltq_eiu_membase)
panic("Failed to remap eiu memory");
/* make sure all irqs are turned off by default */
for (i = 0; i < 5; i++)
ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET));
/* clear all possibly pending interrupts */
ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
mips_cpu_irq_init();
for (i = 2; i <= 6; i++)
setup_irq(i, &cascade);
if (cpu_has_vint) {
pr_info("Setting up vectored interrupts\n");
set_vi_handler(2, ltq_hw0_irqdispatch);
set_vi_handler(3, ltq_hw1_irqdispatch);
set_vi_handler(4, ltq_hw2_irqdispatch);
set_vi_handler(5, ltq_hw3_irqdispatch);
set_vi_handler(6, ltq_hw4_irqdispatch);
set_vi_handler(7, ltq_hw5_irqdispatch);
}
for (i = INT_NUM_IRQ0;
i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) ||
(i == LTQ_EIU_IR2))
irq_set_chip_and_handler(i, <q_eiu_type,
handle_level_irq);
/* EIU3-5 only exist on ar9 and vr9 */
else if (((i == LTQ_EIU_IR3) || (i == LTQ_EIU_IR4) ||
(i == LTQ_EIU_IR5)) && (ltq_is_ar9() || ltq_is_vr9()))
irq_set_chip_and_handler(i, <q_eiu_type,
handle_level_irq);
else
irq_set_chip_and_handler(i, <q_irq_type,
handle_level_irq);
#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
#else
set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
#endif
}
void __init mach_sched_init (struct irqaction *timer_action)
{
/* ...do magic timer initialization?... */
mach_tick = simcons_poll_ttys;
setup_irq (0, timer_action);
}
/**
* time_init_hook - do any specific initialisations for the system timer.
*
* Description:
* Must plug the system timer interrupt source at HZ into the IRQ listed
* in irq_vectors.h:TIMER_IRQ
**/
void __init time_init_hook(void)
{
setup_irq(0, &irq0);
}
void __init bcm947xx_timer_setup(struct irqaction *irq)
{
/* Enable the timer interrupt */
setup_irq(7, &bcm947xx_timer_irqaction);
}
void __init arch_init_ipiirq(int irq, struct irqaction *action)
{
setup_irq(irq, action);
irq_set_handler(irq, handle_percpu_irq);
}
unsigned int cpm_pic_init(void)
{
struct device_node *np = NULL;
struct resource res;
unsigned int sirq = NO_IRQ, hwirq, eirq;
int ret;
pr_debug("cpm_pic_init\n");
np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic");
if (np == NULL)
np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
if (np == NULL) {
printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
return sirq;
}
ret = of_address_to_resource(np, 0, &res);
if (ret)
goto end;
cpic_reg = ioremap(res.start, resource_size(&res));
if (cpic_reg == NULL)
goto end;
sirq = irq_of_parse_and_map(np, 0);
if (sirq == NO_IRQ)
goto end;
hwirq = (unsigned int)virq_to_hw(sirq);
out_be32(&cpic_reg->cpic_cicr,
(CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
((hwirq/2) << 13) | CICR_HP_MASK);
out_be32(&cpic_reg->cpic_cimr, 0);
cpm_pic_host = irq_domain_add_linear(np, 64, &cpm_pic_host_ops, NULL);
if (cpm_pic_host == NULL) {
printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
sirq = NO_IRQ;
goto end;
}
np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
if (np == NULL)
np = of_find_node_by_type(NULL, "cpm");
if (np == NULL) {
printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
goto end;
}
eirq = irq_of_parse_and_map(np, 0);
if (eirq == NO_IRQ)
goto end;
if (setup_irq(eirq, &cpm_error_irqaction))
printk(KERN_ERR "Could not allocate CPM error IRQ!");
setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
end:
of_node_put(np);
return sirq;
}
void __init arch_init_irq(void)
{
int i;
/* Init local mask --> irq tables. */
for (i = 0; i < 256; i++) {
if (i & 0x80) {
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 7;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 7;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 7;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 7;
} else if (i & 0x40) {
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 6;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 6;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 6;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 6;
} else if (i & 0x20) {
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 5;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 5;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 5;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 5;
} else if (i & 0x10) {
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 4;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 4;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 4;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 4;
} else if (i & 0x08) {
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 3;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 3;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 3;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 3;
} else if (i & 0x04) {
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 2;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 2;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 2;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 2;
} else if (i & 0x02) {
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 1;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 1;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 1;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 1;
} else if (i & 0x01) {
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 0;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 0;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 0;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 0;
} else {
lc0msk_to_irqnr[i] = 0;
lc1msk_to_irqnr[i] = 0;
lc2msk_to_irqnr[i] = 0;
lc3msk_to_irqnr[i] = 0;
}
}
/* Mask out all interrupts. */
sgint->imask0 = 0;
sgint->imask1 = 0;
sgint->cmeimask0 = 0;
sgint->cmeimask1 = 0;
/* init CPU irqs */
mips_cpu_irq_init();
for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) {
struct irq_chip *handler;
if (i < SGINT_LOCAL1)
handler = &ip22_local0_irq_type;
else if (i < SGINT_LOCAL2)
handler = &ip22_local1_irq_type;
else if (i < SGINT_LOCAL3)
handler = &ip22_local2_irq_type;
else
handler = &ip22_local3_irq_type;
set_irq_chip_and_handler(i, handler, handle_level_irq);
}
/* vector handler. this register the IRQ as non-sharable */
setup_irq(SGI_LOCAL_0_IRQ, &local0_cascade);
setup_irq(SGI_LOCAL_1_IRQ, &local1_cascade);
setup_irq(SGI_BUSERR_IRQ, &buserr);
/* cascade in cascade. i love Indy ;-) */
setup_irq(SGI_MAP_0_IRQ, &map0_cascade);
#ifdef USE_LIO3_IRQ
setup_irq(SGI_MAP_1_IRQ, &map1_cascade);
#endif
#ifdef CONFIG_EISA
if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */
ip22_eisa_init();
#endif
}
static void __init msm_timer_init(void)
{
int i;
int res;
int global_offset = 0;
if (cpu_is_msm7x01()) {
msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
} else if (cpu_is_msm7x30()) {
msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
} else if (cpu_is_qsd8x50()) {
msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
} else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
/* Use CPU0's timer as the global timer. */
global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
} else
BUG();
#ifdef CONFIG_ARCH_MSM_SCORPIONMP
writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
#endif
for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
struct msm_clock *clock = &msm_clocks[i];
struct clock_event_device *ce = &clock->clockevent;
struct clocksource *cs = &clock->clocksource;
clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
clock->global_counter = clock->local_counter + global_offset;
writel(0, clock->regbase + TIMER_ENABLE);
writel(0, clock->regbase + TIMER_CLEAR);
writel(~0, clock->regbase + TIMER_MATCH_VAL);
ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
/* allow at least 10 seconds to notice that the timer wrapped */
ce->max_delta_ns =
clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
/* 4 gets rounded down to 3 */
ce->min_delta_ns = clockevent_delta2ns(4, ce);
ce->cpumask = cpumask_of(0);
res = clocksource_register_hz(cs, clock->freq);
if (res)
printk(KERN_ERR "msm_timer_init: clocksource_register "
"failed for %s\n", cs->name);
res = setup_irq(clock->irq.irq, &clock->irq);
if (res)
printk(KERN_ERR "msm_timer_init: setup_irq "
"failed for %s\n", cs->name);
clockevents_register_device(ce);
}
}
