void govw_reg_dump(void) { int i; printf("========== GOVW register dump ==========\n"); for(i=0;i<0xcc;i+=16){ printf("0x%8x : 0x%08x 0x%08x 0x%08x 0x%08x\n",GOVW_BASE_ADDR+i,vppif_reg32_in(GOVW_BASE_ADDR+i), vppif_reg32_in(GOVW_BASE_ADDR+i+4),vppif_reg32_in(GOVW_BASE_ADDR+i+8),vppif_reg32_in(GOVW_BASE_ADDR+i+12)); } printf("GOVW enable %d\n",vppif_reg32_read(GOVW_HD_MIF_ENABLE)); printf("color mode %s\n",vpp_colfmt_str[govw_get_hd_color_format()]); printf("Y addr 0x%x,C addr 0x%x\n",vppif_reg32_in(REG_GOVW_HD_YSA),vppif_reg32_in(REG_GOVW_HD_CSA)); printf("Y width %d,fb width %d\n",vppif_reg32_read(GOVW_HD_YPXLWID),vppif_reg32_read(GOVW_HD_YBUFWID)); printf("C width %d,fb width %d\n",vppif_reg32_read(GOVW_HD_CPXLWID),vppif_reg32_read(GOVW_HD_CBUFWID)); printf("---------- GOVW TG ----------\n"); printf("TG enable %d, wait ready enable %d\n",vppif_reg32_read(GOVW_TG_ENABLE),vppif_reg32_read(GOVW_TG_WATCHDOG_ENABLE)); printf("clk %d,Read cyc %d\n",vpp_get_base_clock(VPP_PLL_B,VPP_DIV_VPP),vppif_reg32_read(GOVW_TG_RDCYC)); printf("H total %d, beg %d, end %d\n",vppif_reg32_read(GOVW_TG_H_ALLPIXEL), vppif_reg32_read(GOVW_TG_H_ACTBG),vppif_reg32_read(GOVW_TG_H_ACTEND)); printf("V total %d, beg %d, end %d\n",vppif_reg32_read(GOVW_TG_V_ALLLINE), vppif_reg32_read(GOVW_TG_V_ACTBG),vppif_reg32_read(GOVW_TG_V_ACTEND)); printf("VBIE %d,PVBI %d\n",vppif_reg32_read(GOVW_TG_VBIE),vppif_reg32_read(GOVW_TG_PVBI)); printf("Watch dog %d\n",vppif_reg32_read(GOVW_TG_WATCHDOG_VALUE)); printf("INT MIF C err %d,Y err %d,TG err %d\n",vppif_reg32_read(GOVW_INT_MIFCERR_ENABLE), vppif_reg32_read(GOVW_INT_MIFYERR_ENABLE),vppif_reg32_read(GOVW_INT_TGERR_ENABLE)); }
void govw_reg_dump(void) { auto_pll_divisor(DEV_GOVW,CLK_ENABLE,0,0); DPRINT("========== GOVW register dump ==========\n"); vpp_reg_dump(REG_GOVW_BEGIN,REG_GOVW_END-REG_GOVW_BEGIN); DPRINT("GOVW enable %d\n",vppif_reg32_read(GOVW_HD_MIF_ENABLE)); DPRINT("color mode %s\n",vpp_colfmt_str[govw_get_color_format()]); DPRINT("Y addr 0x%x,C addr 0x%x\n",vppif_reg32_in(REG_GOVW_HD_YSA),vppif_reg32_in(REG_GOVW_HD_CSA)); DPRINT("Y width %d,fb width %d\n",vppif_reg32_read(GOVW_HD_YPXLWID),vppif_reg32_read(GOVW_HD_YBUFWID)); DPRINT("C width %d,fb width %d\n",vppif_reg32_read(GOVW_HD_CPXLWID),vppif_reg32_read(GOVW_HD_CBUFWID)); DPRINT("---------- GOVW TG ----------\n"); DPRINT("TG enable %d, wait ready enable %d\n",vppif_reg32_read(GOVW_TG_ENABLE),vppif_reg32_read(GOVW_TG_WATCHDOG_ENABLE)); DPRINT("clk %d,Read cyc %d\n",vpp_get_base_clock(VPP_MOD_GOVW),vppif_reg32_read(GOVW_TG_RDCYC)); DPRINT("H total %d, beg %d, end %d\n",vppif_reg32_read(GOVW_TG_H_ALLPIXEL), vppif_reg32_read(GOVW_TG_H_ACTBG),vppif_reg32_read(GOVW_TG_H_ACTEND)); DPRINT("V total %d, beg %d, end %d\n",vppif_reg32_read(GOVW_TG_V_ALLLINE), vppif_reg32_read(GOVW_TG_V_ACTBG),vppif_reg32_read(GOVW_TG_V_ACTEND)); DPRINT("VBIE %d,PVBI %d\n",vppif_reg32_read(GOVW_TG_VBIE),vppif_reg32_read(GOVW_TG_PVBI)); DPRINT("Watch dog 0x%x\n",vppif_reg32_read(GOVW_TG_WATCHDOG_VALUE)); DPRINT("INT MIF C err %d,Y err %d,TG err %d\n",vppif_reg32_read(GOVW_INT_MIFCERR_ENABLE), vppif_reg32_read(GOVW_INT_MIFYERR_ENABLE),vppif_reg32_read(GOVW_INT_TGERR_ENABLE)); auto_pll_divisor(DEV_GOVW,CLK_DISABLE,0,0); }
void scl_reg_dump(void) { auto_pll_divisor(DEV_SCL444U,CLK_ENABLE,0,0); DPRINT("========== SCL register dump ==========\n"); vpp_reg_dump(REG_SCL_BASE1_BEGIN,REG_SCL_BASE1_END-REG_SCL_BASE1_BEGIN); vpp_reg_dump(REG_SCL_BASE2_BEGIN,REG_SCL_BASE2_END-REG_SCL_BASE2_BEGIN); DPRINT("---------- SCL scale ----------\n"); DPRINT("scale enable %d\n",vppif_reg32_read(SCL_ALU_ENABLE)); DPRINT("scale width H %d,V %d\n",vppif_reg32_read(SCL_HXWIDTH),vppif_reg32_read(SCL_VXWIDTH)); DPRINT("H scale up %d,V scale up %d\n",vppif_reg32_read(SCL_HSCLUP_ENABLE),vppif_reg32_read(SCL_VSCLUP_ENABLE)); DPRINT("H sub step %d,thr %d,step %d,sub step cnt %d,i step cnt %d\n",vppif_reg32_read(SCL_H_SUBSTEP), vppif_reg32_read(SCL_H_THR),vppif_reg32_read(SCL_H_STEP),vppif_reg32_read(SCL_H_I_SUBSTEPCNT),vppif_reg32_read(SCL_H_I_STEPCNT)); DPRINT("V sub step %d,thr %d,step %d,sub step cnt %d,i step cnt %d\n",vppif_reg32_read(SCL_V_SUBSTEP), vppif_reg32_read(SCL_V_THR),vppif_reg32_read(SCL_V_STEP),vppif_reg32_read(SCL_V_I_SUBSTEPCNT),vppif_reg32_read(SCL_V_I_STEPCNT)); DPRINT("---------- SCL filter ----------\n"); DPRINT("DEBLOCK %d,boundary 1st 0x%x,2nd 0x%x\n,",vppif_reg32_read(SCL_DEBLOCK_ENABLE), vppif_reg32_read(SCL_1ST_LAYER_BOUNDARY),vppif_reg32_read(SCL_2ND_LAYER_BOUNDARY)); DPRINT("FIELD DEFLICKER %d,up %s down,thr Y %d,C %d\n",vppif_reg32_read(SCL_FIELD_DEFLICKER),vppif_reg32_read(SCL_FIELD_DEFLICKER)?"&":"or", vppif_reg32_read(SCL_FIELD_FILTER_Y_THD),vppif_reg32_read(SCL_FIELD_FILTER_C_THD)); DPRINT("FRAME DEFLICKER %d,%s,2^%d,scene chg %d\n",vppif_reg32_read(SCL_FRAME_DEFLICKER),vppif_reg32_read(SCL_FRAME_FILTER_RGB)?"RGB":"Y", vppif_reg32_read(SCL_FRAME_FILTER_SAMPLER),vppif_reg32_read(SCL_FR_FILTER_SCENE_CHG_THD)); DPRINT("CSC enable %d,CSC clamp %d\n",vppif_reg32_read(SCL_CSC_ENABLE),vppif_reg32_read(SCL_CSC_CLAMP_ENABLE)); DPRINT("---------- SCL TG ----------\n"); DPRINT("TG source : %s\n",(vppif_reg32_read(SCL_TG_GOVWTG_ENABLE))?"GOVW":"SCL"); DPRINT("TG enable %d, wait ready enable %d\n",vppif_reg32_read(SCL_TG_ENABLE),vppif_reg32_read(SCL_TG_WATCHDOG_ENABLE)); DPRINT("clk %d,Read cyc %d,1T %d\n",vpp_get_base_clock(VPP_MOD_SCL),vppif_reg32_read(SCL_TG_RDCYC),vppif_reg32_read(SCL_READCYC_1T)); DPRINT("H total %d, beg %d, end %d\n",vppif_reg32_read(SCL_TG_H_ALLPIXEL),vppif_reg32_read(SCL_TG_H_ACTBG),vppif_reg32_read(SCL_TG_H_ACTEND)); DPRINT("V total %d, beg %d, end %d\n",vppif_reg32_read(SCL_TG_V_ALLLINE),vppif_reg32_read(SCL_TG_V_ACTBG),vppif_reg32_read(SCL_TG_V_ACTEND)); DPRINT("VBIE %d,PVBI %d\n",vppif_reg32_read(SCL_TG_VBIE),vppif_reg32_read(SCL_TG_PVBI)); DPRINT("Watch dog 0x%x\n",vppif_reg32_read(SCL_TG_WATCHDOG_VALUE)); DPRINT("---------- SCLR FB ----------\n"); DPRINT("SCLR MIF enable %d,MIF2 enable %d\n",vppif_reg32_read(SCLR_MIF_ENABLE),vppif_reg32_read(SCLR_MIF2_ENABLE)); DPRINT("color format %s\n",vpp_colfmt_str[sclr_get_color_format()]); DPRINT("color bar enable %d,mode %d,inv %d\n",vppif_reg32_read(SCLR_COLBAR_ENABLE),vppif_reg32_read(SCLR_COLBAR_MODE),vppif_reg32_read(SCLR_COLBAR_INVERSION)); DPRINT("sourc mode : %s,H264 %d\n",(vppif_reg32_read(SCLR_TAR_DISP_FMT))?"field":"frame",vppif_reg32_read(SCLR_MEDIAFMT_H264)); DPRINT("Y addr 0x%x, C addr 0x%x\n",vppif_reg32_in(REG_SCLR_YSA),vppif_reg32_in(REG_SCLR_CSA)); #ifdef REG_SCLR_YSA2 DPRINT("Y addr2 0x%x, C addr2 0x%x\n",vppif_reg32_in(REG_SCLR_YSA2),vppif_reg32_in(REG_SCLR_CSA2)); #endif DPRINT("width %d, fb width %d\n",vppif_reg32_read(SCLR_YPXLWID),vppif_reg32_read(SCLR_YBUFWID)); DPRINT("H crop %d, V crop %d\n",vppif_reg32_read(SCLR_HCROP),vppif_reg32_read(SCLR_VCROP)); DPRINT("---------- SCLW FB ----------\n"); DPRINT("SCLW MIF enable %d\n",vppif_reg32_read(SCLW_MIF_ENABLE)); DPRINT("color format %s\n",vpp_colfmt_str[sclw_get_color_format()]); DPRINT("Y addr 0x%x, C addr 0x%x\n",vppif_reg32_in(REG_SCLW_YSA),vppif_reg32_in(REG_SCLW_CSA)); DPRINT("Y width %d, fb width %d\n",vppif_reg32_read(SCLW_YPXLWID),vppif_reg32_read(SCLW_YBUFWID)); DPRINT("C width %d, fb width %d\n",vppif_reg32_read(SCLW_CPXLWID),vppif_reg32_read(SCLW_CBUFWID)); DPRINT("Y err %d, C err %d\n",vppif_reg32_read(SCLW_INTSTS_MIFYERR),vppif_reg32_read(SCLW_INTSTS_MIFCERR)); auto_pll_divisor(DEV_SCL444U,CLK_DISABLE,0,0); }
unsigned int scl_set_clock(unsigned int pixel_clock) { unsigned int rd_cyc; rd_cyc = vpp_get_base_clock(VPP_MOD_SCL) / pixel_clock; return rd_cyc; }