static void hw2_int_handler(void)
{
/* Hardware Interrupt 2 -- remove interrupt event from queue */
remove_interrupt_event();
g_cp0_regs[CP0_STATUS_REG] = (g_cp0_regs[CP0_STATUS_REG] & ~(CP0_STATUS_SR | CP0_STATUS_TS | UINT32_C(0x00080000))) | CP0_STATUS_IM4;
g_cp0_regs[CP0_CAUSE_REG] = (g_cp0_regs[CP0_CAUSE_REG] | CP0_CAUSE_IP4) & ~CP0_CAUSE_EXCCODE_MASK;
wrapped_exception_general();
}
static void hw2_int_handler(void)
{
/* Hardware Interrupt 2 -- remove interrupt event from queue */
remove_interupt_event();
g_cp0_regs[CP0_STATUS_REG] = (g_cp0_regs[CP0_STATUS_REG] & ~UINT32_C(0x00380000)) | UINT32_C(0x1000);
g_cp0_regs[CP0_CAUSE_REG] = (g_cp0_regs[CP0_CAUSE_REG] | UINT32_C(0x1000)) & UINT32_C(0xffffff83);
wrapped_exception_general();
}
static void hw2_int_handler(usf_state_t * state)
{
// Hardware Interrupt 2 -- remove interrupt event from queue
remove_interupt_event(state);
state->g_cp0_regs[CP0_STATUS_REG] = (state->g_cp0_regs[CP0_STATUS_REG] & ~0x00380000) | 0x1000;
state->g_cp0_regs[CP0_CAUSE_REG] = (state->g_cp0_regs[CP0_CAUSE_REG] | 0x1000) & 0xffffff83;
wrapped_exception_general(state);
}
void raise_maskable_interrupt(uint32_t cause)
{
g_cp0_regs[CP0_CAUSE_REG] = (g_cp0_regs[CP0_CAUSE_REG] | cause) & ~CP0_CAUSE_EXCCODE_MASK;
if (!(g_cp0_regs[CP0_STATUS_REG] & g_cp0_regs[CP0_CAUSE_REG] & UINT32_C(0xff00)))
return;
if ((g_cp0_regs[CP0_STATUS_REG] & (CP0_STATUS_IE | CP0_STATUS_EXL | CP0_STATUS_ERL)) != CP0_STATUS_IE)
return;
wrapped_exception_general();
}
void raise_maskable_interrupt(uint32_t cause)
{
g_cp0_regs[CP0_CAUSE_REG] = (g_cp0_regs[CP0_CAUSE_REG] | cause) & UINT32_C(0xffffff83);
if (!(g_cp0_regs[CP0_STATUS_REG] & g_cp0_regs[CP0_CAUSE_REG] & UINT32_C(0xff00)))
return;
if ((g_cp0_regs[CP0_STATUS_REG] & 7) != 1)
return;
wrapped_exception_general();
}
void raise_maskable_interrupt(usf_state_t * state, uint32_t cause)
{
state->g_cp0_regs[CP0_CAUSE_REG] = (state->g_cp0_regs[CP0_CAUSE_REG] | cause) & 0xffffff83;
if (!(state->g_cp0_regs[CP0_STATUS_REG] & state->g_cp0_regs[CP0_CAUSE_REG] & 0xff00))
return;
if ((state->g_cp0_regs[CP0_STATUS_REG] & 7) != 1)
return;
wrapped_exception_general(state);
}
void gen_interrupt(void)
{
if (stop == 1)
{
g_gs_vi_counter = 0; /* debug */
dyna_stop();
}
if (!interrupt_unsafe_state)
{
if (reset_hard_job)
{
reset_hard();
reset_hard_job = 0;
return;
}
}
if (skip_jump)
{
uint32_t dest = skip_jump;
uint32_t count = g_cp0_regs[CP0_COUNT_REG];
skip_jump = 0;
next_interrupt = (q.first->data.count > count
|| (count - q.first->data.count) < UINT32_C(0x80000000))
? q.first->data.count
: 0;
last_addr = dest;
generic_jump_to(dest);
return;
}
switch(q.first->data.type)
{
case SPECIAL_INT:
special_int_handler();
break;
case VI_INT:
remove_interrupt_event();
vi_vertical_interrupt_event(&g_dev.vi);
retro_return(false);
break;
case COMPARE_INT:
compare_int_handler();
break;
case CHECK_INT:
remove_interrupt_event();
wrapped_exception_general();
break;
case SI_INT:
remove_interrupt_event();
si_end_of_dma_event(&g_dev.si);
break;
case PI_INT:
remove_interrupt_event();
pi_end_of_dma_event(&g_dev.pi);
break;
case AI_INT:
remove_interrupt_event();
ai_end_of_dma_event(&g_dev.ai);
break;
case SP_INT:
remove_interrupt_event();
rsp_interrupt_event(&g_dev.sp);
break;
case DP_INT:
remove_interrupt_event();
rdp_interrupt_event(&g_dev.dp);
break;
case HW2_INT:
hw2_int_handler();
break;
case NMI_INT:
nmi_int_handler();
break;
case CART_INT:
g_cp0_regs[CP0_CAUSE_REG] |= 0x00000800; /* set IP3 */
g_cp0_regs[CP0_CAUSE_REG] &= 0xFFFFFF83; /* mask out old exception code */
remove_interrupt_event();
#if 0
if (dd_end_of_dma_event(&g_dd) == 1)
{
remove_interrupt_event();
g_cp0_regs[CP0_CAUSE_REG] &= ~0x00000800;
}
#endif
break;
default:
DebugMessage(M64MSG_ERROR, "Unknown interrupt queue event type %.8X.", q.first->data.type);
remove_interrupt_event();
wrapped_exception_general();
break;
}
}
void gen_interupt(void)
{
if (stop == 1)
{
g_gs_vi_counter = 0; // debug
dyna_stop();
}
if (!interupt_unsafe_state)
{
if (savestates_get_job() == savestates_job_load)
{
savestates_load();
return;
}
if (reset_hard_job)
{
reset_hard();
reset_hard_job = 0;
return;
}
}
if (skip_jump)
{
uint32_t dest = skip_jump;
skip_jump = 0;
next_interupt = (q.first->data.count > g_cp0_regs[CP0_COUNT_REG]
|| (g_cp0_regs[CP0_COUNT_REG] - q.first->data.count) < UINT32_C(0x80000000))
? q.first->data.count
: 0;
last_addr = dest;
generic_jump_to(dest);
return;
}
switch(q.first->data.type)
{
case SPECIAL_INT:
special_int_handler();
break;
case VI_INT:
remove_interupt_event();
vi_vertical_interrupt_event(&g_vi);
break;
case COMPARE_INT:
compare_int_handler();
break;
case CHECK_INT:
remove_interupt_event();
wrapped_exception_general();
break;
case SI_INT:
remove_interupt_event();
si_end_of_dma_event(&g_si);
break;
case PI_INT:
remove_interupt_event();
pi_end_of_dma_event(&g_pi);
break;
case AI_INT:
remove_interupt_event();
ai_end_of_dma_event(&g_ai);
break;
case SP_INT:
remove_interupt_event();
rsp_interrupt_event(&g_sp);
break;
case DP_INT:
remove_interupt_event();
rdp_interrupt_event(&g_dp);
break;
case HW2_INT:
hw2_int_handler();
break;
case NMI_INT:
nmi_int_handler();
break;
default:
DebugMessage(M64MSG_ERROR, "Unknown interrupt queue event type %.8X.", q.first->data.type);
remove_interupt_event();
wrapped_exception_general();
break;
}
if (!interupt_unsafe_state)
{
if (savestates_get_job() == savestates_job_save)
{
savestates_save();
return;
}
}
}
void osal_fastcall gen_interupt(usf_state_t * state)
{
if (state->stop == 1)
{
state->g_gs_vi_counter = 0; // debug
dyna_stop(state);
}
if (!state->interupt_unsafe_state)
{
if (state->reset_hard_job)
{
reset_hard(state);
state->reset_hard_job = 0;
return;
}
}
if (state->skip_jump)
{
unsigned int dest = state->skip_jump;
state->skip_jump = 0;
state->next_interupt = (state->q.first->data.count > state->g_cp0_regs[CP0_COUNT_REG]
|| (state->g_cp0_regs[CP0_COUNT_REG] - state->q.first->data.count) < 0x80000000)
? state->q.first->data.count
: 0;
state->last_addr = dest;
generic_jump_to(state, dest);
return;
}
switch(state->q.first->data.type)
{
case SPECIAL_INT:
special_int_handler(state);
break;
case VI_INT:
remove_interupt_event(state);
vi_vertical_interrupt_event(&state->g_vi);
break;
case COMPARE_INT:
compare_int_handler(state);
break;
case CHECK_INT:
remove_interupt_event(state);
wrapped_exception_general(state);
break;
case SI_INT:
remove_interupt_event(state);
si_end_of_dma_event(&state->g_si);
break;
case PI_INT:
remove_interupt_event(state);
pi_end_of_dma_event(&state->g_pi);
break;
case AI_INT:
remove_interupt_event(state);
ai_end_of_dma_event(&state->g_ai);
break;
case SP_INT:
remove_interupt_event(state);
rsp_interrupt_event(&state->g_sp);
break;
case DP_INT:
remove_interupt_event(state);
rdp_interrupt_event(&state->g_dp);
break;
case HW2_INT:
hw2_int_handler(state);
break;
case NMI_INT:
nmi_int_handler(state);
break;
default:
DebugMessage(state, M64MSG_ERROR, "Unknown interrupt queue event type %.8X.", state->q.first->data.type);
remove_interupt_event(state);
wrapped_exception_general(state);
break;
}
}