Skip to content

Varunsrivathsa/VLSI-Design-Automation

BranchesTags

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

10 Commits

Netmeger.cpp

Netmeger.cpp

 
 

README.md

README.md

 
 

Soukup.cpp

Soukup.cpp

 
 

cell.h

cell.h

 
 

main1.cpp

main1.cpp

 
 

main2.cpp

main2.cpp

 
 

readFile.cpp

readFile.cpp

 
 

readFiles.cpp

readFiles.cpp

 
 

readNets.cpp

readNets.cpp

 
 

readScl.cpp

readScl.cpp

 
 

Repository files navigation

VLSI-Design-Automation

This repository contains 9 files.

  1. Partitioning of ciruits using Fiduccia-Matteyses Algorithm -cell.h -main1.cpp

  2. Placement of ciruits using Simulated Annealing Algorithm -main2.cpp -readFiles.cpp -readNets.cpp -readScl.cpp

  3. Routing of circuits using Soukup's and Netmerger Algorithm -Netmerger.cpp -Soukup.cpp -readFile.cpp

About

Building a tool which does partitioning placement and routing of VLSI circuit.

Resources

Readme
Activity

Stars

0 stars

Watchers

1 watching

Forks

1 fork
Report repository

Releases

No releases published

Packages

No packages published

Languages