static void
ti_adc_disable(struct ti_adc_softc *sc)
{
int count;
uint32_t data;
TI_ADC_LOCK_ASSERT(sc);
if (sc->sc_last_state == 0)
return;
/* Disable all the enabled steps. */
ADC_WRITE4(sc, ADC_STEPENABLE, 0);
/* Disable the ADC. */
ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) & ~ADC_CTRL_ENABLE);
/* Disable the FIFO0 threshold and the end of sequence interrupt. */
ADC_WRITE4(sc, ADC_IRQENABLE_CLR,
ADC_IRQ_FIFO0_THRES | ADC_IRQ_END_OF_SEQ);
/* ACK any pending interrupt. */
ADC_WRITE4(sc, ADC_IRQSTATUS, ADC_READ4(sc, ADC_IRQSTATUS));
/* Drain the FIFO data. */
count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
while (count > 0) {
data = ADC_READ4(sc, ADC_FIFO0DATA);
count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
}
sc->sc_last_state = 0;
}
static void
ti_adc_intr(void *arg)
{
struct ti_adc_softc *sc;
uint32_t status;
sc = (struct ti_adc_softc *)arg;
status = ADC_READ4(sc, ADC_IRQSTATUS);
if (status == 0)
return;
if (status & ~(ADC_IRQ_FIFO0_THRES | ADC_IRQ_END_OF_SEQ))
device_printf(sc->sc_dev, "stray interrupt: %#x\n", status);
TI_ADC_LOCK(sc);
/* ACK the interrupt. */
ADC_WRITE4(sc, ADC_IRQSTATUS, status);
/* Read the available data. */
if (status & ADC_IRQ_FIFO0_THRES)
ti_adc_read_data(sc);
/* Start the next conversion ? */
if (status & ADC_IRQ_END_OF_SEQ)
ti_adc_setup(sc);
TI_ADC_UNLOCK(sc);
}
static int
ti_adc_open_delay_proc(SYSCTL_HANDLER_ARGS)
{
int error, reg;
struct ti_adc_softc *sc;
struct ti_adc_input *input;
input = (struct ti_adc_input *)arg1;
sc = input->sc;
TI_ADC_LOCK(sc);
reg = (int)ADC_READ4(sc, input->stepdelay) & ADC_STEP_OPEN_DELAY;
TI_ADC_UNLOCK(sc);
error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
if (error != 0 || req->newptr == NULL)
return (error);
if (reg < 0)
reg = 0;
TI_ADC_LOCK(sc);
ADC_WRITE4(sc, input->stepdelay, reg & ADC_STEP_OPEN_DELAY);
TI_ADC_UNLOCK(sc);
return (0);
}
static int
ti_adc_setup(struct ti_adc_softc *sc)
{
int ain;
uint32_t enabled;
TI_ADC_LOCK_ASSERT(sc);
/* Check for enabled inputs. */
enabled = 0;
for (ain = 0; ain < TI_ADC_NPINS; ain++) {
if (ti_adc_inputs[ain].enable)
enabled |= (1U << (ain + 1));
}
/* Set the ADC global status. */
if (enabled != 0) {
ti_adc_enable(sc);
/* Update the enabled steps. */
if (enabled != ADC_READ4(sc, ADC_STEPENABLE))
ADC_WRITE4(sc, ADC_STEPENABLE, enabled);
} else
ti_adc_disable(sc);
return (0);
}
static void
ti_adc_input_setup(struct ti_adc_softc *sc, int32_t ain)
{
struct ti_adc_input *input;
uint32_t reg, val;
TI_ADC_LOCK_ASSERT(sc);
input = &ti_adc_inputs[ain];
reg = input->stepconfig;
val = ADC_READ4(sc, reg);
/* Set single ended operation. */
val &= ~ADC_STEP_DIFF_CNTRL;
/* Set the negative voltage reference. */
val &= ~ADC_STEP_RFM_MSK;
/* Set the positive voltage reference. */
val &= ~ADC_STEP_RFP_MSK;
/* Set the samples average. */
val &= ~ADC_STEP_AVG_MSK;
val |= input->samples << ADC_STEP_AVG_SHIFT;
/* Select the desired input. */
val &= ~ADC_STEP_INP_MSK;
val |= ain << ADC_STEP_INP_SHIFT;
/* Set the ADC to one-shot mode. */
val &= ~ADC_STEP_MODE_MSK;
ADC_WRITE4(sc, reg, val);
}
static void
ti_adc_enable(struct ti_adc_softc *sc)
{
TI_ADC_LOCK_ASSERT(sc);
if (sc->sc_last_state == 1)
return;
/* Enable the FIFO0 threshold and the end of sequence interrupt. */
ADC_WRITE4(sc, ADC_IRQENABLE_SET,
ADC_IRQ_FIFO0_THRES | ADC_IRQ_END_OF_SEQ);
/* Enable the ADC. Run thru enabled steps, start the conversions. */
ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) | ADC_CTRL_ENABLE);
sc->sc_last_state = 1;
}
static void
ti_adc_idlestep_init(struct ti_adc_softc *sc)
{
uint32_t val;
val = ADC_READ4(sc, ADC_IDLECONFIG);
/* Set single ended operation. */
val &= ~ADC_STEP_DIFF_CNTRL;
/* Set the negative voltage reference. */
val &= ~ADC_STEP_RFM_MSK;
/* Set the positive voltage reference. */
val &= ~ADC_STEP_RFP_MSK;
/* Connect the input to VREFN. */
val &= ~ADC_STEP_INP_MSK;
val |= ADC_STEP_IN_VREFN << ADC_STEP_INP_SHIFT;
ADC_WRITE4(sc, ADC_IDLECONFIG, val);
}
static int
ti_adc_clockdiv_proc(SYSCTL_HANDLER_ARGS)
{
int error, reg;
struct ti_adc_softc *sc;
sc = (struct ti_adc_softc *)arg1;
TI_ADC_LOCK(sc);
reg = (int)ADC_READ4(sc, ADC_CLKDIV) + 1;
TI_ADC_UNLOCK(sc);
error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
if (error != 0 || req->newptr == NULL)
return (error);
/*
* The actual written value is the prescaler setting - 1.
* Enforce a minimum value of 10 (i.e. 9) which limits the maximum
* ADC clock to ~2.4Mhz (CLK_M_OSC / 10).
*/
reg--;
if (reg < 9)
reg = 9;
if (reg > USHRT_MAX)
reg = USHRT_MAX;
TI_ADC_LOCK(sc);
/* Disable the ADC. */
ti_adc_disable(sc);
/* Update the ADC prescaler setting. */
ADC_WRITE4(sc, ADC_CLKDIV, reg);
/* Enable the ADC again. */
ti_adc_setup(sc);
TI_ADC_UNLOCK(sc);
return (0);
}
static int
ti_adc_attach(device_t dev)
{
int err, rid;
struct ti_adc_softc *sc;
uint32_t reg, rev;
sc = device_get_softc(dev);
sc->sc_dev = dev;
rid = 0;
sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (!sc->sc_mem_res) {
device_printf(dev, "cannot allocate memory window\n");
return (ENXIO);
}
rid = 0;
sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_ACTIVE);
if (!sc->sc_irq_res) {
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
device_printf(dev, "cannot allocate interrupt\n");
return (ENXIO);
}
if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
NULL, ti_adc_intr, sc, &sc->sc_intrhand) != 0) {
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
device_printf(dev, "Unable to setup the irq handler.\n");
return (ENXIO);
}
/* Activate the ADC_TSC module. */
err = ti_prcm_clk_enable(TSC_ADC_CLK);
if (err)
return (err);
/* Check the ADC revision. */
rev = ADC_READ4(sc, ADC_REVISION);
device_printf(dev,
"scheme: %#x func: %#x rtl: %d rev: %d.%d custom rev: %d\n",
(rev & ADC_REV_SCHEME_MSK) >> ADC_REV_SCHEME_SHIFT,
(rev & ADC_REV_FUNC_MSK) >> ADC_REV_FUNC_SHIFT,
(rev & ADC_REV_RTL_MSK) >> ADC_REV_RTL_SHIFT,
(rev & ADC_REV_MAJOR_MSK) >> ADC_REV_MAJOR_SHIFT,
rev & ADC_REV_MINOR_MSK,
(rev & ADC_REV_CUSTOM_MSK) >> ADC_REV_CUSTOM_SHIFT);
/*
* Disable the step write protect and make it store the step ID for
* the captured data on FIFO.
*/
reg = ADC_READ4(sc, ADC_CTRL);
ADC_WRITE4(sc, ADC_CTRL, reg | ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID);
/*
* Set the ADC prescaler to 2400 (yes, the actual value written here
* is 2400 - 1).
* This sets the ADC clock to ~10Khz (CLK_M_OSC / 2400).
*/
ADC_WRITE4(sc, ADC_CLKDIV, 2399);
TI_ADC_LOCK_INIT(sc);
ti_adc_idlestep_init(sc);
ti_adc_inputs_init(sc);
ti_adc_sysctl_init(sc);
return (0);
}