int t114_get_dev_param(build_image_context *context, u_int32_t index, parse_token token, u_int32_t *value) { nvboot_config_table *bct = NULL; bct = (nvboot_config_table *)(context->bct); assert(context != NULL); assert(bct != NULL); switch (token) { CASE_GET_DEV_PARAM(sdmmc, clock_divider); CASE_GET_DEV_PARAM(sdmmc, data_width); CASE_GET_DEV_PARAM(sdmmc, max_power_class_supported); CASE_GET_DEV_PARAM(sdmmc, multi_page_support); CASE_GET_DEV_PARAM(spiflash, clock_source); CASE_GET_DEV_PARAM(spiflash, clock_divider); CASE_GET_DEV_PARAM(spiflash, read_command_type_fast); CASE_GET_DEV_PARAM(spiflash, page_size_2k_or_16k); case token_dev_type: *value = bct->dev_type[index]; break; default: return -ENODATA; } return 0; }
int t30_get_dev_param(build_image_context *context, uint32_t index, parse_token token, uint32_t *value) { nvboot_config_table *bct = NULL; bct = (nvboot_config_table *)(context->bct); assert(context != NULL); assert(bct != NULL); switch (token) { CASE_GET_DEV_PARAM(nand, clock_divider); CASE_GET_DEV_PARAM(nand, block_size_log2); CASE_GET_DEV_PARAM(nand, page_size_log2); CASE_GET_DEV_PARAM(nand, async_timing0); CASE_GET_DEV_PARAM(nand, async_timing1); CASE_GET_DEV_PARAM(nand, async_timing2); CASE_GET_DEV_PARAM(nand, async_timing3); CASE_GET_DEV_PARAM(nand, sddr_timing0); CASE_GET_DEV_PARAM(nand, sddr_timing1); CASE_GET_DEV_PARAM(nand, tddr_timing0); CASE_GET_DEV_PARAM(nand, tddr_timing1); CASE_GET_DEV_PARAM(nand, fbio_dqsib_dly_byte); CASE_GET_DEV_PARAM(nand, fbio_quse_dly_byte); CASE_GET_DEV_PARAM(nand, fbio_cfg_quse_late); CASE_GET_DEV_PARAM(nand, disable_sync_ddr); CASE_GET_DEV_PARAM(sdmmc, clock_divider); CASE_GET_DEV_PARAM(sdmmc, data_width); CASE_GET_DEV_PARAM(sdmmc, max_power_class_supported); CASE_GET_DEV_PARAM(sdmmc, sd_controller); CASE_GET_DEV_PARAM(spiflash, clock_source); CASE_GET_DEV_PARAM(spiflash, clock_divider); CASE_GET_DEV_PARAM(spiflash, read_command_type_fast); case token_dev_type: *value = bct->dev_type[index]; break; default: return -ENODATA; } return 0; }