uint8_t USCI_A_SPI_getInterruptStatus(uint16_t baseAddress, uint8_t mask) { return (HWREG8(baseAddress + OFS_UCAxIFG) & mask); }
void LDOPWR_togglePort_U0_outputData(uint16_t baseAddress) { HWREG8(baseAddress + OFS_PUCTL_L) ^= PUOUT0; }
void LDOPWR_enable(uint16_t baseAddress) { HWREG8(baseAddress + OFS_LDOPWRCTL_H) |= LDOOEN_H; }
//***************************************************************************** // //! \brief Disables supervisor high side in LPM with tpd = 20 ?s(1) //! //! \param baseAddress is the base address of the PMM module. //! //! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. //! //! \return None // //***************************************************************************** void PMM_SvsHDisabledInLPMNormPerf (uint32_t baseAddress) { HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; HWREG16(baseAddress + OFS_SVSMHCTL) &= ~(SVSMHACE + SVSHFP + SVSHMD); HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; }
//***************************************************************************** // //! \brief Decrease Vcore by one level //! //! \param baseAddress is the base address of the PMM module. //! \param level level to which Vcore needs to be decreased //! Valid values are: //! - \b PMM_CORE_LEVEL_0 [Default] //! - \b PMM_CORE_LEVEL_1 //! - \b PMM_CORE_LEVEL_2 //! - \b PMM_CORE_LEVEL_3 //! //! Modified bits of \b PMMCTL0 register, bits of \b PMMIFG register, bits of //! \b PMMRIE register, bits of \b SVSMHCTL register and bits of \b SVSMLCTL //! register. //! //! \return STATUS_SUCCESS // //***************************************************************************** uint16_t PMM_setVCoreDown (uint32_t baseAddress, uint8_t level) { uint32_t PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup; //The code flow for decreasing the Vcore has been altered to work around //the erratum FLASH37. //Please refer to the Errata sheet to know if a specific device is affected //DO NOT ALTER THIS FUNCTION //Open PMM registers for write access HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; //Disable dedicated Interrupts //Backup all registers PMMRIE_backup = HWREG16(baseAddress + OFS_PMMRIE); HWREG16(baseAddress + OFS_PMMRIE) &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE | SVSLPE | SVMHVLRIE | SVMHIE | SVSMHDLYIE | SVMLVLRIE | SVMLIE | SVSMLDLYIE ); SVSMHCTL_backup = HWREG16(baseAddress + OFS_SVSMHCTL); SVSMLCTL_backup = HWREG16(baseAddress + OFS_SVSMLCTL); //Clear flags HWREG16(baseAddress + OFS_PMMIFG) &= ~(SVMHIFG | SVSMHDLYIFG | SVMLIFG | SVSMLDLYIFG ); //Set SVM, SVS high & low side to new settings in normal mode HWREG16(baseAddress + OFS_SVSMHCTL) = SVMHE | (SVSMHRRL0 * level) | SVSHE | (SVSHRVL0 * level); HWREG16(baseAddress + OFS_SVSMLCTL) = SVMLE | (SVSMLRRL0 * level) | SVSLE | (SVSLRVL0 * level); //Wait until SVM high side and SVM low side is settled while ((HWREG16(baseAddress + OFS_PMMIFG) & SVSMHDLYIFG) == 0 || (HWREG16(baseAddress + OFS_PMMIFG) & SVSMLDLYIFG) == 0) ; //Clear flags HWREG16(baseAddress + OFS_PMMIFG) &= ~(SVSMHDLYIFG + SVSMLDLYIFG); //SVS, SVM core and high side are now set to protect for the new core level //Set VCore to new level HWREG8(baseAddress + OFS_PMMCTL0_L) = PMMCOREV0 * level; //Restore Low side settings //Clear all other bits _except_ level settings HWREG16(baseAddress + OFS_SVSMLCTL) &= (SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2 ); //Clear level settings in the backup register,keep all other bits SVSMLCTL_backup &= ~(SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2); //Restore low-side SVS monitor settings HWREG16(baseAddress + OFS_SVSMLCTL) |= SVSMLCTL_backup; //Restore High side settings //Clear all other bits except level settings HWREG16(baseAddress + OFS_SVSMHCTL) &= (SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2 ); //Clear level settings in the backup register, keep all other bits SVSMHCTL_backup &= ~(SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2); //Restore backup HWREG16(baseAddress + OFS_SVSMHCTL) |= SVSMHCTL_backup; //Wait until high side, low side settled while (((HWREG16(baseAddress + OFS_PMMIFG) & SVSMLDLYIFG) == 0) || ((HWREG16(baseAddress + OFS_PMMIFG) & SVSMHDLYIFG) == 0)) ; //Clear all Flags HWREG16(baseAddress + OFS_PMMIFG) &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG ); //Restore PMM interrupt enable register HWREG16(baseAddress + OFS_PMMRIE) = PMMRIE_backup; //Lock PMM registers for write access HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; //Return: OK return ( STATUS_SUCCESS) ; }
//***************************************************************************** // //! \brief Disables the POR signal generation when a low-voltage event is //! registered by the high-side SVS //! //! \param baseAddress is the base address of the PMM module. //! //! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. //! //! \return None // //***************************************************************************** void PMM_disableSvsHReset (uint32_t baseAddress) { HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; HWREG16(baseAddress + OFS_PMMRIE) &= ~SVSHPE; HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; }
//***************************************************************************** // //! \brief Clear all interrupt flags for the PMM //! //! \param baseAddress is the base address of the PMM module. //! //! Modified bits of \b PMMCTL0 register and bits of \b PMMIFG register. //! //! \return None // //***************************************************************************** void PMM_clearPMMIFGS (uint32_t baseAddress) { HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; HWREG16(baseAddress + OFS_PMMIFG) = 0; HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; }
void SFR_disableInterrupt(uint8_t interruptMask) { HWREG8(SFR_BASE + OFS_SFRIE1_L) &= ~(interruptMask); }
uint8_t SFR_getInterruptStatus(uint8_t interruptFlagMask) { return (HWREG8(SFR_BASE + OFS_SFRIFG1_L) & interruptFlagMask); }
uint8_t USCI_A_SPI_isBusy(uint16_t baseAddress) { //Return the bus busy status. return (HWREG8(baseAddress + OFS_UCAxSTAT) & UCBUSY); }
void SFR_enableInterrupt(uint8_t interruptMask) { HWREG8(SFR_BASE + OFS_SFRIE1_L) |= interruptMask; }
void USCI_A_SPI_disable(uint16_t baseAddress) { //Set the UCSWRST bit to disable the USCI Module HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST; }
void USCI_A_SPI_enable(uint16_t baseAddress) { //Reset the UCSWRST bit to enable the USCI Module HWREG8(baseAddress + OFS_UCAxCTL1) &= ~(UCSWRST); }
void USCI_A_SPI_clearInterrupt(uint16_t baseAddress, uint8_t mask) { HWREG8(baseAddress + OFS_UCAxIFG) &= ~mask; }
//***************************************************************************** // //! \brief Enables the POR signal generation when a low-voltage event is //! registered by the low-side SVS //! //! \param baseAddress is the base address of the PMM module. //! //! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. //! //! \return None // //***************************************************************************** void PMM_enableSvsLReset (uint32_t baseAddress) { HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; HWREG16(baseAddress + OFS_PMMRIE) |= SVSLPE; HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; }
void SFR_clearInterrupt(uint8_t interruptFlagMask) { HWREG8(SFR_BASE + OFS_SFRIFG1_L) &= ~(interruptFlagMask); }
//***************************************************************************** // //! \brief Enables the interrupt generation when a low-voltage event is //! registered by the low-side SVM //! //! \param baseAddress is the base address of the PMM module. //! //! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. //! //! \return None // //***************************************************************************** void PMM_enableSvmLInterrupt (uint32_t baseAddress) { HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; HWREG16(baseAddress + OFS_PMMRIE) |= SVMLIE; HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; }
void SFR_setResetPinPullResistor(uint16_t pullResistorSetup) { HWREG8(SFR_BASE + OFS_SFRRPCR_L) &= ~(SYSRSTRE + SYSRSTUP); HWREG8(SFR_BASE + OFS_SFRRPCR_L) |= pullResistorSetup; }
//***************************************************************************** // //! \brief Disables the interrupt generation when a low-voltage event is //! registered by the high-side SVM //! //! \param baseAddress is the base address of the PMM module. //! //! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. //! //! \return None // //***************************************************************************** void PMM_disableSvmHInterrupt (uint32_t baseAddress) { HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; HWREG16(baseAddress + OFS_PMMRIE) &= ~SVMHIE; HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; }
void SFR_setNMIEdge(uint16_t edgeDirection) { HWREG8(SFR_BASE + OFS_SFRRPCR_L) &= ~(SYSNMIIES); HWREG8(SFR_BASE + OFS_SFRRPCR_L) |= edgeDirection; }
//***************************************************************************** // //! \brief Disables supervisor low side in LPM with twake-up-slow from LPM2, //! LPM3, and LPM4 //! //! \param baseAddress is the base address of the PMM module. //! //! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. //! //! \return None // //***************************************************************************** void PMM_SvsLDisabledInLPMSlowWake (uint32_t baseAddress) { HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; HWREG16(baseAddress + OFS_SVSMLCTL) &= ~(SVSLFP + SVSMLACE + SVSLMD); HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; }
void SFR_setResetNMIPinFunction(uint8_t resetPinFunction) { HWREG8(SFR_BASE + OFS_SFRRPCR_L) &= ~(SYSNMI); HWREG8(SFR_BASE + OFS_SFRRPCR_L) |= resetPinFunction; }
//***************************************************************************** // //! \brief Optimized to provide tpd = 2.5 ?s(1) in LPM with least power //! //! \param baseAddress is the base address of the PMM module. //! //! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. //! //! \return None // //***************************************************************************** void PMM_SvsHOptimizedInLPMFullPerf (uint32_t baseAddress) { HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; HWREG16(baseAddress + OFS_SVSMHCTL) |= (SVSHMD + SVSHFP + SVSMHACE); HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; }
//***************************************************************************** // //! \brief Enables the high-side SVM circuitry //! //! \param baseAddress is the base address of the PMM module. //! //! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. //! //! \return None // //***************************************************************************** void PMM_enableSvmH (uint32_t baseAddress) { HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; HWREG16(baseAddress + OFS_SVSMHCTL) |= SVMHE; HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; }
//***************************************************************************** // //! \brief Disables the low-side SVS circuitry //! //! \param baseAddress is the base address of the PMM module. //! //! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. //! //! \return None // //***************************************************************************** void PMM_disableSvsL (uint32_t baseAddress) { HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; HWREG16(baseAddress + OFS_SVSMLCTL) &= ~SVSLE; HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; }
//***************************************************************************** // //! \brief Enables the low-side SVS and SVM circuitry //! //! \param baseAddress is the base address of the PMM module. //! //! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. //! //! \return None // //***************************************************************************** void PMM_enableSvsLSvmL (uint32_t baseAddress) { HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; HWREG16(baseAddress + OFS_SVSMLCTL) |= (SVSLE + SVMLE); HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; }
void LDOPWR_disableInterrupt(uint16_t baseAddress, uint16_t mask) { HWREG8(baseAddress + OFS_LDOPWRCTL_H) &= ~mask; }
//***************************************************************************** // //! \brief Disables the high-side SVS and SVM circuitry //! //! \param baseAddress is the base address of the PMM module. //! //! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. //! //! \return None // //***************************************************************************** void PMM_disableSvsHSvmH (uint32_t baseAddress) { HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; HWREG16(baseAddress + OFS_SVSMHCTL) &= ~(SVSHE + SVMHE); HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; }
void LDOPWR_disable(uint16_t baseAddress) { HWREG8(baseAddress + OFS_LDOPWRCTL_H) &= ~LDOOEN_H; }
void USCI_A_SPI_disableInterrupt(uint16_t baseAddress, uint8_t mask) { HWREG8(baseAddress + OFS_UCAxIE) &= ~mask; }