//测试用这个函数应该出现在初始化文件中,或是有系统设置好从而删除这个函数 void omap_pinmux_init(void) { MUX(EMIFA_CLK_PINMUXREG,EMIFA_CLK_PINMUX,PINMUX_CONFIG_EMIFA); MUX( KSZ8873_MDC_PINMUXREG,KSZ8873_MDC_PINMUX,PINMUX_CONFIG_MD_GPIO); MUX(KSZ8873_MDIO_PINMUXREG,KSZ8873_MDIO_PINMUX,PINMUX_CONFIG_MD_GPIO); MUX( TMP_SCL_REG,TMP_SCL_PIN,PINMUX_CONFIG_GPIO); MUX(TMP_SDA_REG,TMP_SDA_PIN,PINMUX_CONFIG_GPIO); MUX(1,1,8); MUX(1,7,8); MUX(1,3,8); MUX(1,4,8); MUX(1,5,8); }
/* see inner.h */ uint16_t br_i15_ninv15(uint16_t x) { uint32_t y; y = 2 - x; y = MUL15(y, 2 - MUL15(x, y)); y = MUL15(y, 2 - MUL15(x, y)); y = MUL15(y, 2 - MUL15(x, y)); return MUX(x & 1, -y, 0) & 0x7FFF; }
/* userspace injects packet into plum */ int bpf_dp_channel_push_on_plum(struct datapath *dp, u32 plum_id, u32 port_id, u32 fwd_plum_id, u32 arg1, u32 arg2, u32 arg3, u32 arg4, struct sk_buff *skb, u32 direction) { struct plum_stack stack = {}; struct plum_stack_frame first_frame = {}; struct plum_stack_frame *frame; struct bpf_dp_context *ctx; u32 dest; frame = &first_frame; frame->kmem = 0; INIT_LIST_HEAD(&stack.list); ctx = &frame->ctx; ctx->stack = &stack; ctx->skb = skb; ctx->dp = dp; bpf_dp_ctx_init(ctx); rcu_read_lock(); if (direction == OVS_BPF_OUT_DIR) { ctx->context.plum_id = plum_id; stack.curr_frame = frame; bpf_forward(&ctx->context, port_id); execute_plums(&stack); consume_skb(skb); } else if (direction == OVS_BPF_IN_DIR) { dest = MUX(plum_id, port_id); frame->dest = dest; stack.curr_frame = NULL; list_add(&frame->link, &stack.list); execute_plums(&stack); } else if (direction == OVS_BPF_FWD_TO_PLUM) { ctx->context.plum_id = plum_id; ctx->context.arg1 = arg1; ctx->context.arg2 = arg2; ctx->context.arg3 = arg3; ctx->context.arg4 = arg4; stack.curr_frame = frame; bpf_forward_to_plum(&ctx->context, fwd_plum_id); execute_plums(&stack); consume_skb(skb); } rcu_read_unlock(); return 0; }
/* see inner.h */ uint32_t br_i31_add(uint32_t *a, const uint32_t *b, uint32_t ctl) { uint32_t cc; size_t u, m; cc = 0; m = (a[0] + 63) >> 5; for (u = 1; u < m; u ++) { uint32_t aw, bw, naw; aw = a[u]; bw = b[u]; naw = aw + bw + cc; cc = naw >> 31; a[u] = MUX(ctl, naw & (uint32_t)0x7FFFFFFF, aw); } return cc; }
/* queue the packet to port zero of different plum * * all subsequent bpf_forward()/bpf_forward_self()/bpf_forward_to_plum() * calls from this plum will be ignored */ void bpf_forward_to_plum(struct bpf_context *pctx, u32 plum_id) { struct bpf_dp_context *ctx = container_of(pctx, struct bpf_dp_context, context); struct datapath *dp = ctx->dp; struct plum *plum; u32 dest; if (unlikely(!ctx->skb) || plum_id >= DP_MAX_PLUMS) return; plum = rcu_dereference(dp->plums[pctx->plum_id]); if (unlikely(!plum)) /* plum was unregistered while running */ return; dest = MUX(plum_id, 0); if (dest) plum_stack_push(ctx, dest, 0); }
/* re-queue the packet to plum's own port * * all subsequent bpf_forward()/bpf_forward_self()/bpf_forward_to_plum() * calls from this plum will be ignored */ void bpf_forward_self(struct bpf_context *pctx, u32 port_id) { struct bpf_dp_context *ctx = container_of(pctx, struct bpf_dp_context, context); struct datapath *dp = ctx->dp; struct plum *plum; u32 dest; if (unlikely(!ctx->skb) || port_id >= PLUM_MAX_PORTS) return; plum = rcu_dereference(dp->plums[pctx->plum_id]); if (unlikely(!plum)) return; dest = MUX(pctx->plum_id, port_id); if (dest) { plum_update_stats(plum, port_id, ctx->skb, false); plum_stack_push(ctx, dest, 0); } }
/* see inner.h */ uint32_t br_i32_add(uint32_t *a, const uint32_t *b, uint32_t ctl) { uint32_t cc; size_t u, m; cc = 0; m = (a[0] + 63) >> 5; for (u = 1; u < m; u ++) { uint32_t aw, bw, naw; aw = a[u]; bw = b[u]; naw = aw + bw + cc; /* * Carry is 1 if naw < aw. Carry is also 1 if naw == aw * AND the carry was already 1. */ cc = (cc & EQ(naw, aw)) | LT(naw, aw); a[u] = MUX(ctl, naw, aw); } return cc; }
CLKDIV1, CLKDIV2, PCLKCON, HCLKCON, SCLKCON, }; PNAME(epllref_p) = { "mpllref", "mpllref", "xti", "ext" }; PNAME(esysclk_p) = { "epllref", "epll" }; PNAME(mpllref_p) = { "xti", "mdivclk" }; PNAME(msysclk_p) = { "mpllref", "mpll" }; PNAME(armclk_p) = { "armdiv" , "hclk" }; PNAME(i2s0_p) = { "div_i2s0", "ext_i2s", "epllref", "epllref" }; static struct samsung_mux_clock s3c2443_common_muxes[] __initdata = { MUX(0, "epllref", epllref_p, CLKSRC, 7, 2), MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1), MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1), MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1), MUX(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1), MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2), }; static struct clk_div_table hclk_d[] = { { .val = 0, .div = 1 }, { .val = 1, .div = 2 }, { .val = 3, .div = 4 }, { /* sentinel */ }, }; static struct clk_div_table mdivclk_d[] = {
struct mux { void *reg; u8 mux_shift; u8 mux_width; }; #define MUX(_id, _reg, _mux_shift, _mux_width) \ [_id] = { \ .reg = (void *)TOPCKGEN_REG(_reg), \ .mux_shift = _mux_shift, \ .mux_width = _mux_width, \ } static const struct mux muxes[] = { /* CLK_CFG_0 */ MUX(TOP_AXI_SEL, clk_cfg_0, 0, 3), MUX(TOP_MEM_SEL, clk_cfg_0, 8, 1), MUX(TOP_DDRPHYCFG_SEL, clk_cfg_0, 16, 1), MUX(TOP_MM_SEL, clk_cfg_0, 24, 4), /* CLK_CFG_1 */ MUX(TOP_PWM_SEL, clk_cfg_1, 0, 2), MUX(TOP_VDEC_SEL, clk_cfg_1, 8, 4), MUX(TOP_VENC_SEL, clk_cfg_1, 16, 4), MUX(TOP_MFG_SEL, clk_cfg_1, 24, 4), /* CLK_CFG_2 */ MUX(TOP_CAMTG_SEL, clk_cfg_2, 0, 3), MUX(TOP_UART_SEL, clk_cfg_2, 8, 1), MUX(TOP_SPI_SEL, clk_cfg_2, 16, 3), MUX(TOP_USB20_SEL, clk_cfg_2, 24, 2), /* CLK_CFG_3 */ MUX(TOP_USB30_SEL, clk_cfg_3, 0, 2),
PNAME(mux_xtal_rpu_v) = { "xtal", "rpu_v_pll" }; PNAME(mux_xtal_rpu_l) = { "xtal", "rpu_l_pll" }; PNAME(mux_rpu_l_mips) = { "rpu_l_pll_mux", "mips_pll_mux" }; PNAME(mux_xtal_wifi) = { "xtal", "wifi_pll" }; PNAME(mux_xtal_wifi_div4) = { "xtal", "wifi_div4" }; PNAME(mux_xtal_wifi_div8) = { "xtal", "wifi_div8" }; PNAME(mux_wifi_div4_rpu_l) = { "wifi_pll_gate", "wifi_div4_mux", "rpu_l_pll_mux" }; PNAME(mux_xtal_sys) = { "xtal", "sys_pll" }; PNAME(mux_sys_enet) = { "sys_internal_div", "enet_in" }; PNAME(mux_audio_sys) = { "audio_pll_mux", "sys_internal_div" }; PNAME(mux_sys_bt) = { "sys_internal_div", "bt_pll_mux" }; PNAME(mux_xtal_bt) = { "xtal", "bt_pll" }; static struct pistachio_mux pistachio_muxes[] __initdata = { MUX(CLK_AUDIO_REF_MUX, "audio_refclk_mux", mux_xtal_audio_refclk, 0x200, 0), MUX(CLK_MIPS_PLL_MUX, "mips_pll_mux", mux_xtal_mips, 0x200, 1), MUX(CLK_AUDIO_PLL_MUX, "audio_pll_mux", mux_xtal_audio, 0x200, 2), MUX(CLK_AUDIO_MUX, "audio_mux", mux_audio_debug, 0x200, 4), MUX(CLK_RPU_V_PLL_MUX, "rpu_v_pll_mux", mux_xtal_rpu_v, 0x200, 5), MUX(CLK_RPU_L_PLL_MUX, "rpu_l_pll_mux", mux_xtal_rpu_l, 0x200, 6), MUX(CLK_RPU_L_MUX, "rpu_l_mux", mux_rpu_l_mips, 0x200, 7), MUX(CLK_WIFI_PLL_MUX, "wifi_pll_mux", mux_xtal_wifi, 0x200, 8), MUX(CLK_WIFI_DIV4_MUX, "wifi_div4_mux", mux_xtal_wifi_div4, 0x200, 9), MUX(CLK_WIFI_DIV8_MUX, "wifi_div8_mux", mux_xtal_wifi_div8, 0x200, 10), MUX(CLK_RPU_CORE_MUX, "rpu_core_mux", mux_wifi_div4_rpu_l, 0x200, 11), MUX(CLK_SYS_PLL_MUX, "sys_pll_mux", mux_xtal_sys, 0x200, 13), MUX(CLK_ENET_MUX, "enet_mux", mux_sys_enet, 0x200, 14), MUX(CLK_EVENT_TIMER_MUX, "event_timer_mux", mux_audio_sys, 0x200, 15), MUX(CLK_SD_HOST_MUX, "sd_host_mux", mux_sys_bt, 0x200, 16), MUX(CLK_BT_PLL_MUX, "bt_pll_mux", mux_xtal_bt, 0x200, 17),
* suspend/resume cycle. */ static unsigned long s3c2410_clk_regs[] __initdata = { LOCKTIME, MPLLCON, UPLLCON, CLKCON, CLKSLOW, CLKDIVN, CAMDIVN, }; PNAME(fclk_p) = { "mpll", "div_slow" }; static struct samsung_mux_clock s3c2410_common_muxes[] __initdata = { MUX(FCLK, "fclk", fclk_p, CLKSLOW, 4, 1), }; static struct clk_div_table divslow_d[] = { { .val = 0, .div = 1 }, { .val = 1, .div = 2 }, { .val = 2, .div = 4 }, { .val = 3, .div = 6 }, { .val = 4, .div = 8 }, { .val = 5, .div = 10 }, { .val = 6, .div = 12 }, { .val = 7, .div = 14 }, { /* sentinel */ }, }; static struct samsung_div_clock s3c2410_common_dividers[] __initdata = {
CC_PLL_CON0, BUS0_PLL_CON0, BUS1_DPLL_CON0, MFC_PLL_CON0, AUD_PLL_CON0, MUX_SEL_TOPC0, MUX_SEL_TOPC1, MUX_SEL_TOPC2, MUX_SEL_TOPC3, DIV_TOPC0, DIV_TOPC1, DIV_TOPC3, }; static struct samsung_mux_clock topc_mux_clks[] __initdata = { MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1), MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1), MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1), MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1), MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p, MUX_SEL_TOPC0, 16, 2), MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p, MUX_SEL_TOPC0, 20, 1), MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p, MUX_SEL_TOPC0, 24, 1), MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p, MUX_SEL_TOPC0, 28, 1), MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p, MUX_SEL_TOPC1, 16, 1),
CC_PLL_CON0, BUS0_PLL_CON0, BUS1_DPLL_CON0, MFC_PLL_CON0, AUD_PLL_CON0, MUX_SEL_TOPC0, MUX_SEL_TOPC1, MUX_SEL_TOPC2, MUX_SEL_TOPC3, DIV_TOPC0, DIV_TOPC1, DIV_TOPC3, }; static struct samsung_mux_clock topc_mux_clks[] __initdata = { MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1), MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1), MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1), MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1), MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p, MUX_SEL_TOPC0, 16, 2), MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p, MUX_SEL_TOPC0, 20, 1), MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p, MUX_SEL_TOPC0, 24, 1), MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p, MUX_SEL_TOPC0, 28, 1),
static struct rockchip_pll_clock rk1108_pll_clks[] __initdata = { [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RK1108_PLL_CON(0), RK1108_PLL_CON(3), 8, 31, 0, rk1108_pll_rates), [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK1108_PLL_CON(8), RK1108_PLL_CON(11), 8, 31, 0, NULL), [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK1108_PLL_CON(16), RK1108_PLL_CON(19), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk1108_pll_rates), }; #define MFLAGS CLK_MUX_HIWORD_MASK #define DFLAGS CLK_DIVIDER_HIWORD_MASK #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK static struct rockchip_clk_branch rk1108_uart0_fracmux __initdata = MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK1108_CLKSEL_CON(13), 8, 2, MFLAGS); static struct rockchip_clk_branch rk1108_uart1_fracmux __initdata = MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK1108_CLKSEL_CON(14), 8, 2, MFLAGS); static struct rockchip_clk_branch rk1108_uart2_fracmux __initdata = MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK1108_CLKSEL_CON(15), 8, 2, MFLAGS); static struct rockchip_clk_branch rk1108_i2s0_fracmux __initdata = MUX(0, "i2s0_pre", mux_i2s0_pre_p, CLK_SET_RATE_PARENT, RK1108_CLKSEL_CON(5), 12, 2, MFLAGS); static struct rockchip_clk_branch rk1108_i2s1_fracmux __initdata = MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT,
static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = { RK3368_CPUCLKL_RATE(1512000000, 1, 6, 6), RK3368_CPUCLKL_RATE(1488000000, 1, 5, 5), RK3368_CPUCLKL_RATE(1416000000, 1, 5, 5), RK3368_CPUCLKL_RATE(1200000000, 1, 4, 4), RK3368_CPUCLKL_RATE(1008000000, 1, 4, 4), RK3368_CPUCLKL_RATE( 816000000, 1, 3, 3), RK3368_CPUCLKL_RATE( 696000000, 1, 2, 2), RK3368_CPUCLKL_RATE( 600000000, 1, 2, 2), RK3368_CPUCLKL_RATE( 408000000, 1, 1, 1), RK3368_CPUCLKL_RATE( 312000000, 1, 1, 1), }; static struct rockchip_clk_branch rk3368_i2s_8ch_fracmux __initdata = MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(27), 8, 2, MFLAGS); static struct rockchip_clk_branch rk3368_spdif_8ch_fracmux __initdata = MUX(0, "spdif_8ch_pre", mux_spdif_8ch_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(31), 8, 2, MFLAGS); static struct rockchip_clk_branch rk3368_i2s_2ch_fracmux __initdata = MUX(0, "i2s_2ch_pre", mux_i2s_2ch_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(53), 8, 2, MFLAGS); static struct rockchip_clk_branch rk3368_uart0_fracmux __initdata = MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(33), 8, 2, MFLAGS); static struct rockchip_clk_branch rk3368_uart1_fracmux __initdata = MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 0, GFLAGS), COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS, RK2928_CLKGATE_CON(1), 4, GFLAGS), GATE(0, "aclk_peri", "aclk_peri_pre", 0, RK2928_CLKGATE_CON(2), 1, GFLAGS), COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_pre", 0, RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK2928_CLKGATE_CON(2), 2, GFLAGS), COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_pre", 0, RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK2928_CLKGATE_CON(2), 3, GFLAGS), MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(29), 0, 1, MFLAGS), COMPOSITE_NOMUX(0, "cif0_pre", "cif_src", 0, RK2928_CLKSEL_CON(29), 1, 5, DFLAGS, RK2928_CLKGATE_CON(3), 7, GFLAGS), MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0, RK2928_CLKSEL_CON(29), 7, 1, MFLAGS), GATE(0, "pclkin_cif0", "ext_cif0", 0, RK2928_CLKGATE_CON(3), 3, GFLAGS), /* * the 480m are generated inside the usb block from these clocks, * but they are also a source for the hsicphy clock. */ GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0, RK2928_CLKGATE_CON(1), 5, GFLAGS),
INT("mpe", mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60, 0, tegra_clk_mpe), INT("2d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d), INT("3d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d), INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde_8), INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8), INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_9), INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp_8), INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, tegra_clk_msenc), INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec), INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8), INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se), INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8), INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8), INT8("vic03", mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03), INT_FLAGS("mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, tegra_clk_mselect, CLK_IGNORE_UNUSED), MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_i2s0), MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_i2s1), MUX("i2s2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, tegra_clk_i2s2), MUX("i2s3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, tegra_clk_i2s3), MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk_i2s4), MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out), MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in), MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm), MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx), MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, tegra_clk_amx), MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda), MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x), MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir), MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1), MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2), MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3),
0, RK3328_PLL_CON(16), RK3328_MODE_CON, 8, 2, 0, rk3328_pll_rates), [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, RK3328_PLL_CON(24), RK3328_MODE_CON, 12, 1, 0, rk3328_pll_frac_rates), [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, 0, RK3328_PLL_CON(40), RK3328_MODE_CON, 1, 0, 0, rk3328_pll_rates), }; #define MFLAGS CLK_MUX_HIWORD_MASK #define DFLAGS CLK_DIVIDER_HIWORD_MASK #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) static struct rockchip_clk_branch rk3328_i2s0_fracmux __initdata = MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(6), 8, 2, MFLAGS); static struct rockchip_clk_branch rk3328_i2s1_fracmux __initdata = MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(8), 8, 2, MFLAGS); static struct rockchip_clk_branch rk3328_i2s2_fracmux __initdata = MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(10), 8, 2, MFLAGS); static struct rockchip_clk_branch rk3328_spdif_fracmux __initdata = MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(12), 8, 2, MFLAGS); static struct rockchip_clk_branch rk3328_uart0_fracmux __initdata = MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
/* Fixed rate clocks generated outside the SoC. */ FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_ext_clks) __initdata = { FRATE(0, "fin_pll", NULL, CLK_IS_ROOT, 0), FRATE(0, "xusbxti", NULL, CLK_IS_ROOT, 0), }; /* Fixed rate clocks generated inside the SoC. */ FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_clks) __initdata = { FRATE(CLK27M, "clk27m", NULL, CLK_IS_ROOT, 27000000), FRATE(CLK48M, "clk48m", NULL, CLK_IS_ROOT, 48000000), }; /* List of clock muxes present on all S3C64xx SoCs. */ MUX_CLOCKS(s3c64xx_mux_clks) __initdata = { MUX_F(0, "mout_syncmux", hclkx2_p, OTHERS, 6, 1, 0, CLK_MUX_READ_ONLY), MUX(MOUT_APLL, "mout_apll", apll_p, CLK_SRC, 0, 1), MUX(MOUT_MPLL, "mout_mpll", mpll_p, CLK_SRC, 1, 1), MUX(MOUT_EPLL, "mout_epll", epll_p, CLK_SRC, 2, 1), MUX(MOUT_MFC, "mout_mfc", mfc_p, CLK_SRC, 4, 1), MUX(MOUT_AUDIO0, "mout_audio0", audio0_p, CLK_SRC, 7, 3), MUX(MOUT_AUDIO1, "mout_audio1", audio1_p, CLK_SRC, 10, 3), MUX(MOUT_UART, "mout_uart", uart_p, CLK_SRC, 13, 1), MUX(MOUT_SPI0, "mout_spi0", spi_mmc_p, CLK_SRC, 14, 2), MUX(MOUT_SPI1, "mout_spi1", spi_mmc_p, CLK_SRC, 16, 2), MUX(MOUT_MMC0, "mout_mmc0", spi_mmc_p, CLK_SRC, 18, 2), MUX(MOUT_MMC1, "mout_mmc1", spi_mmc_p, CLK_SRC, 20, 2), MUX(MOUT_MMC2, "mout_mmc2", spi_mmc_p, CLK_SRC, 22, 2), }; /* List of clock muxes present on S3C6400. */ MUX_CLOCKS(s3c6400_mux_clks) __initdata = {
GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "faxi", 18), GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "faxi", 19), GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "faxi", 20), GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "faxi", 22), GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "faxi", 23), GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi", 28), GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "sf", 29), GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "faxi", 30), GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "faxi", 31), /* PERI1 */ GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash", 1), }; static struct mtk_composite infra_muxes[] = { /* INFRA_TOPCKGEN_CKMUXSEL */ MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000, 2, 2), }; static struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3, 7), MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1, 15), MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x040, 16, 1, 23), MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x040, 24, 3, 31), /* CLK_CFG_1 */ MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x050, 0, 2, 7),
/* Common fixed factor clocks. */ static struct samsung_fixed_factor_clock ffactor_clks[] __initdata = { FFACTOR(FOUT_APLL_CLKOUT, "fout_apll_clkout", "fout_apll", 1, 4, 0), FFACTOR(FOUT_MPLL_CLKOUT, "fout_mpll_clkout", "fout_mpll", 1, 2, 0), FFACTOR(DOUT_APLL_CLKOUT, "dout_apll_clkout", "dout_apll", 1, 4, 0), }; /* PLL input mux (fin_pll), which needs to be registered before PLLs. */ static struct samsung_mux_clock early_mux_clks[] __initdata = { MUX_F(FIN_PLL, "fin_pll", fin_pll_p, OM_STAT, 0, 1, CLK_MUX_READ_ONLY, 0), }; /* Common clock muxes. */ static struct samsung_mux_clock mux_clks[] __initdata = { MUX(MOUT_FLASH, "mout_flash", mout_flash_p, CLK_SRC0, 28, 1), MUX(MOUT_PSYS, "mout_psys", mout_group4_p, CLK_SRC0, 24, 1), MUX(MOUT_DSYS, "mout_dsys", mout_group4_p, CLK_SRC0, 20, 1), MUX(MOUT_MSYS, "mout_msys", mout_group3_p, CLK_SRC0, 16, 1), MUX(MOUT_EPLL, "mout_epll", mout_epll_p, CLK_SRC0, 8, 1), MUX(MOUT_MPLL, "mout_mpll", mout_mpll_p, CLK_SRC0, 4, 1), MUX(MOUT_APLL, "mout_apll", mout_apll_p, CLK_SRC0, 0, 1), MUX(MOUT_CLKOUT, "mout_clkout", mout_clkout_p, MISC, 8, 2), }; /* S5PV210-specific clock muxes. */ static struct samsung_mux_clock s5pv210_mux_clks[] __initdata = { MUX(MOUT_VPLL, "mout_vpll", mout_vpll_p, CLK_SRC0, 12, 1), MUX(MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, CLK_SRC1, 28, 1),
}; static struct samsung_fixed_factor_clock exynos5x_fixed_factor_clks[] __initdata = { FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0), }; static struct samsung_fixed_factor_clock exynos5800_fixed_factor_clks[] __initdata = { FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), }; static struct samsung_mux_clock exynos5800_mux_clks[] __initdata = { MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2), MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2), MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2), MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2), MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2), MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2), MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3), MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2), MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2), MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2), MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
RK3288_CLKGATE_CON(0), 4, GFLAGS), GATE(0, "c2c_host", "aclk_cpu_src", 0, RK3288_CLKGATE_CON(13), 8, GFLAGS), COMPOSITE_NOMUX(0, "crypto", "aclk_cpu_pre", 0, RK3288_CLKSEL_CON(26), 6, 2, DFLAGS, RK3288_CLKGATE_CON(5), 4, GFLAGS), GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(0), 7, GFLAGS), COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS, RK3288_CLKGATE_CON(4), 1, GFLAGS), COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(8), 0, RK3288_CLKGATE_CON(4), 2, GFLAGS), MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(4), 8, 2, MFLAGS), COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0, RK3288_CLKSEL_CON(4), 12, 1, MFLAGS, RK3288_CLKGATE_CON(4), 0, GFLAGS), GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT, RK3288_CLKGATE_CON(4), 3, GFLAGS), MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(5), 15, 1, MFLAGS), COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", 0, RK3288_CLKSEL_CON(5), 0, 7, DFLAGS, RK3288_CLKGATE_CON(4), 4, GFLAGS), COMPOSITE_FRAC(0, "spdif_frac", "spdif_src", 0, RK3288_CLKSEL_CON(9), 0, RK3288_CLKGATE_CON(4), 5, GFLAGS), COMPOSITE_NODIV(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0,
static const char * const ca53_parents[] __initconst = { "clk26m", "armca7pll", "mainpll", "univpll" }; static const char * const ca72_parents[] __initconst = { "clk26m", "armca15pll", "mainpll", "univpll" }; static const struct mtk_composite cpu_muxes[] __initconst = { MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2), MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2), }; static const struct mtk_composite top_muxes[] __initconst = { /* CLK_CFG_0 */ MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3), MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1), MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23), MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31), /* CLK_CFG_1 */ MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7), MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15), MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23), MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 24, 4, 31), /* CLK_CFG_2 */
/* fixed rate clocks generated inside the soc */ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = { FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000), FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000), FRATE(none, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), }; static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = { FFACTOR(none, "sclk_hsic_12m", "fin_pll", 1, 2, 0), }; static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { MUX(none, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2), MUX(none, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2), MUX(none, "mout_apll", apll_p, SRC_CPU, 0, 1), MUX(none, "mout_cpu", cpu_p, SRC_CPU, 16, 1), MUX(none, "mout_kpll", kpll_p, SRC_KFC, 0, 1), MUX(none, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1), MUX(none, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1), MUX_A(none, "mout_aclk400_mscl", group1_p, SRC_TOP0, 4, 2, "aclk400_mscl"), MUX(none, "mout_aclk200", group1_p, SRC_TOP0, 8, 2), MUX(none, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2), MUX(none, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2), MUX(none, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2),
FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 60000000), FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 60000000), FRATE(none, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000), FRATE(none, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000), }; /* fixed factor clocks */ struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = { FFACTOR(none, "div250", "ppll", 1, 4, 0), FFACTOR(none, "div200", "ppll", 1, 5, 0), FFACTOR(none, "div125", "div250", 1, 2, 0), }; /* mux clocks */ struct samsung_mux_clock exynos5440_mux_clks[] __initdata = { MUX(none, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1), MUX_A(arm_clk, "arm_clk", mout_armclk_p, CPU_CLK_STATUS, 0, 1, "armclk"), }; /* divider clocks */ struct samsung_div_clock exynos5440_div_clks[] __initdata = { DIV(spi_baud, "div_spi", "mout_spi", MISC_DOUT1, 3, 2), }; /* gate clocks */ struct samsung_gate_clock exynos5440_gate_clks[] __initdata = { GATE(pb0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0), GATE(pr0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0), GATE(pr1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0), GATE(b_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
/* fixed rate clocks generated inside the soc */ struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000), FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), }; struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), }; /* list of mux clocks supported in all exynos4 soc's */ struct samsung_mux_clock exynos4_mux_clks[] __initdata = { MUX_F(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, CLK_SET_RATE_PARENT, 0), MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), MUX_F(mout_g3d1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1, CLK_SET_RATE_PARENT, 0), MUX_F(mout_g3d, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1, CLK_SET_RATE_PARENT, 0), MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2), MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1), MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"), MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1), }; /* list of mux clocks supported in exynos4210 soc */ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
PNAME(mpll_p) = { "fin_pll", "fout_mpll", }; PNAME(kpll_p) = { "fin_pll", "fout_kpll", }; PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", }; PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", }; PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", }; PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", }; PNAME(mpll_bpll_p) = { "sclk_mpll_muxed", "sclk_bpll_muxed", }; PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none", "none", "none", "sclk_mpll_bpll", "none", "none", "sclk_cpll" }; static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = { MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1), MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1), MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1), MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1), MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1), MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1), MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1), MUX(0, "sclk_mpll_bpll", mpll_bpll_p, SRC_TOP1, 20, 1),
/* Process 4OP Integer instructions */ bool eval_4OP_Int(struct lilith* vm, struct Instruction* c) { #ifdef DEBUG char Name[20] = "ILLEGAL_4OP"; #endif switch(c->raw_XOP) { case 0x00: /* ADD.CI */ { #ifdef DEBUG strncpy(Name, "ADD.CI", 19); #elif TRACE record_trace("ADD.CI"); #endif ADD_CI(vm, c); break; } case 0x01: /* ADD.CO */ { #ifdef DEBUG strncpy(Name, "ADD.CO", 19); #elif TRACE record_trace("ADD.CO"); #endif ADD_CO(vm, c); break; } case 0x02: /* ADD.CIO */ { #ifdef DEBUG strncpy(Name, "ADD.CIO", 19); #elif TRACE record_trace("ADD.CIO"); #endif ADD_CIO(vm, c); break; } case 0x03: /* ADDU.CI */ { #ifdef DEBUG strncpy(Name, "ADDU.CI", 19); #elif TRACE record_trace("ADDU.CI"); #endif ADDU_CI(vm, c); break; } case 0x04: /* ADDU.CO */ { #ifdef DEBUG strncpy(Name, "ADDU.CO", 19); #elif TRACE record_trace("ADDU.CO"); #endif ADDU_CO(vm, c); break; } case 0x05: /* ADDU.CIO */ { #ifdef DEBUG strncpy(Name, "ADDU.CIO", 19); #elif TRACE record_trace("ADDU.CIO"); #endif ADDU_CIO(vm, c); break; } case 0x06: /* SUB.BI */ { #ifdef DEBUG strncpy(Name, "SUB.BI", 19); #elif TRACE record_trace("SUB.BI"); #endif SUB_BI(vm, c); break; } case 0x07: /* SUB.BO */ { #ifdef DEBUG strncpy(Name, "SUB.BO", 19); #elif TRACE record_trace("SUB.BO"); #endif SUB_BO(vm, c); break; } case 0x08: /* SUB.BIO */ { #ifdef DEBUG strncpy(Name, "SUB.BIO", 19); #elif TRACE record_trace("SUB.BIO"); #endif SUB_BIO(vm, c); break; } case 0x09: /* SUBU.BI */ { #ifdef DEBUG strncpy(Name, "SUBU.BI", 19); #elif TRACE record_trace("SUBU.BI"); #endif SUBU_BI(vm, c); break; } case 0x0A: /* SUBU.BO */ { #ifdef DEBUG strncpy(Name, "SUBU.BO", 19); #elif TRACE record_trace("SUBU.BO"); #endif SUBU_BO(vm, c); break; } case 0x0B: /* SUBU.BIO */ { #ifdef DEBUG strncpy(Name, "SUBU.BIO", 19); #elif TRACE record_trace("SUBU.BIO"); #endif SUBU_BIO(vm, c); break; } case 0x0C: /* MULTIPLY */ { #ifdef DEBUG strncpy(Name, "MULTIPLY", 19); #elif TRACE record_trace("MULTIPLY"); #endif MULTIPLY(vm, c); break; } case 0x0D: /* MULTIPLYU */ { #ifdef DEBUG strncpy(Name, "MULTIPLYU", 19); #elif TRACE record_trace("MULTIPLYU"); #endif MULTIPLYU(vm, c); break; } case 0x0E: /* DIVIDE */ { #ifdef DEBUG strncpy(Name, "DIVIDE", 19); #elif TRACE record_trace("DIVIDE"); #endif DIVIDE(vm, c); break; } case 0x0F: /* DIVIDEU */ { #ifdef DEBUG strncpy(Name, "DIVIDEU", 19); #elif TRACE record_trace("DIVIDEU"); #endif DIVIDEU(vm, c); break; } case 0x10: /* MUX */ { #ifdef DEBUG strncpy(Name, "MUX", 19); #elif TRACE record_trace("MUX"); #endif MUX(vm, c); break; } case 0x11: /* NMUX */ { #ifdef DEBUG strncpy(Name, "NMUX", 19); #elif TRACE record_trace("NMUX"); #endif NMUX(vm, c); break; } case 0x12: /* SORT */ { #ifdef DEBUG strncpy(Name, "SORT", 19); #elif TRACE record_trace("SORT"); #endif SORT(vm, c); break; } case 0x13: /* SORTU */ { #ifdef DEBUG strncpy(Name, "SORTU", 19); #elif TRACE record_trace("SORTU"); #endif SORTU(vm, c); break; } default: { illegal_instruction(vm, c); break; } } #ifdef DEBUG fprintf(stdout, "# %s reg%u reg%u reg%u reg%u\n", Name, c->reg0, c->reg1, c->reg2, c->reg3); #endif return false; }
/* fixed rate clocks generated inside the soc */ static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = { FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), FRATE(0, "sclk_hdmi27m", NULL, 0, 27000000), FRATE(0, "sclk_dptxphy", NULL, 0, 24000000), FRATE(0, "sclk_uhostphy", NULL, 0, 48000000), }; static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0), FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0), }; static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = { MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1), }; static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { /* * NOTE: Following table is sorted by (clock domain, register address, * bitfield shift) triplet in ascending order. When adding new entries, * please make sure that the order is kept, to avoid merge conflicts * and make further work with defined data easier. */ /* * CMU_CPU */ MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, CLK_SET_RATE_PARENT, 0, "mout_apll"),