static void setup_epdc(void) { /*** epdc Maxim PMIC settings ***/ /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */ imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */ imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* Set pixel clock rates for EPDC in clock.c */ panel_info.epdc_data.wv_modes.mode_init = 0; panel_info.epdc_data.wv_modes.mode_du = 1; panel_info.epdc_data.wv_modes.mode_gc4 = 3; panel_info.epdc_data.wv_modes.mode_gc8 = 2; panel_info.epdc_data.wv_modes.mode_gc16 = 2; panel_info.epdc_data.wv_modes.mode_gc32 = 2; panel_info.epdc_data.epdc_timings = panel_timings; setup_epdc_power(); }
static void setup_epdc_power(void) { /* Setup epdc voltage */ /* EIM_A17 - GPIO2[21] for PWR_GOOD status */ imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* Set as input */ gpio_direction_input(IMX_GPIO_NR(2, 21)); /* EIM_D17 - GPIO3[17] for VCOM control */ imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* Set as output */ gpio_direction_output(IMX_GPIO_NR(3, 17), 1); /* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */ imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* Set as output */ gpio_direction_output(IMX_GPIO_NR(3, 20), 1); /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* Set as output */ gpio_direction_output(IMX_GPIO_NR(2, 20), 1); }
static void setup_epdc_power(void) { /* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */ struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0); /* Setup epdc voltage */ /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); gpio_direction_input(IMX_GPIO_NR(2, 31)); /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* Set as output */ gpio_direction_output(IMX_GPIO_NR(4, 14), 1); /* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */ imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* Set as output */ gpio_direction_output(IMX_GPIO_NR(2, 23), 1); /* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */ imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* Set as output */ gpio_direction_output(IMX_GPIO_NR(2, 30), 1); }
static void setup_epdc_power(void) { /* Setup epdc voltage */ /* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */ imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRSTAT__GPIO_2_13 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); gpio_direction_input(IMX_GPIO_NR(2, 13)); /* EPDC_VCOM0 - GPIO2[3] for VCOM control */ imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO_2_3 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* Set as output */ gpio_direction_output(IMX_GPIO_NR(2, 3), 1); /* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */ imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* Set as output */ gpio_direction_output(IMX_GPIO_NR(2, 14), 1); /* EPDC_PWRCTRL0 - GPIO2[7] for EPD PWR CTL0 */ imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* Set as output */ gpio_direction_output(IMX_GPIO_NR(2, 7), 1); }
static void setup_iomux_uart(void) { static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); }
static int cm_fx6_setup_usb_host(void) { int err; err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst"); if (err) return err; SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)); SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)); return 0; }
static void mx50_suspend_exit() { iomux_v3_cfg_t iomux_setting = (MX50_PAD_ECSPI2_SCLK__GPIO_4_16 & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(0x84); /* Power Up the band-gap and set the SELFBIAS bit. */ __raw_writel(MXC_ANADIG_REF_PWD, apll_base + MXC_ANADIG_MISC_CLR); udelay(100); __raw_writel(MXC_ANADIG_REF_SELFBIAS_OFF, apll_base + MXC_ANADIG_MISC_SET); //if (board_is_mx50_rd3()) { /* Enable the Pull/keeper */ mxc_iomux_v3_setup_pad(iomux_setting); gpio_request(DCDC_EN, "dcdc-en"); gpio_direction_output(DCDC_EN, 1); //} mxc_iomux_v3_setup_multiple_pads(suspend_exit_pads, ARRAY_SIZE(suspend_exit_pads)); nimbus_gpio_iomux_init(); }
static void nimbus_gpio_iomux_init() { iomux_v3_cfg_t iomux_setting; iomux_setting = (MX50_PAD_ECSPI2_SCLK__GPIO_4_16 & \ ~MUX_PAD_CTRL_MASK) | \ MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_DSE_HIGH); /* Enable the Pull/keeper */ mxc_iomux_v3_setup_pad(iomux_setting); nimbus_led_ctrl(LEDID_WLAN,0,0); nimbus_led_ctrl(LEDID_WIFI,0,0); nimbus_led_ctrl(LEDID_CHARGER_RED,0,0); nimbus_led_ctrl(LEDID_CHARGER_GREEN,0,0); #if 0 if( gpio_get_value(SD1_CHANGE_FOUND)==0) { printk("Found SD changed during suspending.\n"); } gpio_direction_output(SD1_CHANGE_CLEAR,1); mdelay(1); gpio_direction_output(SD1_CHANGE_CLEAR,0); #endif }
static int cm_fx6_init_usb_otg(void) { int ret; struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; ret = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr"); if (ret) { printf("USB OTG pwr gpio request failed: %d\n", ret); return ret; } SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL)); SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLDOWN)); clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK); /* disable ext. charger detect, or it'll affect signal quality at dp. */ return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0); }
int board_eth_init(bd_t *bis) { struct phy_device *phydev; struct mii_dev *bus; unsigned short id1, id2; int ret; iomux_v3_cfg_t enet_reset = MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL); /* check whether KSZ9031 or AR8035 has to be configured */ imx_iomux_v3_setup_multiple_pads(enet_pads_ar8035, ARRAY_SIZE(enet_pads_ar8035)); imx_iomux_v3_setup_pad(enet_reset); /* phy reset */ gpio_direction_output(IMX_GPIO_NR(3, 23), 0); udelay(2000); gpio_set_value(IMX_GPIO_NR(3, 23), 1); udelay(500); bus = fec_get_miibus(IMX_FEC_BASE, -1); if (!bus) return -EINVAL; phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); if (!phydev) { printf("Error: phy device not found.\n"); ret = -ENODEV; goto free_bus; } /* get the PHY id */ id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) { /* re-configure for Micrel KSZ9031 */ printf("configure Micrel KSZ9031 Ethernet Phy at address %d\n", phydev->addr); /* phy reset: gpio3-23 */ gpio_set_value(IMX_GPIO_NR(3, 23), 0); gpio_set_value(IMX_GPIO_NR(6, 30), (phydev->addr >> 2)); gpio_set_value(IMX_GPIO_NR(6, 25), 1); gpio_set_value(IMX_GPIO_NR(6, 27), 1); gpio_set_value(IMX_GPIO_NR(6, 28), 1); gpio_set_value(IMX_GPIO_NR(6, 29), 1); imx_iomux_v3_setup_multiple_pads(enet_pads_ksz9031, ARRAY_SIZE(enet_pads_ksz9031)); gpio_set_value(IMX_GPIO_NR(6, 24), 1); udelay(500); gpio_set_value(IMX_GPIO_NR(3, 23), 1); imx_iomux_v3_setup_multiple_pads(enet_pads_final_ksz9031, ARRAY_SIZE(enet_pads_final_ksz9031)); } else if ((id1 == 0x004d) && (id2 == 0xd072)) {
/* * Board specific initialization. */ static void __init mx51_babbage_init(void) { iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 | MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP); imx51_soc_init(); #if defined(CONFIG_CPU_FREQ_IMX) get_cpu_op = mx51_get_cpu_op; #endif mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, ARRAY_SIZE(mx51babbage_pads)); imx51_add_imx_uart(0, &uart_pdata); imx51_add_imx_uart(1, NULL); imx51_add_imx_uart(2, &uart_pdata); babbage_fec_reset(); imx51_add_fec(NULL); /* Set the PAD settings for the pwr key. */ mxc_iomux_v3_setup_pad(power_key); imx_add_gpio_keys(&imx_button_data); imx51_add_imx_i2c(0, &babbage_i2c_data); imx51_add_imx_i2c(1, &babbage_i2c_data); mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data); if (otg_mode_host) mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); else { initialize_otg_port(NULL); mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata); } gpio_usbh1_active(); mxc_register_device(&mxc_usbh1_device, &usbh1_config); /* setback USBH1_STP to be function */ mxc_iomux_v3_setup_pad(usbh1stp); babbage_usbhub_reset(); imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data); imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data); spi_register_board_info(mx51_babbage_spi_board_info, ARRAY_SIZE(mx51_babbage_spi_board_info)); imx51_add_ecspi(0, &mx51_babbage_spi_pdata); imx51_add_imx2_wdt(0, NULL); }
static int cm_fx6_usb_hub_reset(void) { int err; err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst"); if (err) { printf("USB hub rst gpio request failed: %d\n", err); return -1; } SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)); gpio_direction_output(CM_FX6_USB_HUB_RST, 0); udelay(10); gpio_direction_output(CM_FX6_USB_HUB_RST, 1); mdelay(1); return 0; }
int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)); gpio_direction_output(IMX_GPIO_NR(2, 4), 0); /* Set Low */ gpio_set_value(IMX_GPIO_NR(2, 4), 0); udelay(1000); /* Set High */ gpio_set_value(IMX_GPIO_NR(2, 4), 1); return 0; }
int board_ehci_hcd_init(int port) { u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4); switch (port) { case 0: return cm_fx6_init_usb_otg(); case 1: SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)); /* Set PWR polarity to match power switch's enable polarity */ setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL); return cm_fx6_usb_hub_reset(); default: break; } return 0; }
static void mx50_suspend_enter() { iomux_v3_cfg_t *p = suspend_enter_pads; int i; iomux_v3_cfg_t iomux_setting = (MX50_PAD_ECSPI2_SCLK__GPIO_4_16 & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(0x84); /* Clear the SELF_BIAS bit and power down * the band-gap. */ __raw_writel(MXC_ANADIG_REF_SELFBIAS_OFF, apll_base + MXC_ANADIG_MISC_CLR); __raw_writel(MXC_ANADIG_REF_PWD, apll_base + MXC_ANADIG_MISC_SET); //if (board_is_mx50_rd3()) { /* Enable the Pull/keeper */ mxc_iomux_v3_setup_pad(iomux_setting); gpio_request(DCDC_EN, "dcdc-en"); gpio_direction_output(DCDC_EN, 0); //} /* Set PADCTRL to 0 for all IOMUX. */ for (i = 0; i < ARRAY_SIZE(suspend_enter_pads); i++) { suspend_exit_pads[i] = *p; *p &= ~MUX_PAD_CTRL_MASK; p++; } mxc_iomux_v3_get_multiple_pads(suspend_exit_pads, ARRAY_SIZE(suspend_exit_pads)); mxc_iomux_v3_setup_multiple_pads(suspend_enter_pads, ARRAY_SIZE(suspend_enter_pads)); nimbus_gpio_iomux_deinit(); //system_status=2; }
static void nimbus_gpio_iomux_deinit() { iomux_v3_cfg_t iomux_setting; iomux_setting = (MX50_PAD_ECSPI2_SCLK__GPIO_4_16 & \ ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(0x4); mxc_iomux_v3_setup_pad(iomux_setting); nimbus_led_ctrl(LEDID_WLAN,0,0); nimbus_led_ctrl(LEDID_WIFI,0,0); nimbus_led_ctrl(LEDID_CHARGER_RED,0,0); nimbus_led_ctrl(LEDID_CHARGER_GREEN,0,0); #if 0 printk("Clear SD changer before suspending.\n"); gpio_direction_output(SD1_CHANGE_CLEAR,1); mdelay(1); gpio_direction_output(SD1_CHANGE_CLEAR,0); #endif }
.i2c_mode = MX7D_PAD_I2C2_SDA__I2C2_SDA | PC, .gpio_mode = MX7D_PAD_I2C2_SDA__GPIO4_IO11 | PC, .gp = IMX_GPIO_NR(4, 11), }, }; #endif int dram_init(void) { gd->ram_size = PHYS_SDRAM_SIZE; return 0; } static iomux_v3_cfg_t const uart1_pads[] = { MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; static iomux_v3_cfg_t const usdhc1_pads[] = { MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX7D_PAD_GPIO1_IO08__SD1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; } iomux_v3_cfg_t const uart4_pads[] = { MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1); mdelay(10); } for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) { gpio_direction_output(cm_fx6_issd_gpios[i], on); udelay(100); } if (!on) /* for compatibility lower the power loss interrupt */ gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); } static iomux_v3_cfg_t const sata_pads[] = { /* SATA PWR */ IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)), IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* SATA CTRL */ IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)), IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)), IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; static void cm_fx6_setup_issd(void) { SETUP_IOMUX_PADS(sata_pads); /* Make sure this gpio has logical 0 value */
#include <asm/mach/map.h> #include <mach/hardware.h> #include <mach/common.h> #include <mach/iomux-mx51.h> #include <mach/audmux.h> #include "devices-imx51.h" #include "devices.h" static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { /* LED */ MX51_PAD_NANDF_D10__GPIO3_30, /* SWITCH */ _MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), /* UART2 */ MX51_PAD_UART2_RXD__UART2_RXD, MX51_PAD_UART2_TXD__UART2_TXD, /* UART 3 */ MX51_PAD_UART3_RXD__UART3_RXD, MX51_PAD_UART3_TXD__UART3_TXD, MX51_PAD_KEY_COL4__UART3_RTS, MX51_PAD_KEY_COL5__UART3_CTS, /* SD */ MX51_PAD_SD1_CMD__SD1_CMD, MX51_PAD_SD1_CLK__SD1_CLK, MX51_PAD_SD1_DATA0__SD1_DATA0, MX51_PAD_SD1_DATA1__SD1_DATA1, MX51_PAD_SD1_DATA2__SD1_DATA2,
PAD_CTL_DSE_40ohm | PAD_CTL_HYS) #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) #define ETH_PHY_RESET IMX_GPIO_NR(4, 21) int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; } static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; static iomux_v3_cfg_t const usdhc1_pads[] = { /* 8 bit SD */ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) #define IOX_SDI IMX_GPIO_NR(5, 10) #define IOX_STCP IMX_GPIO_NR(5, 7) #define IOX_SHCP IMX_GPIO_NR(5, 11) #define IOX_OE IMX_GPIO_NR(5, 8) static iomux_v3_cfg_t const iox_pads[] = { /* IOX_SDI */ MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), /* IOX_SHCP */ MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* IOX_STCP */ MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), /* IOX_nOE */ MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), }; /* * HDMI_nRST --> Q0 * ENET1_nRST --> Q1 * ENET2_nRST --> Q2 * CAN1_2_STBY --> Q3 * BT_nPWD --> Q4 * CSI_RST --> Q5
.i2c_mode = MX6SX_PAD_KEY_ROW4__I2C3_SDA | PC, .gpio_mode = MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 | PC, .gp = IMX_GPIO_NR(2, 19), }, }; #endif int dram_init(void) { gd->ram_size = PHYS_SDRAM_SIZE; return 0; } static iomux_v3_cfg_t const uart1_pads[] = { MX6SX_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), MX6SX_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; static iomux_v3_cfg_t const usdhc3_pads[] = { MX6SX_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6SX_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
if (bank1_size == 0x20000000) return 0; spl_mx6q_dram_init(DDR_16BIT_256MB, true); bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); if (bank1_size == 0x10000000) return 0; break; } return -1; } static iomux_v3_cfg_t const uart4_pads[] = { IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), }; static void cm_fx6_setup_uart(void) { SETUP_IOMUX_PADS(uart4_pads); enable_uart_clk(1); } #ifdef CONFIG_SPL_SPI_SUPPORT static void cm_fx6_setup_ecspi(void) { cm_fx6_set_ecspi_iomux(); enable_spi_clk(1, 0); }
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) #define I2C_PMIC 1 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) int dram_init(void) { gd->ram_size = imx_ddr_size(); return 0; } static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; static iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
PAD_CTL_ODE | PAD_CTL_SRE_FAST) #define I2C_PMIC 1 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) #define DISP0_PWR_EN IMX_GPIO_NR(1, 21) int dram_init(void) { gd->ram_size = imx_ddr_size(); return 0; } static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; static iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
#include <asm/arch/crm_regs.h> #include <asm/arch/iomux.h> #include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/sys_proto.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/video.h> #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) static iomux_v3_cfg_t const uart_pads[] = { #ifdef CONFIG_MX6QDL IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), #elif CONFIG_MX6UL IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)), IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)), #endif }; #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { if (is_mx6dq() && !strcmp(name, "imx6q-icore")) return 0; else if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs")) return 0; else if (is_mx6dq() && !strcmp(name, "imx6q-icore-mipi"))
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; } iomux_v3_cfg_t const uart4_pads[] = { MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; } iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const uart2_pads[] = { MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) /* I2C1, SGTL5000 */ struct i2c_pads_info i2c_pad_info0 = { .scl = { .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC,
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, MX51_PAD_CSPI1_MISO__ECSPI1_MISO, MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, MX51_PAD_CSPI1_SS0__GPIO4_24, /* nCS */ MX51_PAD_CSI2_PIXCLK__GPIO4_15, /* nReset */ MX51_PAD_GPIO1_1__GPIO1_1, /* IRQ */ MX51_PAD_GPIO1_4__GPIO1_4, /* Control signals */ MX51_PAD_GPIO1_6__GPIO1_6, MX51_PAD_GPIO1_7__GPIO1_7, MX51_PAD_GPIO1_8__GPIO1_8, MX51_PAD_GPIO1_9__GPIO1_9, /* Touchscreen */ /* IRQ */ _MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), }; static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; static struct tsc2007_platform_data tsc2007_info = { .model = 2007, .x_plate_ohms = 180, }; static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = { { I2C_BOARD_INFO("pcf8563", 0x51),