void PlatformDisableHostL0s(struct net_device *dev) { struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); u32 PciCfgAddrPort=0; u8 Num4Bytes; u8 uPciBridgeASPMSetting = 0; if( (priv->NdisAdapter.BusNumber == 0xff && priv->NdisAdapter.DevNumber == 0xff && priv->NdisAdapter.FuncNumber == 0xff) || (priv->NdisAdapter.PciBridgeBusNum == 0xff && priv->NdisAdapter.PciBridgeDevNum == 0xff && priv->NdisAdapter.PciBridgeFuncNum == 0xff) ) { printk("PlatformDisableHostL0s(): Fail to enable ASPM. " "Cannot find the Bus of PCI(Bridge).\n"); return; } PciCfgAddrPort= (priv->NdisAdapter.PciBridgeBusNum << 16)| (priv->NdisAdapter.PciBridgeDevNum<< 11)| (priv->NdisAdapter.PciBridgeFuncNum << 8)|(1 << 31); Num4Bytes = (priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10)/4; NdisRawWritePortUlong(PCI_CONF_ADDRESS , PciCfgAddrPort+(Num4Bytes << 2)); NdisRawReadPortUchar(PCI_CONF_DATA, &uPciBridgeASPMSetting); if(uPciBridgeASPMSetting & BIT0) uPciBridgeASPMSetting &= ~(BIT0); NdisRawWritePortUlong(PCI_CONF_ADDRESS , PciCfgAddrPort+(Num4Bytes << 2)); NdisRawWritePortUchar(PCI_CONF_DATA, uPciBridgeASPMSetting); udelay(50); printk("PlatformDisableHostL0s():PciBridge BusNumber[%x], " "DevNumbe[%x], FuncNumber[%x], Write reg[%x] = %x\n", priv->NdisAdapter.PciBridgeBusNum, priv->NdisAdapter.PciBridgeDevNum, priv->NdisAdapter.PciBridgeFuncNum, (priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10), (priv->NdisAdapter.PciBridgeLinkCtrlReg | (priv->RegDevicePciASPMSetting&~BIT0))); }
uint cf_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) { _irqL irqL; u32 i, w_cnt, loop_cnt; _adapter* adapter = (_adapter*)(pintfhdl->adapter); struct intf_priv *pintfpriv = pintfhdl->pintfpriv; u32 *pdata = (u32 *)wmem; u32 maxlen = pintfpriv->max_xmitsz; struct dvobj_priv * pcfiodev = (struct dvobj_priv * )(pintfpriv->intf_dev); u32 iobase_addr = pcfiodev->io_base_address; // Please remember, you just can't only use lock/unlock to // protect the rw functions... // since, i/o is quite common in call-back and isr routines... _func_enter_; if ((cnt == 0) || (addr != HWFF0DR)) { _func_exit_; return _SUCCESS; } //_enter_critical(&pintfpriv->rwlock, &irqL); #ifdef PLATFORM_WINDOWS addr = (addr&0x00003FFF);//Convert addr to CFIO Interface local offset addr do { w_cnt = (cnt > maxlen) ? maxlen: cnt;//actually cnt must be <= maxlen loop_cnt = (w_cnt/4) + (((w_cnt%4) >0)?1:0); for(i=0; i<loop_cnt; i++) { NdisRawWritePortUlong((u32)(iobase_addr+addr), (u32)(*pdata)); pdata++; } cnt -= w_cnt; }while(cnt > 0); #endif //_exit_critical(&pintfpriv->rwlock, &irqL); _func_exit_; return _SUCCESS; }
void cf_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val) { _irqL irqL; uint res; struct _SyncContext synccontext; struct intf_priv *pintfpriv = pintfhdl->pintfpriv; struct dvobj_priv * pcfiodev = (struct dvobj_priv * )(pintfpriv->intf_dev); u32 iobase_addr = pcfiodev->io_base_address; _func_enter_; _enter_hwio_critical(&pintfpriv->rwlock, &irqL); #ifdef PLATFORM_WINDOWS if( addr >= RTL8711_HCICTRL_ && addr <= (RTL8711_HCICTRL_+0x1FFFF) ) { //the address is in HCI local register addr = (addr&0x00003FFF); NdisRawWritePortUlong((u32)(iobase_addr+addr), val); }else{ synccontext.pintfpriv = pintfpriv; synccontext.lbusaddr = addr; synccontext.bytecnt = 4; // 4-byte synccontext.pdata=(u8 *)&val; irqL = KeGetCurrentIrql(); if ( irqL <= DISPATCH_LEVEL ) res = NdisMSynchronizeWithInterrupt(&pcfiodev->interrupt, cfbus_write, (void *)&synccontext); else//IRQL > DISPATCH_LEVEL res = cfbus_write((void *)&synccontext); } #endif _exit_hwio_critical(&pintfpriv->rwlock, &irqL); _func_exit_; }
void PlatformEnableASPM(struct net_device *dev) { struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->rtllib->PowerSaveControl)); u16 ASPMLevel = 0; u32 PciCfgAddrPort=0; u8 Num4Bytes; u8 uPciBridgeASPMSetting = 0; u8 uDeviceASPMSetting = 0; if( (priv->NdisAdapter.BusNumber == 0xff && priv->NdisAdapter.DevNumber == 0xff && priv->NdisAdapter.FuncNumber == 0xff) || (priv->NdisAdapter.PciBridgeBusNum == 0xff && priv->NdisAdapter.PciBridgeDevNum == 0xff && priv->NdisAdapter.PciBridgeFuncNum == 0xff) ) { RT_TRACE(COMP_INIT, "PlatformEnableASPM(): Fail to enable ASPM." " Cannot find the Bus of PCI(Bridge).\n"); return; } #ifdef RTL8192SE if(priv->NdisAdapter.PciBridgeVendor != PCI_BRIDGE_VENDOR_INTEL) { RT_TRACE(COMP_POWER, "%s(): Dont modify ASPM for non intel " "chipset. For Bridge Vendor %d.\n" ,__func__,priv->NdisAdapter.PciBridgeVendor); return; } #endif #ifdef RTL8192CE PciCfgAddrPort= (priv->NdisAdapter.PciBridgeBusNum << 16)| (priv->NdisAdapter.PciBridgeDevNum<< 11) | (priv->NdisAdapter.PciBridgeFuncNum << 8)|(1 << 31); Num4Bytes = (priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10)/4; NdisRawWritePortUlong(PCI_CONF_ADDRESS , PciCfgAddrPort+(Num4Bytes << 2)); uPciBridgeASPMSetting = priv->NdisAdapter.PciBridgeLinkCtrlReg | priv->RegHostPciASPMSetting; if(priv->NdisAdapter.PciBridgeVendor == PCI_BRIDGE_VENDOR_INTEL) uPciBridgeASPMSetting &= ~ BIT0; NdisRawWritePortUchar(PCI_CONF_DATA, uPciBridgeASPMSetting); RT_TRACE(COMP_INIT, "PlatformEnableASPM():PciBridge BusNumber[%x], " "DevNumbe[%x], FuncNumber[%x], Write reg[%x] = %x\n", priv->NdisAdapter.PciBridgeBusNum, priv->NdisAdapter.PciBridgeDevNum, priv->NdisAdapter.PciBridgeFuncNum, (priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10), uPciBridgeASPMSetting); udelay(50); #endif ASPMLevel |= priv->RegDevicePciASPMSetting; uDeviceASPMSetting = priv->NdisAdapter.LinkCtrlReg; #ifdef RTL8192SE if(priv->CustomerID == RT_CID_TOSHIBA && priv->NdisAdapter.PciBridgeVendor == PCI_BRIDGE_VENDOR_AMD) { if(priv->NdisAdapter.LinkCtrlReg & BIT1) uDeviceASPMSetting |= BIT0; else uDeviceASPMSetting |= ASPMLevel; } else #endif uDeviceASPMSetting |= ASPMLevel; PlatformSwitchDevicePciASPM(dev, uDeviceASPMSetting); if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_CLK_REQ) { PlatformSwitchClkReq(dev,(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0); RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_CLK_REQ); } udelay(100); #ifdef RTL8192SE PciCfgAddrPort= (priv->NdisAdapter.PciBridgeBusNum << 16)| (priv->NdisAdapter.PciBridgeDevNum<< 11)| (priv->NdisAdapter.PciBridgeFuncNum << 8)|(1 << 31); Num4Bytes = (priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10)/4; NdisRawWritePortUlong(PCI_CONF_ADDRESS , PciCfgAddrPort+(Num4Bytes << 2)); uPciBridgeASPMSetting = priv->NdisAdapter.PciBridgeLinkCtrlReg | priv->RegHostPciASPMSetting; if(priv->CustomerID == RT_CID_TOSHIBA && priv->NdisAdapter.PciBridgeVendor == PCI_BRIDGE_VENDOR_AMD && pPSC->RegAMDPciASPM) { if(priv->NdisAdapter.PciBridgeLinkCtrlReg & BIT1) uPciBridgeASPMSetting |= BIT0; } else if(priv->NdisAdapter.PciBridgeVendor == PCI_BRIDGE_VENDOR_INTEL ) { uPciBridgeASPMSetting &= ~ BIT0; } NdisRawWritePortUchar(PCI_CONF_DATA, uPciBridgeASPMSetting); RT_TRACE(COMP_INIT, "%s:PciBridge BusNumber[%x], DevNumbe[%x], " "FuncNumber[%x], Write reg[%x] = %x\n",__func__, priv->NdisAdapter.PciBridgeBusNum, priv->NdisAdapter.PciBridgeDevNum, priv->NdisAdapter.PciBridgeFuncNum, (priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10), uPciBridgeASPMSetting); #endif udelay(100); }
void PlatformDisableASPM(struct net_device *dev) { struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->rtllib->PowerSaveControl)); u32 PciCfgAddrPort=0; u8 Num4Bytes; u8 LinkCtrlReg; u16 PciBridgeLinkCtrlReg, ASPMLevel=0; if( (priv->NdisAdapter.BusNumber == 0xff && priv->NdisAdapter.DevNumber == 0xff && priv->NdisAdapter.FuncNumber == 0xff) || (priv->NdisAdapter.PciBridgeBusNum == 0xff && priv->NdisAdapter.PciBridgeDevNum == 0xff && priv->NdisAdapter.PciBridgeFuncNum == 0xff) ) { RT_TRACE(COMP_INIT, "PlatformEnableASPM(): Fail to enable ASPM." " Cannot find the Bus of PCI(Bridge).\n"); return; } #ifdef RTL8192SE if(priv->NdisAdapter.PciBridgeVendor != PCI_BRIDGE_VENDOR_INTEL) { RT_TRACE(COMP_POWER, "%s(): Dont modify ASPM for non intel " "chipset. For Bridge Vendor %d.\n" ,__func__,priv->NdisAdapter.PciBridgeVendor); return; } #endif #ifdef RTL8192CE if(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_CLK_REQ) { RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_CLK_REQ); PlatformSwitchClkReq(dev, 0x0); } { u8 tmpU1b; pci_read_config_byte(priv->pdev, 0x80, &tmpU1b); } #endif LinkCtrlReg = priv->NdisAdapter.LinkCtrlReg; PciBridgeLinkCtrlReg = priv->NdisAdapter.PciBridgeLinkCtrlReg; ASPMLevel |= BIT0|BIT1; LinkCtrlReg &=~ASPMLevel; PciBridgeLinkCtrlReg &=~(BIT0|BIT1); #ifdef RTL8192CE PlatformSwitchDevicePciASPM(dev, LinkCtrlReg); udelay( 50); #endif PciCfgAddrPort= (priv->NdisAdapter.PciBridgeBusNum << 16)| (priv->NdisAdapter.PciBridgeDevNum<< 11)| (priv->NdisAdapter.PciBridgeFuncNum << 8)|(1 << 31); Num4Bytes = (priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10)/4; NdisRawWritePortUlong(PCI_CONF_ADDRESS , PciCfgAddrPort+(Num4Bytes << 2)); NdisRawWritePortUchar(PCI_CONF_DATA, PciBridgeLinkCtrlReg); RT_TRACE(COMP_POWER, "%s:PciBridge BusNumber[%x], " "DevNumbe[%x], FuncNumber[%x], Write reg[%x] = %x\n", __func__, priv->NdisAdapter.PciBridgeBusNum, priv->NdisAdapter.PciBridgeDevNum, priv->NdisAdapter.PciBridgeFuncNum, (priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10), PciBridgeLinkCtrlReg); udelay(50); #ifdef RTL8192SE PlatformSwitchDevicePciASPM(dev, LinkCtrlReg); PlatformSwitchClkReq(dev, 0x0); if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_CLK_REQ) RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_CLK_REQ); udelay(100); #endif }
static uint cfbus_read(void *context) { #ifdef PLATFORM_WINDOWS u32 iobase_addr, len, addr, HAARValue, Read_Data; u8 *pdata; USHORT readCF_HAAR; u32 counter=0; struct _SyncContext *psynccontext = (struct _SyncContext *)context; struct intf_priv *pintfpriv = (struct intf_priv *)psynccontext->pintfpriv; struct dvobj_priv * pcfiodev = (struct dvobj_priv *)pintfpriv->intf_dev; //u8 *rwmem = (u8 *)pintfpriv->rw_mem; iobase_addr = pcfiodev->io_base_address; len = psynccontext ->bytecnt; addr = psynccontext->lbusaddr; pdata = psynccontext->pdata; _func_enter_; //if the address is in HCI local register, to skip it if( addr >= RTL8711_HCICTRL_ && addr <= (RTL8711_HCICTRL_+0x1FFFF) ) { _func_exit_; return _FAIL; } HAARValue = HAARSetting(len, IO_READ, addr); // 1.Write HAAR NdisRawWritePortUlong( (ULONG)(iobase_addr+HAAR), HAARValue); // 2.Polling HAAR Ready do { if(counter > HAAR_POLLING_CNT){ //RT_TRACE(COMP_DBG, DBG_LOUD, ("\n\nCFIOReadReg: Poll HAAR Ready too long, LBus = 0x%X checkRegRWCnt(1) = %d currentIRQL = %x, read HAAR=%x, HAARValue=%x.\n\n",c->LexraBusAddr, checkRegRWCnt, currentIRQL, test32, HAARValue )); _func_exit_; return _FAIL; } if(addr == CR9346) NdisStallExecution(50); //Considering CFIO default mode is 16-bit mode, we use 16-bit reading NdisRawReadPortUshort( (ULONG)(iobase_addr+HAAR+0x0002), &readCF_HAAR); counter++; }while(((readCF_HAAR >> 14) & 0x3) != 0x3); //while READY has not been set // 3.Read HRADR NdisRawReadPortUlong( (ULONG)(iobase_addr+HRADR), (ULONG *)&Read_Data); NdisMoveMemory(pdata , (u8 *)&Read_Data, len); #endif _func_exit_; return _SUCCESS; }
PU8 C_DM9000::DeviceWriteString( PU8 ptrBuffer, int nLength) { int count; count = (nLength + m_nIoMaxPad) / m_nIoMode; #if defined(PREEMPTIVE_TX_WRITE) switch (m_nIoMode) { case BYTE_MODE: { PU8 pcurr=(PU8)ptrBuffer; for(;count--;pcurr++) { ENTER_CRITICAL_SECTION VALIDATE_ADDR_PORT(DM9_MWCMD); NdisRawWritePortUchar( m_szCurrentSettings[SID_PORT_BASE_ADDRESS] + DM9000_DATA_OFFSET, *pcurr); LEAVE_CRITICAL_SECTION } } break; case WORD_MODE: { PU16 pcurr=(PU16)ptrBuffer; for(;count--;pcurr++) { ENTER_CRITICAL_SECTION VALIDATE_ADDR_PORT(DM9_MWCMD); NdisRawWritePortUshort( m_szCurrentSettings[SID_PORT_BASE_ADDRESS] + DM9000_DATA_OFFSET, *pcurr); LEAVE_CRITICAL_SECTION } } break; case DWORD_MODE: { PU32 pcurr=(PU32)ptrBuffer; for(;count--;pcurr++) { ENTER_CRITICAL_SECTION VALIDATE_ADDR_PORT(DM9_MWCMD); NdisRawWritePortUlong( m_szCurrentSettings[SID_PORT_BASE_ADDRESS] + DM9000_DATA_OFFSET, *pcurr); LEAVE_CRITICAL_SECTION } } break; default: break; } // of switch #else // !PREEMPTIVE_TX_WRITE // select port to be read from ENTER_CRITICAL_SECTION VALIDATE_ADDR_PORT(DM9_MWCMD); switch (m_nIoMode) { case BYTE_MODE: NdisRawWritePortBufferUchar( m_szCurrentSettings[SID_PORT_BASE_ADDRESS] + DM9000_DATA_OFFSET, ptrBuffer,count); break; case WORD_MODE: NdisRawWritePortBufferUshort( m_szCurrentSettings[SID_PORT_BASE_ADDRESS] + DM9000_DATA_OFFSET, (PU16)ptrBuffer,count); break; case DWORD_MODE: NdisRawWritePortBufferUlong( m_szCurrentSettings[SID_PORT_BASE_ADDRESS] + DM9000_DATA_OFFSET, (PU32)ptrBuffer,count); break; default: break; } // of switch LEAVE_CRITICAL_SECTION #endif return ptrBuffer; }