VOID STATIC PciePortInitCallback ( IN PCIe_ENGINE_CONFIG *Engine, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { ASSERT (Engine->EngineData.EngineType == PciePortEngine); PciePortProgramRegisterTable (PortInitTable, (sizeof (PortInitTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)), Engine, FALSE, Pcie); PcieSetLinkSpeedCap (PcieGen1, Engine, Pcie); PcieSetLinkWidthCap (Engine, Pcie); PcieCompletionTimeout (Engine, Pcie); PcieLinkSetSlotCap (Engine, Pcie); PcieLinkInitHotplug (Engine, Pcie); PcieFmPhyChannelCharacteristic (Engine, Pcie); if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { PcieLinkSafeMode (Engine, Pcie); } if (Engine->Type.Port.PortData.PortPresent == PortDisabled) { ASSERT (Engine->Type.Port.IsSB == FALSE); PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie); } // Train port that forced to compliance in last stage of training if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { PcieTrainingSetPortState (Engine, LinkStateTrainingCompleted, FALSE, Pcie); } }
VOID STATIC PcieEarlyPortInitCallbackTN ( IN PCIe_ENGINE_CONFIG *Engine, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackTN Enter\n"); ASSERT (Engine->EngineData.EngineType == PciePortEngine); PciePortProgramRegisterTable (PortInitEarlyTableTN.Table, PortInitEarlyTableTN.Length, Engine, FALSE, Pcie); PcieSetLinkSpeedCapV4 (PcieGen1, Engine, Pcie); PcieSetLinkWidthCap (Engine, Pcie); PcieCompletionTimeout (Engine, Pcie); PcieLinkSetSlotCap (Engine, Pcie); PcieLinkInitHotplug (Engine, Pcie); if (Engine->Type.Port.PortData.PortPresent == PortDisabled || (Engine->Type.Port.PortData.EndpointStatus == EndpointNotPresent && Engine->Type.Port.PortData.LinkHotplug != HotplugEnhanced && Engine->Type.Port.PortData.LinkHotplug != HotplugServer)) { ASSERT (!PcieConfigIsSbPcieEngine (Engine)); // // Pass endpoint status in scratch // PciePortRegisterRMW ( Engine, DxF0xE4_x01_ADDRESS, 0x1, 0x1, FALSE, Pcie ); PcieTrainingSetPortStateV1 (Engine, LinkStateDeviceNotPresent, FALSE, Pcie); } if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { PcieTrainingSetPortStateV1 (Engine, LinkStateTrainingCompleted, FALSE, Pcie); } IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackTN Exit\n"); }
VOID STATIC PcieEarlyPortInitCallbackCZ ( IN PCIe_ENGINE_CONFIG *Engine, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackCZ Enter\n"); ASSERT (Engine->EngineData.EngineType == PciePortEngine); PciePortProgramRegisterTable (PortInitEarlyTableCZ.Table, PortInitEarlyTableCZ.Length, Engine, FALSE, Pcie); IDS_OPTION_HOOK (IDS_GNB_EQUAL_PRESET, Engine, (AMD_CONFIG_PARAMS *)Pcie->StdHeader); PcieSetLinkSpeedCapV4 (PcieGen1, Engine, Pcie); PcieSetLinkWidthCap (Engine, Pcie); PcieCompletionTimeout (Engine, Pcie); PcieLinkSetSlotCap (Engine, Pcie); PcieLinkInitHotplugCZ (Engine, Pcie); //Move EXTENDED_FMT_SUPPORTED stting from Mid to here. PciePortRegisterRMW ( Engine, DxFxxE4_xC1_ADDRESS, DxFxxE4_xC1_StrapE2EPrefixEn_MASK | DxFxxE4_xC1_StrapExtendedFmtSupported_MASK, (1 << DxFxxE4_xC1_StrapE2EPrefixEn_OFFSET) | (1 << DxFxxE4_xC1_StrapExtendedFmtSupported_OFFSET), FALSE, Pcie ); if (Engine->Type.Port.PortData.PortPresent == PortDisabled || (Engine->Type.Port.PortData.EndpointStatus == EndpointNotPresent && Engine->Type.Port.PortData.LinkHotplug != HotplugEnhanced && Engine->Type.Port.PortData.LinkHotplug != HotplugServer)) { ASSERT (!PcieConfigIsSbPcieEngine (Engine)); // // Pass endpoint status in scratch // PciePortRegisterRMW ( Engine, DxFxxE4_x01_ADDRESS, 0x1, 0x1, FALSE, Pcie ); PcieTrainingSetPortStateV2 (Engine, LinkStateDeviceNotPresent, FALSE, Pcie); } if (PcieConfigIsSbPcieEngine (Engine)) { PcieTrainingSetPortStateV2 (Engine, LinkStateTrainingSuccess, FALSE, Pcie); PcieRegisterWriteField ( PcieConfigGetParentWrapper (Engine), CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_001C_ADDRESS), D0F0xE4_CORE_001C_TX_ATOMIC_OPS_DISABLE_OFFSET, D0F0xE4_CORE_001C_TX_ATOMIC_OPS_DISABLE_WIDTH, 0x1, TRUE, Pcie ); } if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { PcieTrainingSetPortStateV2 (Engine, LinkStateTrainingCompleted, FALSE, Pcie); } IDS_OPTION_HOOK (IDS_GNB_GEN1_LOOPBACK, Engine, (AMD_CONFIG_PARAMS *)Pcie->StdHeader); IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackCZ Exit\n"); }