static void setup_iomux_enet(void) { SETUP_IOMUX_PADS(enet_pads1); udelay(20); gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */ gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */ gpio_direction_output(IMX_GPIO_NR(6, 24), 1); gpio_direction_output(IMX_GPIO_NR(6, 25), 1); gpio_direction_output(IMX_GPIO_NR(6, 27), 1); gpio_direction_output(IMX_GPIO_NR(6, 28), 1); gpio_direction_output(IMX_GPIO_NR(6, 29), 1); udelay(1000); gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */ /* Need 100ms delay to exit from reset. */ udelay(1000 * 100); gpio_free(IMX_GPIO_NR(6, 24)); gpio_free(IMX_GPIO_NR(6, 25)); gpio_free(IMX_GPIO_NR(6, 27)); gpio_free(IMX_GPIO_NR(6, 28)); gpio_free(IMX_GPIO_NR(6, 29)); SETUP_IOMUX_PADS(enet_pads2); }
int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */ if (is_mx6dq() || is_mx6dqp()) setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); else setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); /* I2C 3 Steer */ gpio_direction_output(IMX_GPIO_NR(5, 4), 1); SETUP_IOMUX_PADS(i2c3_pads); #ifndef CONFIG_SYS_FLASH_CFI if (is_mx6dq() || is_mx6dqp()) setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2); else setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2); #endif gpio_direction_output(IMX_GPIO_NR(1, 15), 1); SETUP_IOMUX_PADS(port_exp); #ifdef CONFIG_VIDEO_IPUV3 setup_display(); #endif #ifdef CONFIG_MTD_NOR_FLASH setup_iomux_eimnor(); #endif return 0; }
int board_mmc_init(bd_t *bis) { int ret; int i; for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: SETUP_IOMUX_PADS(usdhc3_pads); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); break; case 1: SETUP_IOMUX_PADS(usdhc2_pads); gpio_direction_input(USDHC2_CD_GPIO); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); break; default: printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", i + 1, CONFIG_SYS_FSL_USDHC_NUM); return -EINVAL; } ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); if (ret) return ret; } return 0; }
void board_enable_lcd(const struct display_info_t *di, int enable) { if (enable) SETUP_IOMUX_PADS(rgb_pads); else SETUP_IOMUX_PADS(rgb_gpio_pads); gpio_direction_output(GP_BACKLIGHT_RGB, enable); }
int board_early_init_f(void) { set_gpios_in(gpios_in, ARRAY_SIZE(gpios_in)); set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1); set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0); SETUP_IOMUX_PADS(init_pads); SETUP_IOMUX_PADS(rgb_gpio_pads); return 0; }
int board_eth_init(bd_t *bis) { struct phy_device *phydev; struct mii_dev *bus; unsigned short id1, id2; int ret; /* check whether KSZ9031 or AR8035 has to be configured */ SETUP_IOMUX_PADS(enet_pads_ar8035); /* phy reset */ gpio_direction_output(IMX_GPIO_NR(3, 23), 0); udelay(2000); gpio_set_value(IMX_GPIO_NR(3, 23), 1); udelay(500); bus = fec_get_miibus(IMX_FEC_BASE, -1); if (!bus) return -EINVAL; phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); if (!phydev) { printf("Error: phy device not found.\n"); ret = -ENODEV; goto free_bus; } /* get the PHY id */ id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) { /* re-configure for Micrel KSZ9031 */ printf("configure Micrel KSZ9031 Ethernet Phy at address %d\n", phydev->addr); /* phy reset: gpio3-23 */ gpio_set_value(IMX_GPIO_NR(3, 23), 0); gpio_set_value(IMX_GPIO_NR(6, 30), (phydev->addr >> 2)); gpio_set_value(IMX_GPIO_NR(6, 25), 1); gpio_set_value(IMX_GPIO_NR(6, 27), 1); gpio_set_value(IMX_GPIO_NR(6, 28), 1); gpio_set_value(IMX_GPIO_NR(6, 29), 1); SETUP_IOMUX_PADS(enet_pads_ksz9031); gpio_set_value(IMX_GPIO_NR(6, 24), 1); udelay(500); gpio_set_value(IMX_GPIO_NR(3, 23), 1); SETUP_IOMUX_PADS(enet_pads_final_ksz9031); } else if ((id1 == 0x004d) && (id2 == 0xd072)) {
static void enable_fwadapt_7wvga(struct display_info_t const *dev) { SETUP_IOMUX_PADS(fwadapt_7wvga_pads); gpio_direction_output(IMX_GPIO_NR(2, 10), 1); gpio_direction_output(IMX_GPIO_NR(2, 11), 1); }
static bool is_hummingboard2(void) { int val1; SETUP_IOMUX_PADS(hb_cbi_sense); gpio_direction_input(IMX_GPIO_NR(2, 8)); val1 = gpio_get_value(IMX_GPIO_NR(2, 8)); /* * Machine selection - * Machine val1 * ------------------- * HB2 0 * HB rev 3.x x * CBi x * HB x */ if (val1 == 0) return true; else return false; }
int board_mmc_init(bd_t *bis) { SETUP_IOMUX_PADS(usdhc3_pads); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); }
static bool is_hummingboard(void) { int val1, val2; SETUP_IOMUX_PADS(hb_cbi_sense); gpio_direction_input(IMX_GPIO_NR(4, 9)); gpio_direction_input(IMX_GPIO_NR(3, 4)); val1 = gpio_get_value(IMX_GPIO_NR(4, 9)); val2 = gpio_get_value(IMX_GPIO_NR(3, 4)); /* * Machine selection - * Machine val1, val2 * ------------------------- * HB rev 3.x x 0 * CBi 0 1 * HB 1 1 */ if (val2 == 0) return true; else if (val1 == 0) return false; else return true; }
static void setup_iomux_enet(void) { gpio_direction_output(GP_PHY_RESET, 0); gpio_direction_output(GP_PHY_AD2, 1); gpio_direction_output(GP_PHY_MODE0, 1); gpio_direction_output(GP_PHY_MODE1, 1); gpio_direction_output(GP_PHY_MODE2, 1); gpio_direction_output(GP_PHY_MODE3, 1); gpio_direction_output(GP_PHY_CLK125, 1); SETUP_IOMUX_PADS(enet_pads1); /* Need delay 10ms according to KSZ9021 spec */ udelay(1000 * 10); gpio_set_value(GP_PHY_RESET, 1); SETUP_IOMUX_PADS(enet_pads2); }
int board_mmc_init(bd_t *bis) { int i, ret; /* * According to the board_mmc_init() the following map is done: * (U-boot device node) (Physical Port) * mmc0 USDHC1 */ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: SETUP_IOMUX_PADS(usdhc1_pads); gpio_direction_input(USDHC1_CD_GPIO); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); break; default: printf("Warning - USDHC%d controller not supporting\n", i + 1); return 0; } ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); if (ret) { printf("Warning: failed to initialize mmc dev %d\n", i); return ret; } } return 0; }
static void setup_gpmi_nand(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; /* config gpmi nand iomux */ SETUP_IOMUX_PADS(nfc_pads); /* gate ENFC_CLK_ROOT clock first,before clk source switch */ clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); /* config gpmi and bch clock to 100 MHz */ clrsetbits_le32(&mxc_ccm->cs2cdr, MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); /* enable ENFC_CLK_ROOT clock */ setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); /* enable gpmi and bch clock gating */ setbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); /* enable apbh clock gating */ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); }
int board_ehci_hcd_init(int port) { int gpio; SETUP_IOMUX_PADS(usb_pads); /* Reset USB HUB */ switch (board_type) { case GW53xx: case GW552x: case GW5906: gpio = (IMX_GPIO_NR(1, 9)); break; case GW54proto: case GW54xx: gpio = (IMX_GPIO_NR(1, 16)); break; default: return 0; } /* request and toggle hub rst */ gpio_request(gpio, "usb_hub_rst#"); gpio_direction_output(gpio, 0); mdelay(2); gpio_set_value(gpio, 1); return 0; }
static void setup_iomux_wdog(void) { SETUP_IOMUX_PADS(wdog_pads); gpio_direction_output(WDT_TRG, 0); gpio_direction_output(WDT_EN, 1); gpio_direction_input(WDT_TRG); }
static void setup_iomux_enet(void) { SETUP_IOMUX_PADS(enet_pads); gpio_direction_output(ETH_PHY_RESET, 0); mdelay(2); gpio_set_value(ETH_PHY_RESET, 1); }
static void setup_iomux_eimnor(void) { SETUP_IOMUX_PADS(eimnor_pads); gpio_direction_output(IMX_GPIO_NR(5, 4), 0); eimnor_cs_setup(); }
int board_mmc_init(bd_t *bis) { SETUP_IOMUX_PADS(usdhc2_pads); usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); }
int board_mmc_init(bd_t *bis) { /* Only one USDHC controller on Ventana */ SETUP_IOMUX_PADS(usdhc3_pads); usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); usdhc_cfg.max_bus_width = 4; return fsl_esdhc_initialize(bis, &usdhc_cfg); }
static void setup_spi(void) { gpio_request(IMX_GPIO_NR(4, 24), "spi_cs0"); gpio_direction_output(IMX_GPIO_NR(4, 24), 1); SETUP_IOMUX_PADS(ecspi3_pads); enable_spi_clk(true, 2); }
static void setup_iomux_enet(void) { gpio_direction_output(GP_ENET_PHY_RESET, 0); /* PHY rst */ gpio_direction_output(GP_PHY_AD2, 1); gpio_direction_output(GP_PHY_MODE0, 1); gpio_direction_output(GP_PHY_MODE1, 1); gpio_direction_output(GP_PHY_MODE2, 1); gpio_direction_output(GP_PHY_MODE3, 1); gpio_direction_output(GP_PHY_CLK125, 1); SETUP_IOMUX_PADS(enet_pads1); /* Need delay 10ms according to KSZ9021 spec */ udelay(1000 * 10); gpio_set_value(GP_ENET_PHY_RESET, 1); /* PHY reset */ SETUP_IOMUX_PADS(enet_pads2); udelay(100); /* Wait 100 us before using mii interface */ }
static void setup_iomux_enet(void) { SETUP_IOMUX_PADS(enet_pads); gpio_direction_output(ENET_PHY_RESET_GPIO, 0); mdelay(10); gpio_set_value(ENET_PHY_RESET_GPIO, 1); mdelay(30); }
static bool is_revc1(void) { SETUP_IOMUX_PADS(rev_detection_pad); gpio_direction_input(REV_DETECTION); if (gpio_get_value(REV_DETECTION)) return true; else return false; }
static void setup_iomux_enet(void) { SETUP_IOMUX_PADS(enet_pads); /* Reset AR8031 PHY */ gpio_direction_output(ETH_PHY_RESET, 0); mdelay(10); gpio_set_value(ETH_PHY_RESET, 1); udelay(100); }
static void cm_fx6_setup_issd(void) { SETUP_IOMUX_PADS(sata_pads); /* Make sure this gpio has logical 0 value */ gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); udelay(100); cm_fx6_sata_power(0); mdelay(250); cm_fx6_sata_power(1); }
static void cm_fx6_setup_gpmi_nand(void) { SETUP_IOMUX_PADS(nand_pads); /* Enable clock roots */ enable_usdhc_clk(1, 3); enable_usdhc_clk(1, 4); setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) | MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) | MXC_CCM_CS2CDR_ENFC_CLK_SEL(0)); }
static void setup_display(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; int reg; /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ SETUP_IOMUX_PADS(di0_pads); enable_ipu_clock(); imx_setup_hdmi(); /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ reg = readl(&mxc_ccm->CCGR3); reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; writel(reg, &mxc_ccm->CCGR3); /* set LDB0, LDB1 clk select to 011/011 */ reg = readl(&mxc_ccm->cs2cdr); reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); writel(reg, &mxc_ccm->cs2cdr); reg = readl(&mxc_ccm->cscmr2); reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; writel(reg, &mxc_ccm->cscmr2); reg = readl(&mxc_ccm->chsccdr); reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); writel(reg, &mxc_ccm->chsccdr); reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; writel(reg, &iomux->gpr[2]); reg = readl(&iomux->gpr[3]); reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); writel(reg, &iomux->gpr[3]); }
static void setup_iomux_enet(int gpio) { SETUP_IOMUX_PADS(enet_pads); /* toggle PHY_RST# */ gpio_request(gpio, "phy_rst#"); gpio_direction_output(gpio, 0); mdelay(10); gpio_set_value(gpio, 1); mdelay(100); }
int board_mmc_init(bd_t *bis) { if (spl_boot_device() == BOOT_DEVICE_SPI) printf("MMC SEtup, Boot SPI"); SETUP_IOMUX_PADS(usdhc3_pads); usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); usdhc_cfg[0].max_bus_width = 4; gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); }
int board_mmc_init(bd_t *bis) { int ret; u32 index = 0; /* * Following map is done: * (U-Boot device node) (Physical Port) * mmc0 SOM MicroSD * mmc1 Carrier board MicroSD */ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { switch (index) { case 0: SETUP_IOMUX_PADS(usdhc3_pads); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); usdhc_cfg[0].max_bus_width = 4; gpio_direction_input(USDHC3_CD_GPIO); break; case 1: SETUP_IOMUX_PADS(usdhc1_pads); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); usdhc_cfg[1].max_bus_width = 4; gpio_direction_input(USDHC1_CD_GPIO); break; default: printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", index + 1, CONFIG_SYS_FSL_USDHC_NUM); return -EINVAL; } ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); if (ret) return ret; } return 0; }