_mqx_int _bsp_usb_io_init ( void ) { #if PE_LDD_VERSION /* USB clock is configured using CPU component */ /* Check if peripheral is not used by Processor Expert USB_LDD component */ if (PE_PeripheralUsed((uint32_t)USB0_BASE_PTR) == TRUE) { /* IO Device used by PE Component*/ return IO_ERROR; } /** * Workaround for Processor Expert as USB clock divider settings has been removed * from __pe_initialize_hardware() and Cpu_SetClockConfiguration() functions * Needs to be replaced by dynamic calculation of dividers. * SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */ SIM_CLKDIV2 = (uint32_t)((SIM_CLKDIV2 & (uint32_t)~0x0DUL) | (uint32_t)0x02UL); /* Update USB clock prescalers */ #endif #if BSPCFG_USB_USE_IRC48M /* * Configure SIM_CLKDIV2: USBDIV = 0, USBFRAC = 0 */ SIM_CLKDIV2 = (uint32_t)0x0UL; /* Update USB clock prescalers */ /* Configure USB to be clocked from IRC 48MHz */ SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL(3); /* Enable USB-OTG IP clocking */ SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBOTG_MASK; /* Enable IRC 48MHz for USB module */ USB0_CLK_RECOVER_IRC_EN = 0x03; #else /* Configure USB to be clocked from PLL */ SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL(1); /* Enable USB-OTG IP clocking */ SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBOTG_MASK; /* USB D+ and USB D- are standalone not multiplexed one-purpose pins */ /* VREFIN for device is standalone not multiplexed one-purpose pin */ #endif #if BSP_USB_TWR_SER2 /* TWR-SER2 board has 2 connectors: on channel A, there is Micro-USB connector, ** which is not routed to TWRK64 board. On channel B, there is standard ** A-type host connector routed to the USB0 peripheral on TWRK64. To enable ** power to this connector, GPIO PB8 must be set as GPIO output */ PORT_PCR_REG(PORTB_BASE_PTR, 8) = PORT_PCR_MUX(0x01); GPIO_PDDR_REG(PTB_BASE_PTR) |= 1 << 8; // PB8 as output GPIO_PDOR_REG(PTB_BASE_PTR) |= 1 << 8; // PB8 in high level #endif return MQX_OK; }
/* ** =================================================================== ** Method : Cpu_SetMCGClockInModePEE (component MK22FN512VDC12) ** ** Description : ** Calling of this method will cause the clock frequency ** change in mode PEE, typically from 120M to 80M, vice versa. ** Parameters : ** NAME - DESCRIPTION ** ModeID - Clock configuration identifier ** Returns : ** --- - ERR_OK - OK. ** ERR_RANGE - Mode parameter out of range ** =================================================================== */ static LDD_TError Cpu_SetMCGClockInModePEE(LDD_TClockConfiguration ModeID) { if (ModeID > 0x03U) return ERR_RANGE; switch (ModeID) { case CPU_CLOCK_CONFIG_3: /* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC_CR = OSC_CR_ERCLKEN_MASK; /* SIM_SOPT2: MCGCLKSEL=0 */ SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x01); /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ MCG_C1 = (MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK); /* MCG_C2: ??=0,??=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ MCG_C2 = (MCG_C2_RANGE(0x02) | MCG_C2_EREFS_MASK); /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV=5 (devider is 6) */ MCG_C5 = MCG_C5_PRDIV0(0x05); /* MCG_C6: LOLIE=0,PLLS=1,CME=0,VDIV=6 */ MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x06)); while((MCG_S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */ } break; case CPU_CLOCK_CONFIG_0: /* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC_CR = (uint8_t)0x80U; /* SIM_SOPT2: MCGCLKSEL=0 */ SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x01); /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ MCG_C1 = (MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK); /* MCG_C2: ??=0,??=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ MCG_C2 = (MCG_C2_RANGE(0x02) | MCG_C2_EREFS_MASK); /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV=0xb (devider is 12) */ MCG_C5 = MCG_C5_PRDIV0(0x0b); /* MCG_C6: LOLIE=0,PLLS=1,CME=0,VDIV=16 (multiply is 40)*/ MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x10)); while((MCG_S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */ } break; default: break; } return ERR_OK; }
static int32_t bsp_usb_otg_io_init ( int32_t i ) { if (i == 0) { #if (OS_ADAPTER_ACTIVE_OS == OS_ADAPTER_MQX) #if BSPCFG_USB_USE_IRC48M /* * Configure SIM_CLKDIV2: USBDIV = 0, USBFRAC = 0 */ //HW_SIM_CLKDIV2_CLR(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK); SIM_CLKDIV2 &= ~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK); /* Configure USB to be clocked from IRC 48MHz */ //HW_SIM_SOPT2_SET(SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_IRC48MSEL_MASK); SIM_SOPT2 |= (SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_IRC48MSEL_MASK); /* Enable USB-OTG IP clocking */ //HW_SIM_SCGC4_SET(SIM_SCGC4_USBOTG_MASK); SIM_SCGC4 |= (SIM_SCGC4_USBOTG_MASK); /* Enable IRC 48MHz for USB module */ USB_CLK_RECOVER_IRC_EN = 0x03; #else /* Configure USBFRAC = 0, USBDIV = 0 => frq(USBout) = 1 / 1 * frq(PLLin) */ //HW_SIM_CLKDIV2_CLR(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK); SIM_CLKDIV2 &= ~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK); /* Configure USB to be clocked from PLL */ //HW_SIM_SOPT2_SET(SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK); SIM_SOPT2 |= (SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL(0x01)); /* Enable USB-OTG IP clocking */ //HW_SIM_SCGC4_SET(SIM_SCGC4_USBOTG_MASK); SIM_SCGC4 |= (SIM_SCGC4_USBOTG_MASK); #endif #else #if BSPCFG_USB_USE_IRC48M /* * Configure SIM_CLKDIV2: USBDIV = 0, USBFRAC = 0 */ HW_SIM_CLKDIV2_CLR(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK); /* Configure USB to be clocked from IRC 48MHz */ HW_SIM_SOPT2_SET(SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_IRC48MSEL_MASK); /* Enable USB-OTG IP clocking */ HW_SIM_SCGC4_SET(SIM_SCGC4_USBOTG_MASK); /* Enable IRC 48MHz for USB module */ USB_CLK_RECOVER_IRC_EN = 0x03; #else /* Configure USBFRAC = 0, USBDIV = 0 => frq(USBout) = 1 / 1 * frq(PLLin) */ HW_SIM_CLKDIV2_CLR(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK); /* Configure USB to be clocked from PLL */ HW_SIM_SOPT2_SET(SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL(0x01)); /* Enable USB-OTG IP clocking */ HW_SIM_SCGC4_SET(SIM_SCGC4_USBOTG_MASK); #endif /* Weak pull downs */ HW_USB_USBCTRL_WR(0x40); #if KHCICFG_HOST_PORT_NATIVE /* Souce the P5V0_K22_USB. Set PTC9 to high */ BW_PORT_PCRn_MUX(HW_PORTC, 9, 1); /* GPIO mux */ HW_GPIO_PDDR_SET(2, 1<<9); /* Set output */ HW_GPIO_PSOR_SET(2, 1<<9); /* Output high */ #endif #endif } else { return -1; /* unknow controller */ } return 0; }
void __pe_initialize_hardware(void) { /*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/ /*** ### MK22FN512VDC12 "Cpu" init code ... ***/ /*** PE initialization code after reset ***/ /* Disable the WDOG module */ /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */ WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */ /* WDOG_UNLOCK: WDOGUNLOCK=0xD928 */ WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */ /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,??=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ WDOG_STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | WDOG_STCTRLH_WAITEN_MASK | WDOG_STCTRLH_STOPEN_MASK | WDOG_STCTRLH_ALLOWUPDATE_MASK | WDOG_STCTRLH_CLKSRC_MASK | 0x0100U; #if 0 /* SIM_SCGC6: RTC=1 */ SIM_SCGC6 |= SIM_SCGC6_RTC_MASK; if ((RTC_CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the OSCILLATOR is not already enabled */ /* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ RTC_CR &= (uint32_t)~(uint32_t)( RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK ); /* RTC_CR: OSCE=1 */ RTC_CR |= RTC_CR_OSCE_MASK; /* RTC_CR: CLKO=0 */ RTC_CR &= (uint32_t)~(uint32_t)(RTC_CR_CLKO_MASK); } #endif /* System clock initialization */ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x03) | SIM_CLKDIV1_OUTDIV4(0x03); /* Set the system prescalers to safe value */ /* SIM_SCGC5: PORTD=1,PORTC=1,PORTA=1 */ SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */ if ((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) { /* PMC_REGSC: ACKISO=1 */ PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */ } /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=2,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x02) | SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */ /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */ SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0x4) | SIM_CLKDIV2_USBFRAC_MASK; /* Update USB clock prescalers */ /* SIM_SOPT2: PLLFLLSEL=1 */ SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x01); /* Select PLL as a clock source for various peripherals */ /* SIM_SOPT1: OSC32KSEL=0 */ SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */ /* PORTA_PCR18: ISF=0,MUX=0 */ PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); /* PORTA_PCR19: ISF=0,MUX=0 */ PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); /* Switch to FBE Mode */ /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ MCG_C2 = (MCG_C2_RANGE(0x02) | MCG_C2_EREFS_MASK); /* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=1,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC_CR = (OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK); /* MCG_C7: OSCSEL=0 */ MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK); /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=0,IREFSTEN=0 */ MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x03)); /* MCG_C4: DMX32=0,DRST_DRS=0 */ MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=b(devider is 12) */ MCG_C5 = MCG_C5_PRDIV0(0x0b); /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=16(multiply is 40) */ MCG_C6 = MCG_C6_VDIV0(0x10); while((MCG_S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */ } while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ } while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ } /* Switch to PBE Mode */ /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=16(multiply is 40) */ MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x10)); while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ } while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */ } /* Switch to PEE Mode */ /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=0,IREFSTEN=0 */ MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x03)); ClockConfigurationID = CPU_CLOCK_CONFIG_3; while((MCG_S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */ } /*** End of PE initialization code after reset ***/ /*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/ }
/* ** =================================================================== ** Method : Cpu_SetClockConfiguration (component MK22FN512VDC12) ** ** Description : ** Calling of this method will cause the clock configuration ** change and reconfiguration of all components according to ** the requested clock configuration setting. ** Parameters : ** NAME - DESCRIPTION ** ModeID - Clock configuration identifier ** Returns : ** --- - ERR_OK - OK. ** ERR_RANGE - Mode parameter out of range ** =================================================================== */ LDD_TError Cpu_SetClockConfiguration(LDD_TClockConfiguration ModeID) { if (ModeID > 0x03U) { return ERR_RANGE; /* Undefined clock configuration requested requested */ } if (0x03U == ClockConfigurationID) { if ((CPU_CLOCK_CONFIG_1 == ModeID) || ( CPU_CLOCK_CONFIG_2 == ModeID)) return ERR_FAILED; Cpu_SetMCGClockInModePEE(ModeID); } if (0x03U == ModeID) { if ((CPU_CLOCK_CONFIG_1 == ClockConfigurationID) || ( CPU_CLOCK_CONFIG_2 == ClockConfigurationID)) return ERR_FAILED; Cpu_SetMCGClockInModePEE(ModeID); } switch (ModeID) { case CPU_CLOCK_CONFIG_0: if (ClockConfigurationID == 2U) { /* Clock configuration 0 and clock configuration 2 use different clock configuration */ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,*/ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x04) | SIM_CLKDIV1_OUTDIV4(0x04); /* Set the system prescalers to safe value */ Cpu_SetMCG(0U); /* Update clock source setting */ } /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=2,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x03) | SIM_CLKDIV1_OUTDIV4(0x02); /* Update system prescalers */ #if (BSPCFG_USB_CLK_FROM_IRC48M) SIM_CLKDIV2 = 0; SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x03); SIM_SCGC4 |= (SIM_SCGC4_USBOTG_MASK); /* Enable IRC 48MHz for USB module */ USB_CLK_RECOVER_IRC_EN = 0x03; #else /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */ SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0x4) | SIM_CLKDIV2_USBFRAC_MASK; /* Update USB clock prescalers */ /* SIM_SOPT2: PLLFLLSEL=0x01 */ SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x01); /* Select PLL as a clock source for various peripherals */ /* SIM_SOPT1: OSC32KSEL=0 */ #endif SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */ break; case CPU_CLOCK_CONFIG_1: if (ClockConfigurationID == 2U) { /* Clock configuration 1 and clock configuration 2 use different clock configuration */ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x04) | SIM_CLKDIV1_OUTDIV4(0x04); /* Set the system prescalers to safe value */ Cpu_SetMCG(0U); /* Update clock source setting */ } /* SIM_CLKDIV1: OUTDIV1=9,OUTDIV2=9,OUTDIV3=9,OUTDIV4=9,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x09) | SIM_CLKDIV1_OUTDIV2(0x09) | SIM_CLKDIV1_OUTDIV3(0x09) | SIM_CLKDIV1_OUTDIV4(0x09); /* Update system prescalers */ /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */ SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0x4) | SIM_CLKDIV2_USBFRAC_MASK; /* SIM_SOPT2: PLLFLLSEL=0x01 */ SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x01); /* SIM_SOPT1: OSC32KSEL=0 */ SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */ break; case CPU_CLOCK_CONFIG_2: /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??*/ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x04) | SIM_CLKDIV1_OUTDIV4(0x04); /* Set the system prescalers to safe value */ if ((MCG_C2 & MCG_C2_IRCS_MASK) == 0x00U) { /* MCG_SC: FCRDIV=1 */ MCG_SC = (uint8_t)((MCG_SC & (uint8_t)~(uint8_t)( MCG_SC_FCRDIV(0x06) )) | (uint8_t)( MCG_SC_FCRDIV(0x01) )); } else { /* MCG_C2: IRCS=0 */ MCG_C2 &= (uint8_t)~(uint8_t)(MCG_C2_IRCS_MASK); while((MCG_S & MCG_S_IRCST_MASK) != 0x00U) { /* Check that the source internal reference clock is slow clock. */ } /* MCG_SC: FCRDIV=1 */ MCG_SC = (uint8_t)((MCG_SC & (uint8_t)~(uint8_t)( MCG_SC_FCRDIV(0x06) )) | (uint8_t)( MCG_SC_FCRDIV(0x01) )); /* MCG_C2: IRCS=1 */ MCG_C2 |= MCG_C2_IRCS_MASK; while((MCG_S & MCG_S_IRCST_MASK) == 0x00U) { /* Check that the source internal reference clock is fast clock. */ } } Cpu_SetMCG(1U); /* Update clock source setting */ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x00) | SIM_CLKDIV1_OUTDIV3(0x00) | SIM_CLKDIV1_OUTDIV4(0x03); /* Update system prescalers */ /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */ SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0x4) | SIM_CLKDIV2_USBFRAC_MASK; /* SIM_SOPT2: PLLFLLSEL=1 */ SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x01); /* Select PLL as a clock source for various peripherals */ /* SIM_SOPT1: OSC32KSEL=0 */ SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */ break; case CPU_CLOCK_CONFIG_3: /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x04) | SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */ #if (BSPCFG_USB_CLK_FROM_IRC48M) SIM_CLKDIV2 = 0; SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x03); SIM_SCGC4 |= (SIM_SCGC4_USBOTG_MASK); /* Enable IRC 48MHz for USB module */ USB_CLK_RECOVER_IRC_EN = 0x03; #else /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */ SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0x4) | SIM_CLKDIV2_USBFRAC_MASK; /* SIM_SOPT2: PLLFLLSEL=1 */ SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x01); /* Select PLL as a clock source for various peripherals */ #endif /* SIM_SOPT1: OSC32KSEL=0 */ SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */ break; default: break; } LDD_SetClockConfiguration(ModeID); /* Call all LDD components to update the clock configuration */ ClockConfigurationID = ModeID; /* Store clock configuration identifier */ return ERR_OK; }
/*lint -esym(765,Cpu_Interrupt) Disable MISRA rule (8.10) checking for symbols (Cpu_Interrupt). */ void __init_hardware(void) { /*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/ /*** ### MK70FN1M0VMJ12 "Cpu" init code ... ***/ /*** PE initialization code after reset ***/ SCB_VTOR = (uint32_t)(&__vect_table); /* Set the interrupt vector table position */ /* Disable the WDOG module */ /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */ WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */ /* WDOG_UNLOCK: WDOGUNLOCK=0xD928 */ WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */ /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,??=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ WDOG_STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | WDOG_STCTRLH_WAITEN_MASK | WDOG_STCTRLH_STOPEN_MASK | WDOG_STCTRLH_ALLOWUPDATE_MASK | WDOG_STCTRLH_CLKSRC_MASK | 0x0100U; /* System clock initialization */ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x03) | SIM_CLKDIV1_OUTDIV4(0x03); /* Set the system prescalers to safe value */ /* SIM_SCGC5: PORTE=1,PORTA=1 */ SIM_SCGC5 |= (SIM_SCGC5_PORTE_MASK | SIM_SCGC5_PORTA_MASK); /* Enable clock gate for ports to enable pin routing */ if ((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) { /* PMC_REGSC: ACKISO=1 */ PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */ } /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x00) | SIM_CLKDIV1_OUTDIV3(0x01) | SIM_CLKDIV1_OUTDIV4(0x01); /* Update system prescalers */ /* SIM_SOPT2: PLLFLLSEL=0 */ SIM_SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL(0x03)); /* Select FLL as a clock source for various peripherals */ /* SIM_SOPT1: OSC32KSEL=0 */ SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL_MASK); /* System oscillator drives 32 kHz clock for various peripherals */ /* SIM_SCGC1: OSC1=1 */ SIM_SCGC1 |= SIM_SCGC1_OSC1_MASK; /* Switch to FEI Mode */ /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ MCG_C1 = MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK; /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */ MCG_C2 = MCG_C2_RANGE0(0x00); /* MCG_C4: DMX32=0,DRST_DRS=0 */ MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC0_CR = OSC_CR_ERCLKEN_MASK; /* MCG_C10: LOCRE2=0,??=0,RANGE1=0,HGO1=0,EREFS1=0,??=0,??=0 */ MCG_C10 = MCG_C10_RANGE1(0x00); /* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC1_CR = OSC_CR_ERCLKEN_MASK; /* MCG_C7: OSCSEL=0 */ MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK); /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=0 */ MCG_C5 = MCG_C5_PRDIV0(0x00); /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ MCG_C6 = MCG_C6_VDIV0(0x00); /* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */ MCG_C11 = MCG_C11_PRDIV1(0x00); /* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */ MCG_C12 = MCG_C12_VDIV1(0x00); /* 3 */ while((MCG_S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */ } while((MCG_S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */ } /*** End of PE initialization code after reset ***/ /*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/ }