static int max63xx_wdt_stop(struct watchdog_device *wdd) { u8 val; spin_lock(&io_lock); val = __raw_readb(wdt_base); val &= ~MAX6369_WDSET; val |= 3; __raw_writeb(val, wdt_base); spin_unlock(&io_lock); return 0; }
static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) { int line = irq_to_gpio(d->irq); int port = line >> 3; int port_mask = 1 << (line & 7); if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) gpio_int_type2[port] ^= port_mask; gpio_int_unmasked[port] &= ~port_mask; ep93xx_gpio_update_int_params(port); __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); }
static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable) { int line = irq_to_gpio(irq); int port = line >> 3; int port_mask = 1 << (line & 7); if (enable) gpio_int_debounce[port] |= port_mask; else gpio_int_debounce[port] &= ~port_mask; __raw_writeb(gpio_int_debounce[port], EP93XX_GPIO_REG(int_debounce_register_offset[port])); }
static void simtec_audio_startup_lrroute(void) { unsigned int tmp; unsigned long flags; local_irq_save(flags); tmp = __raw_readb(BAST_VA_CTRL1); tmp &= ~BAST_CPLD_CTRL1_LRMASK; tmp |= BAST_CPLD_CTRL1_LRCDAC; __raw_writeb(tmp, BAST_VA_CTRL1); local_irq_restore(flags); }
static irqreturn_t ebsa110_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) { u32 count; write_seqlock(&xtime_lock); /* latch and read timer 1 */ __raw_writeb(0x40, PIT_CTRL); count = __raw_readb(PIT_T1); count |= __raw_readb(PIT_T1) << 8; count += COUNT; __raw_writeb(count & 0xff, PIT_T1); __raw_writeb(count >> 8, PIT_T1); timer_tick(regs); write_sequnlock(&xtime_lock); return IRQ_HANDLED; }
/* * Set the executing CPUs power mode as defined. This will be in * preparation for it executing a WFI instruction. * * This function must be called with preemption disabled, and as it * has the side effect of disabling coherency, caches must have been * flushed. Interrupts must also have been disabled. */ int scu_power_mode(void __iomem *scu_base, unsigned int mode) { unsigned int val; int cpu = smp_processor_id(); if (mode > 3 || mode == 1 || cpu > 3) return -EINVAL; val = __raw_readb(scu_base + SCU_CPU_STATUS + cpu) & ~0x03; val |= mode; __raw_writeb(val, scu_base + SCU_CPU_STATUS + cpu); return 0; }
/* * hardware specific access to control-lines * * ctrl: * NAND_NCE: bit 0 -> bit 2 * NAND_CLE: bit 1 -> bit 1 * NAND_ALE: bit 2 -> bit 0 */ static void ts7250_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *chip = mtd->priv; if (ctrl & NAND_CTRL_CHANGE) { unsigned long addr = TS72XX_NAND_CONTROL_VIRT_BASE; unsigned char bits; bits = (ctrl & NAND_NCE) << 2; bits |= ctrl & NAND_CLE; bits |= (ctrl & NAND_ALE) >> 2; __raw_writeb((__raw_readb(addr) & ~0x7) | bits, addr); }
/********************************************************** * Routine: mux_pwr_save * Description: Set pins to optimal power savings state. * * NOTE ES1 Failures for Errata, Do NOT include: * - set D0-D31 (boot failure, u-boot ok) * - set D16-D31 (boot failue, u-boot ok) * - set D0-D15 (boot with memory errors, u-boot ok) * - set DQS3 (boot failures, u-boot start some failures). * - set DQS0-2 (no apparent problems). * *********************************************************/ static void mux_pwr_save(void) { #define SDRAM_WIDTH 32 #define OPTIMZE_FOR_DDR 1 #define NUM_DQS 4 u32 addr, val, offset, base = OMAP24XX_CTRL_BASE; /* Activate DDR/SDR-SDRAM signal pull-ups on DQ signals to save power */ for(offset = 0x65; offset < (0x65 + SDRAM_WIDTH); offset++){ addr = base + offset; /* addr of pin config */ val = __raw_readb(addr) | (BIT4|BIT3); /* mask for pull-up on */ __raw_writeb(val, addr); /* update config */ } #if OPTIMZE_FOR_DDR /* Activate DDR-SDRAM signal pull-ups on DQS signals to save power */ for(offset = 0x50; (offset < 0x50 + NUM_DQS); offset++){ addr = base + offset; /* addr of pin config */ val = __raw_readb(addr) | (BIT4|BIT3); /* mask for pull-up on */ __raw_writeb(val, addr); /* update config */ } #endif }
/* * Set the executing CPUs power mode as defined. This will be in * preparation for it executing a WFI instruction. * * This function must be called with preemption disabled, and as it * has the side effect of disabling coherency, caches must have been * flushed. Interrupts must also have been disabled. */ int scu_power_mode(void __iomem *scu_base, unsigned int mode) { unsigned int val; int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); if (mode > 3 || mode == 1 || cpu > 3) return -EINVAL; val = __raw_readb(scu_base + SCU_CPU_STATUS + cpu) & ~0x03; val |= mode; __raw_writeb(val, scu_base + SCU_CPU_STATUS + cpu); return 0; }
/* newval=(oldval & ~mask)|newdata */ void oldlatch_bupdate(unsigned char mask,unsigned char newdata) { if (machine_is_archimedes()) { unsigned long flags; local_irq_save(flags); latch_b_copy = (latch_b_copy & ~mask) | newdata; __raw_writeb(latch_b_copy, LATCHB_BASE); local_irq_restore(flags); printk("Latch: B = 0x%02x\n", latch_b_copy); } else BUG(); }
static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); unsigned long flags; u8 v; local_irq_save(flags); v = __raw_readb(ep93xx_chip->data_dir_reg); v &= ~(1 << offset); __raw_writeb(v, ep93xx_chip->data_dir_reg); local_irq_restore(flags); return 0; }
static void pca_gmi_writebyte(void *pd, int reg, int val) { struct tegra_nor_chip_parms *chip_parm = info->plat; struct cs_info *csinfo = &chip_parm->csinfo; unsigned int *ptr = csinfo->virt; struct gpio_state *state = &csinfo->gpio_cs; snor_tegra_writel(info, info->init_config, TEGRA_SNOR_CONFIG_REG); snor_tegra_writel(info, info->timing1_read, TEGRA_SNOR_TIMING1_REG); snor_tegra_writel(info, info->timing0_read, TEGRA_SNOR_TIMING0_REG); gpio_set_value(state[0].gpio_num, state[0].value); __raw_writeb(val, ptr + reg); }
asmlinkage void mmc_loader(unsigned char *buf, unsigned long len) { mmc_init_progress(); mmc_update_progress(MMC_PROGRESS_ENTER); __raw_writeb(0x04, PORT84CR); __raw_writeb(0x04, PORT85CR); __raw_writeb(0x04, PORT86CR); __raw_writeb(0x04, PORT87CR); __raw_writeb(0x04, PORT88CR); __raw_writeb(0x04, PORT89CR); __raw_writeb(0x04, PORT90CR); __raw_writeb(0x04, PORT91CR); __raw_writeb(0x04, PORT92CR); __raw_writeb(0x14, PORT99CR); __raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 12), SMSTPCR3); mmc_update_progress(MMC_PROGRESS_INIT); sh_mmcif_boot_init(MMCIF_BASE); mmc_update_progress(MMC_PROGRESS_LOAD); sh_mmcif_boot_do_read(MMCIF_BASE, 2, (len + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS, buf); __raw_writel(__raw_readl(SMSTPCR3) | (1 << 12), SMSTPCR3); mmc_update_progress(MMC_PROGRESS_DONE); }
static void enable_hdmi(struct display_info_t const *dev) { u8 reg; printf("%s: setup HDMI monitor\n", __func__); reg = __raw_readb( HDMI_ARB_BASE_ADDR +HDMI_PHY_CONF0); reg |= HDMI_PHY_CONF0_PDZ_MASK; __raw_writeb(reg, HDMI_ARB_BASE_ADDR +HDMI_PHY_CONF0); udelay(3000); reg |= HDMI_PHY_CONF0_ENTMDS_MASK; __raw_writeb(reg, HDMI_ARB_BASE_ADDR +HDMI_PHY_CONF0); udelay(3000); reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; __raw_writeb(reg, HDMI_ARB_BASE_ADDR +HDMI_PHY_CONF0); __raw_writeb(HDMI_MC_PHYRSTZ_ASSERT, HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ); }
int __init setup_hd64461(void) { int irq_base, i; printk(KERN_INFO "HD64461 configured at 0x%x on irq %d(mapped into %d to %d)\n", HD64461_IOBASE, CONFIG_HD64461_IRQ, HD64461_IRQBASE, HD64461_IRQBASE + 15); /* Should be at processor specific part.. */ #if defined(CONFIG_CPU_SUBTYPE_SH7709) __raw_writew(0x2240, INTC_ICR1); #endif __raw_writew(0xffff, HD64461_NIMR); irq_base = irq_alloc_descs(HD64461_IRQBASE, HD64461_IRQBASE, 16, -1); if (IS_ERR_VALUE(irq_base)) { pr_err("%s: failed hooking irqs for HD64461\n", __func__); return irq_base; } for (i = 0; i < 16; i++) irq_set_chip_and_handler(irq_base + i, &hd64461_irq_chip, handle_level_irq); irq_set_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux); irq_set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW); #ifdef CONFIG_HD64461_ENABLER printk(KERN_INFO "HD64461: enabling PCMCIA devices\n"); __raw_writeb(0x4c, HD64461_PCC1CSCIER); __raw_writeb(0x00, HD64461_PCC1CSCR); #endif return 0; }
/* * Put the dog back in the kennel. */ static int sbwdog_release(struct inode *inode, struct file *file) { if (expect_close == 42) { __raw_writeb(0, user_dog); module_put(THIS_MODULE); } else { pr_crit("%s: Unexpected close, not stopping watchdog!\n", ident.identity); sbwdog_pet(user_dog); } clear_bit(0, &sbwdog_gate); expect_close = 0; return 0; }
static void simtec_nor_vpp(struct platform_device *pdev, int vpp) { unsigned int val; val = __raw_readb(BAST_VA_CTRL3); printk(KERN_DEBUG "%s(%d)\n", __func__, vpp); if (vpp) val |= BAST_CPLD_CTRL3_ROMWEN; else val &= ~BAST_CPLD_CTRL3_ROMWEN; __raw_writeb(val, BAST_VA_CTRL3); }
/* * Allow only a single thread to walk the dog */ static int sbwdog_open(struct inode *inode, struct file *file) { nonseekable_open(inode, file); if (test_and_set_bit(0, &sbwdog_gate)) return -EBUSY; __module_get(THIS_MODULE); /* * Activate the timer */ sbwdog_set(user_dog, timeout); __raw_writeb(1, user_dog); return 0; }
static int write_packet(struct imx_ep_struct *imx_ep, struct imx_request *req) { u8 *buf; int length, count, temp; if (unlikely(__raw_readl(imx_ep->imx_usb->base + USB_EP_STAT(EP_NO(imx_ep))) & EPSTAT_ZLPS)) { D_TRX(imx_ep->imx_usb->dev, "<%s> zlp still queued in EP %s\n", __func__, imx_ep->ep.name); return -1; } buf = req->req.buf + req->req.actual; prefetch(buf); length = min(req->req.length - req->req.actual, (u32)imx_ep->fifosize); if (imx_fifo_bcount(imx_ep) + length > imx_ep->fifosize) { D_TRX(imx_ep->imx_usb->dev, "<%s> packet overfill %s fifo\n", __func__, imx_ep->ep.name); return -1; } req->req.actual += length; count = length; if (!count && req->req.zero) { /* */ temp = __raw_readl(imx_ep->imx_usb->base + USB_EP_STAT(EP_NO(imx_ep))); __raw_writel(temp | EPSTAT_ZLPS, imx_ep->imx_usb->base + USB_EP_STAT(EP_NO(imx_ep))); D_TRX(imx_ep->imx_usb->dev, "<%s> zero packet\n", __func__); return 0; } while (count--) { if (count == 0) { /* */ temp = __raw_readl(imx_ep->imx_usb->base + USB_EP_FCTRL(EP_NO(imx_ep))); __raw_writel(temp | FCTRL_WFR, imx_ep->imx_usb->base + USB_EP_FCTRL(EP_NO(imx_ep))); } __raw_writeb(*buf++, imx_ep->imx_usb->base + USB_EP_FDAT0(EP_NO(imx_ep))); } return length; }
static int v3_write_config_byte(struct pci_dev *dev, int where, u8 val) { unsigned long addr; unsigned long flags; spin_lock_irqsave(&v3_lock, flags); addr = v3_open_config_window(dev, where); __raw_writeb(val, addr); __raw_readb(addr); v3_close_config_window(); spin_unlock_irqrestore(&v3_lock, flags); return PCIBIOS_SUCCESSFUL; }
void memcpy_toio(volatile void __iomem *to, const void *from, long count) { /* */ /* */ if (count >= 8 && ((u64)to & 7) == ((u64)from & 7)) { count -= 8; do { __raw_writeq(*(const u64 *)from, to); count -= 8; to += 8; from += 8; } while (count >= 0); count += 8; } if (count >= 4 && ((u64)to & 3) == ((u64)from & 3)) { count -= 4; do { __raw_writel(*(const u32 *)from, to); count -= 4; to += 4; from += 4; } while (count >= 0); count += 4; } if (count >= 2 && ((u64)to & 1) == ((u64)from & 1)) { count -= 2; do { __raw_writew(*(const u16 *)from, to); count -= 2; to += 2; from += 2; } while (count >= 0); count += 2; } while (count > 0) { __raw_writeb(*(const u8 *) from, to); count--; to++; from++; } mb(); }
/* * Copy data from "real" memory space to IO memory space. * This needs to be optimized. */ void memcpy_toio(volatile void __iomem *to, const void *from, long count) { /* Optimize co-aligned transfers. Everything else gets handled a byte at a time. */ /* FIXME -- align FROM. */ if (count >= 8 && ((u64)to & 7) == ((u64)from & 7)) { count -= 8; do { __raw_writeq(*(const u64 *)from, to); count -= 8; to += 8; from += 8; } while (count >= 0); count += 8; } if (count >= 4 && ((u64)to & 3) == ((u64)from & 3)) { count -= 4; do { __raw_writel(*(const u32 *)from, to); count -= 4; to += 4; from += 4; } while (count >= 0); count += 4; } if (count >= 2 && ((u64)to & 1) == ((u64)from & 1)) { count -= 2; do { __raw_writew(*(const u16 *)from, to); count -= 2; to += 2; from += 2; } while (count >= 0); count += 2; } while (count > 0) { __raw_writeb(*(const u8 *) from, to); count--; to++; from++; } mb(); }
static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { int dev, busno, func; struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus); void __iomem *cfgdata = (void __iomem *)(unsigned long)&pcicptr->g2pcfgdata; busno = bus->number; dev = PCI_SLOT(devfn); func = PCI_FUNC(devfn); /* check if the bus is top-level */ if (bus->parent != NULL) { busno = bus->number; } else { busno = 0; } if (mkaddr(busno, devfn, where, pcicptr)) return -1; switch (size) { case 1: #ifdef __BIG_ENDIAN cfgdata += (where & 3) ^ 3; #else cfgdata += where & 3; #endif __raw_writeb(val, cfgdata); break; case 2: #ifdef __BIG_ENDIAN cfgdata += (where & 2) ^ 2; #else cfgdata += where & 2; #endif __raw_writew(val, cfgdata); break; case 4: __raw_writel(val, cfgdata); break; } return check_abort(pcicptr); }
static void anubis_nand_select(struct s3c2410_nand_set *set, int slot) { unsigned int tmp; slot = set->nr_map[slot] & 3; pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n", slot, set, set->nr_map); tmp = __raw_readb(ANUBIS_VA_CTRL1); tmp &= ~ANUBIS_CTRL1_NANDSEL; tmp |= slot; pr_debug("anubis_nand: ctrl1 now %02x\n", tmp); __raw_writeb(tmp, ANUBIS_VA_CTRL1); }
static void ocelot_ram_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf) { struct map_info *map = mtd->priv; size_t done = 0; /* If we use memcpy, it does word-wide writes. Even though we told the GT64120A that it's an 8-bit wide region, word-wide writes don't work. We end up just writing the first byte of the four to all four bytes. So we have this loop instead */ *retlen = len; while(len) { __raw_writeb(*(unsigned char *) from, map->virt + to); from++; to++; len--; } }
static void osiris_nand_select(struct s3c2410_nand_set *set, int slot) { unsigned int tmp; slot = set->nr_map[slot] & 3; pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n", slot, set, set->nr_map); tmp = __raw_readb(OSIRIS_VA_CTRL0); tmp &= ~OSIRIS_CTRL0_NANDSEL; tmp |= slot; pr_debug("osiris_nand: ctrl0 now %02x\n", tmp); __raw_writeb(tmp, OSIRIS_VA_CTRL0); }
static void gpio_write_raw_reg(unsigned long reg, unsigned long reg_width, unsigned long data) { switch (reg_width) { case 8: __raw_writeb(data, reg); return; case 16: __raw_writew(data, reg); return; case 32: __raw_writel(data, reg); return; } BUG(); }
static void bast_nand_select(struct s3c2410_nand_set *set, int slot) { unsigned int tmp; slot = set->nr_map[slot] & 3; pr_debug("bast_nand: selecting slot %d (set %p,%p)\n", slot, set, set->nr_map); tmp = __raw_readb(BAST_VA_CTRL2); tmp &= BAST_CPLD_CTLR2_IDERST; tmp |= slot; tmp |= BAST_CPLD_CTRL2_WNAND; pr_debug("bast_nand: ctrl2 now %02x\n", tmp); __raw_writeb(tmp, BAST_VA_CTRL2); }
static void ts72xx_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *chip = mtd->priv; if (ctrl & NAND_CTRL_CHANGE) { void __iomem *addr = chip->IO_ADDR_R; unsigned char bits; addr += (1 << TS72XX_NAND_CONTROL_ADDR_LINE); bits = __raw_readb(addr) & ~0x07; bits |= (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */ bits |= (ctrl & NAND_CLE); /* bit 1 -> bit 1 */ bits |= (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */ __raw_writeb(bits, addr); }
static void simtec_nor_vpp(struct map_info *map, int vpp) { unsigned int val; unsigned long flags; local_irq_save(flags); val = __raw_readb(BAST_VA_CTRL3); printk(KERN_DEBUG "%s(%d)\n", __func__, vpp); if (vpp) val |= BAST_CPLD_CTRL3_ROMWEN; else val &= ~BAST_CPLD_CTRL3_ROMWEN; __raw_writeb(val, BAST_VA_CTRL3); local_irq_restore(flags); }