static int f3s_devices_init(void)
{
babbage_mmu_init();
register_device(&sdram_dev);
register_device(&fec_dev);
register_device(&esdhc_dev);
spi_register_board_info(mx51_babbage_spi_board_info,
ARRAY_SIZE(mx51_babbage_spi_board_info));
register_device(&spi_dev);
babbage_power_init();
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0x90000100);
armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE);
return 0;
}
static int eukrea_cpuimx35_devices_init(void)
{
register_device(&nand_dev);
devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
register_device(&fec_dev);
register_device(&sdram_dev);
register_device(&imxfb_dev);
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX35);
return 0;
}
static int dss11_devices_init(void)
{
dss11_add_device_nand();
dss11_phy_reset();
at91_add_device_eth(0, &macb_pdata);
at91_add_device_mci(0, &dss11_mci_data);
at91_add_device_usbh_ohci(&dss11_usbh_data);
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
armlinux_set_architecture(MACH_TYPE_DSS11);
devfs_add_partition("nand0", 0x00000, 0x20000, DEVFS_PARTITION_FIXED, "bootstrap");
dev_add_bb_dev("bootstrap", "bootstrap.bb");
devfs_add_partition("nand0", 0x20000, 0x40000, DEVFS_PARTITION_FIXED, "barebox");
dev_add_bb_dev("barebox", "barebox.bb");
devfs_add_partition("nand0", 0x60000, 0x40000, DEVFS_PARTITION_FIXED, "barebox-env");
dev_add_bb_dev("barebox-env", "env0");
return 0;
}
static int at91sam9x5ek_devices_init(void)
{
ek_add_device_nand();
at91_add_device_eth(0, &macb_pdata);
at91_add_device_usbh_ohci(&ek_usbh_data);
ek_add_led();
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
armlinux_set_architecture(CONFIG_MACH_AT91SAM9X5EK);
devfs_add_partition("nand0", 0x00000, SZ_256K, PARTITION_FIXED, "at91bootstrap_raw");
dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap");
devfs_add_partition("nand0", SZ_256K, SZ_256K + SZ_128K, PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_512K + SZ_128K, SZ_128K, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
devfs_add_partition("nand0", SZ_512K + SZ_256K, SZ_128K, PARTITION_FIXED, "env_raw1");
dev_add_bb_dev("env_raw1", "env1");
return 0;
}
static int f3s_devices_init(void)
{
imx51_iim_register_fec_ethaddr();
imx51_add_fec(&fec_info);
imx51_add_mmc0(NULL);
spi_register_board_info(mx51_babbage_spi_board_info,
ARRAY_SIZE(mx51_babbage_spi_board_info));
imx51_add_spi0(&spi_0_data);
babbage_power_init();
console_flush();
imx51_init_lowlevel();
clock_notifier_call_chain();
armlinux_set_bootparams((void *)0x90000100);
armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE);
return 0;
}
static int mmccpu_devices_init(void)
{
/*
* PB27 enables the 50MHz oscillator for Ethernet PHY
* 1 - enable
* 0 - disable
*/
at91_set_gpio_output(AT91_PIN_PB27, 1);
at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
at91_add_device_eth(&macb_pdata);
add_cfi_flash_device(0, AT91_CHIPSELECT_0, 0, 0);
devfs_add_partition("nor0", 0x00000, 256 * 1024, PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 128 * 1024, PARTITION_FIXED, "env0");
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
armlinux_set_architecture(MACH_TYPE_MMCCPU);
return 0;
}
static int tny_a9260_devices_init(void)
{
tny_a9260_add_device_nand();
ek_add_device_macb();
ek_add_device_udc();
ek_add_device_spi();
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
tny_a9260_set_board_type();
devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw");
dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap");
devfs_add_partition("nand0", SZ_128K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
devfs_add_partition("nand0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw1");
dev_add_bb_dev("env_raw1", "env1");
return 0;
}
static int panda_devices_init(void)
{
panda_boardrev_init();
if (gpio_get_value(182)) {
/* enable software ioreq */
sr32(OMAP44XX_SCRM_AUXCLK3, 8, 1, 0x1);
/* set for sys_clk (38.4MHz) */
sr32(OMAP44XX_SCRM_AUXCLK3, 1, 2, 0x0);
/* set divisor to 2 */
sr32(OMAP44XX_SCRM_AUXCLK3, 16, 4, 0x1);
/* set the clock source to active */
sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1);
/* enable clocks */
sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
} else {
/* enable software ioreq */
sr32(OMAP44XX_SCRM_AUXCLK1, 8, 1, 0x1);
/* set for PER_DPLL */
sr32(OMAP44XX_SCRM_AUXCLK1, 1, 2, 0x2);
/* set divisor to 16 */
sr32(OMAP44XX_SCRM_AUXCLK1, 16, 4, 0xf);
/* set the clock source to active */
sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1);
/* enable clocks */
sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
}
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
omap44xx_add_i2c1(NULL);
omap44xx_add_mmc1(NULL);
panda_ehci_init();
panda_led_init();
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_OMAP4_PANDA);
return 0;
}
static int tx53_devices_init(void)
{
imx53_iim_register_fec_ethaddr();
tx53_fec_init();
imx53_add_fec(&fec_info);
imx53_add_mmc0(&tx53_sd1_data);
imx53_add_nand(&nand_info);
armlinux_set_bootparams((void *)0x70000100);
armlinux_set_architecture(MACH_TYPE_TX53);
/* rev xx30 can boot from nand or USB */
imx53_bbu_internal_nand_register_handler("nand-xx30",
BBU_HANDLER_FLAG_DEFAULT, (void *)dcd_entry_xx30,
sizeof(dcd_entry_xx30), SZ_512K, 0);
/* rev 1011 can boot from MMC/SD, other bootsource currently unknown */
imx53_bbu_internal_mmc_register_handler("mmc-1011", "/dev/disk0",
0, (void *)dcd_entry_1011, sizeof(dcd_entry_1011), 0);
return 0;
}
static int eukrea_cpuimx51_devices_init(void)
{
imx51_add_fec(&fec_info);
#ifdef CONFIG_MCI_IMX_ESDHC
imx51_add_mmc0(NULL);
#endif
imx51_add_nand(&nand_info);
devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
gpio_direction_output(GPIO_LAN8700_RESET, 0);
gpio_set_value(GPIO_LAN8700_RESET, 1);
gpio_direction_output(GPIO_LCD_BL, 0);
armlinux_set_bootparams((void *)0x90000100);
armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX51SD);
return 0;
}
static int beagle_devices_init(void)
{
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
omap3_add_i2c1(NULL);
#ifdef CONFIG_USB_EHCI_OMAP
if (ehci_omap_init(&omap_ehci_pdata) >= 0)
omap3_add_ehci(&ehci_pdata);
#endif /* CONFIG_USB_EHCI_OMAP */
#ifdef CONFIG_OMAP_GPMC
/* WP is made high and WAIT1 active Low */
gpmc_generic_init(0x10);
#endif
omap_add_gpmc_nand_device(&nand_plat);
omap3_add_mmc1(NULL);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_OMAP3_BEAGLE);
return 0;
}
static int pcaaxl2_devices_init(void)
{
u32 value;
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
add_generic_device("i2c-omap", DEVICE_ID_DYNAMIC, NULL, 0x48070000, 0x1000,
IORESOURCE_MEM, NULL);
value = readl(OMAP4_CONTROL_PBIASLITE);
value &= ~OMAP4_MMC1_PBIASLITE_VMODE;
value |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ);
writel(value, OMAP4_CONTROL_PBIASLITE);
add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, 0x4809C100, SZ_4K,
IORESOURCE_MEM, &mmc_device);
gpmc_generic_init(0x10);
pcaaxl2_network_init();
omap_add_gpmc_nand_device(&nand_plat);
#ifdef CONFIG_PARTITION
devfs_add_partition("nand0", 0x00000, SZ_128K,
DEVFS_PARTITION_FIXED, "xload_raw");
dev_add_bb_dev("xload_raw", "xload");
devfs_add_partition("nand0", SZ_128K, SZ_256K,
DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_128K + SZ_256K, SZ_128K,
DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
#endif
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_PCAAXL2);
return 0;
}
static int qil_a9260_devices_init(void)
{
qil_a9260_add_device_nand();
qil_a9260_add_device_mci();
ek_add_led();
ek_add_device_button();
qil_a9260_add_device_mb();
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
armlinux_set_architecture(MACH_TYPE_QIL_A9260);
devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw");
dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap");
devfs_add_partition("nand0", SZ_128K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
devfs_add_partition("nand0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw1");
dev_add_bb_dev("env_raw1", "env1");
return 0;
}
static int archosg9_devices_init(void){
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
omap44xx_add_i2c1(NULL);
omap44xx_add_mmc1(NULL);
#if defined(CONFIG_KEYBOARD_TWL6030) && defined(CONFIG_KEYBOARD_GPIO)
add_generic_device_res("twl6030_pwrbtn", DEVICE_ID_DYNAMIC, 0, 0,
&pwrbtn_data);
add_gpio_keys_device(DEVICE_ID_DYNAMIC, &gk_data);
#endif
armlinux_set_bootparams((void *)0x80000100);
/*
* This should be:
* armlinux_set_architecture(MACH_TYPE_OMAP4_ARCHOSG9);
* But Archos has not registered it's board to arch/arm/tools/mach-types
* So here there is the hardcoded value
*/
armlinux_set_architecture(5032);
armlinux_set_revision(5);
armlinux_set_atag_appender(archos_append_atags);
return 0;
}
static int at91sam9263ek_devices_init(void)
{
/*
* PB27 enables the 50MHz oscillator for Ethernet PHY
* 1 - enable
* 0 - disable
*/
at91_set_gpio_output(AT91_PIN_PB27, 1);
at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
ek_add_device_nand();
at91_add_device_eth(0, &macb_pdata);
add_cfi_flash_device(0, AT91_CHIPSELECT_0, 8 * 1024 * 1024, 0);
ek_add_device_mci();
ek_device_add_leds();
ek_add_device_udc();
ek_add_device_buttons();
if (IS_ENABLED(CONFIG_DRIVER_CFI) && cdev_by_name("nor0")) {
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");
devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
} else if (IS_ENABLED(CONFIG_NAND_ATMEL)) {
devfs_add_partition("nand0", 0x00000, SZ_128K, PARTITION_FIXED, "at91bootstrap_raw");
dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap");
devfs_add_partition("nand0", SZ_128K, SZ_256K, PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
devfs_add_partition("nand0", SZ_512K, SZ_128K, PARTITION_FIXED, "env_raw1");
dev_add_bb_dev("env_raw1", "env1");
}
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
armlinux_set_architecture(MACH_TYPE_AT91SAM9263EK);
return 0;
}
static int loco_devices_init(void)
{
imx53_iim_register_fec_ethaddr();
loco_fec_reset();
imx53_add_fec(&fec_info);
imx53_add_mmc0(&loco_sd1_data);
imx53_add_mmc2(&loco_sd3_data);
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
imx53_add_i2c0(NULL);
if (IS_ENABLED(CONFIG_USB_EHCI))
loco_ehci_init();
set_silicon_rev(imx_silicon_revision());
armlinux_set_bootparams((void *)0x70000100);
armlinux_set_architecture(MACH_TYPE_MX53_LOCO);
imx53_bbu_internal_mmc_register_handler("mmc", "/dev/disk0",
BBU_HANDLER_FLAG_DEFAULT, dcd_entry, sizeof(dcd_entry), 0);
return 0;
}
static int cfa10036_devices_init(void)
{
int i;
/* initizalize muxing */
for (i = 0; i < ARRAY_SIZE(cfa10036_pads); i++)
imx_gpio_mode(cfa10036_pads[i]);
/* enable IOCLK0 to run at the PLL frequency */
imx_set_ioclk(0, 480000000);
/* run the SSP unit clock at 100 MHz */
imx_set_sspclk(0, 100000000, 1);
armlinux_set_bootparams((void *)IMX_MEMORY_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_CFA10036);
add_generic_device("mxs_mci", 0, NULL, IMX_SSP0_BASE, SZ_8K,
IORESOURCE_MEM, &mci_pdata);
add_generic_device("ocotp", 0, NULL, IMX_OCOTP_BASE, SZ_8K,
IORESOURCE_MEM, NULL);
return 0;
}
static int imx23_olinuxino_devices_init(void)
{
int i, rc;
/* initizalize gpios */
for (i = 0; i < ARRAY_SIZE(pad_setup); i++)
imx_gpio_mode(pad_setup[i]);
armlinux_set_bootparams((void *)IMX_MEMORY_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_IMX233_OLINUXINO);
add_generic_device("mxs_mci", DEVICE_ID_DYNAMIC, NULL, IMX_SSP1_BASE,
0x8000, IORESOURCE_MEM, &mci_pdata);
olinuxino_init_usb();
rc = envfs_register_partition("disk0", 1);
if (rc != 0)
printf("Cannot create the 'env0' persistent "
"environment storage (%d)\n", rc);
return 0;
}
static int at91sam9260ek_devices_init(void)
{
ek_add_device_nand();
at91sam9260ek_phy_reset();
at91_add_device_eth(&macb_pdata);
at91_add_device_usbh_ohci(&ek_usbh_data);
at91_add_device_udc(&ek_udc_data);
ek_usb_add_device_mci();
ek_add_device_buttons();
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
ek_set_board_type();
devfs_add_partition("nand0", 0x00000, SZ_128K, PARTITION_FIXED, "at91bootstrap_raw");
dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap");
devfs_add_partition("nand0", SZ_128K, SZ_256K, PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
devfs_add_partition("nand0", SZ_512K, SZ_128K, PARTITION_FIXED, "env_raw1");
dev_add_bb_dev("env_raw1", "env1");
return 0;
}
static int tx25_devices_init(void)
{
gpio_fec_active();
imx25_iim_register_fec_ethaddr();
imx25_add_fec(&fec_info);
if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14))
nand_info.width = 2;
imx25_add_nand(&nand_info);
devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_TX25);
armlinux_set_serial(imx_uid());
return 0;
}
static int do_bootm_aimage(struct image_data *data)
{
struct resource *snd_stage_res;
int fd, ret;
struct android_header __header, *header;
void *buf;
int to_read;
struct android_header_comp *cmp;
unsigned long mem_free;
unsigned long mem_start, mem_size;
ret = sdram_start_and_size(&mem_start, &mem_size);
if (ret)
return ret;
fd = open(data->os_file, O_RDONLY);
if (fd < 0) {
perror("open");
return 1;
}
header = &__header;
ret = read(fd, header, sizeof(*header));
if (ret < sizeof(*header)) {
printf("could not read %s\n", data->os_file);
goto err_out;
}
printf("Android Image for '%s'\n", header->name);
/*
* As on tftp we do not support lseek and we will just have to seek
* for the size of a page - 1 max just buffer instead to read to dummy
* data
*/
buf = xmalloc(header->page_size);
to_read = header->page_size - sizeof(*header);
ret = read_full(fd, buf, to_read);
if (ret < 0) {
printf("could not read dummy %d from %s\n", to_read, data->os_file);
goto err_out;
}
cmp = &header->kernel;
data->os_res = request_sdram_region("akernel", cmp->load_addr, cmp->size);
if (!data->os_res) {
pr_err("Cannot request region 0x%08x - 0x%08x, using default load address\n",
cmp->load_addr, cmp->size);
data->os_address = mem_start + PAGE_ALIGN(cmp->size * 4);
data->os_res = request_sdram_region("akernel", data->os_address, cmp->size);
if (!data->os_res) {
pr_err("Cannot request region 0x%08x - 0x%08x\n",
cmp->load_addr, cmp->size);
ret = -ENOMEM;
goto err_out;
}
}
ret = aimage_load_resource(fd, data->os_res, buf, header->page_size);
if (ret < 0) {
perror("could not read kernel");
goto err_out;
}
/*
* fastboot always expect a ramdisk
* in barebox we can be less restrictive
*/
cmp = &header->ramdisk;
if (cmp->size) {
data->initrd_res = request_sdram_region("ainitrd", cmp->load_addr, cmp->size);
if (!data->initrd_res) {
ret = -ENOMEM;
goto err_out;
}
ret = aimage_load_resource(fd, data->initrd_res, buf, header->page_size);
if (ret < 0) {
perror("could not read initrd");
goto err_out;
}
}
if (!getenv("aimage_noverwrite_bootargs"))
linux_bootargs_overwrite(header->cmdline);
if (!getenv("aimage_noverwrite_tags"))
armlinux_set_bootparams((void*)header->tags_addr);
cmp = &header->second_stage;
if (cmp->size) {
void (*second)(void);
snd_stage_res = request_sdram_region("asecond", cmp->load_addr, cmp->size);
if (!snd_stage_res) {
ret = -ENOMEM;
goto err_out;
}
ret = aimage_load_resource(fd, snd_stage_res, buf, header->page_size);
if (ret < 0) {
perror("could not read initrd");
goto err_out;
}
second = (void*)snd_stage_res->start;
shutdown_barebox();
second();
restart_machine();
}
close(fd);
/*
* Put devicetree right after initrd if present or after the kernel
* if not.
*/
if (data->initrd_res)
mem_free = PAGE_ALIGN(data->initrd_res->end);
else
mem_free = PAGE_ALIGN(data->os_res->end + SZ_1M);
return __do_bootm_linux(data, mem_free, 0);
err_out:
linux_bootargs_overwrite(NULL);
close(fd);
return ret;
}
static int neso_devices_init(void)
{
int i;
unsigned int mode[] = {
/* UART1 */
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
/* FEC */
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
/* SSI1 connected in AC97 style */
PC20_PF_SSI1_FS,
PC21_PF_SSI1_RXD,
PC22_PF_SSI1_TXD,
PC23_PF_SSI1_CLK,
/* LED 1 */
(GPIO_PORTB | 15 | GPIO_GPIO | GPIO_OUT),
/* LED 2 */
(GPIO_PORTB | 16 | GPIO_GPIO | GPIO_OUT),
/* CTOUCH reset */
(GPIO_PORTB | 17 | GPIO_GPIO | GPIO_OUT),
/* CTOUCH IRQ */
(GPIO_PORTB | 14 | GPIO_GPIO | GPIO_IN),
/* RTC IRQ */
(GPIO_PORTF | 14 | GPIO_GPIO | GPIO_IN),
/* SD change card detection */
(GPIO_PORTF | 17 | GPIO_GPIO | GPIO_IN),
/* SDHC1*/
PE18_PF_SD1_D0,
PE19_PF_SD1_D1,
PE20_PF_SD1_D2,
PE21_PF_SD1_D3,
PE22_PF_SD1_CMD,
PE23_PF_SD1_CLK,
/* I2C1 */
PD17_PF_I2C_DATA,
PD18_PF_I2C_CLK,
/* I2C2, for CTOUCH */
PC5_PF_I2C2_SDA,
PC6_PF_I2C2_SCL,
/* Connected to: Both USB phys and ethernet phy FIXME 1 = RESET? */
PE17_PF_RESET_OUT,
/* USB host */
(USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT),
PA0_PF_USBH2_CLK,
PA1_PF_USBH2_DIR,
PA3_PF_USBH2_NXT,
PA4_PF_USBH2_STP,
PD22_AF_USBH2_DATA0,
PD24_AF_USBH2_DATA1,
PD23_AF_USBH2_DATA2,
PD20_AF_USBH2_DATA3,
PD19_AF_USBH2_DATA4,
PD26_AF_USBH2_DATA5,
PD21_AF_USBH2_DATA6,
PA2_PF_USBH2_DATA7,
/* USB OTG */
(OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT),
PE24_PF_USBOTG_CLK,
PE2_PF_USBOTG_DIR,
PE0_PF_USBOTG_NXT,
PE1_PF_USBOTG_STP,
PC9_PF_USBOTG_DATA0,
PC11_PF_USBOTG_DATA1,
PC10_PF_USBOTG_DATA2,
PC13_PF_USBOTG_DATA3,
PC12_PF_USBOTG_DATA4,
PC7_PF_USBOTG_DATA5,
PC8_PF_USBOTG_DATA6,
PE25_PF_USBOTG_DATA7,
/* Display signals */
(LCD_POWER_GPIO | GPIO_GPIO | GPIO_OUT), /* LCD power: 1 = LCD on */
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA31_PF_OE_ACD, /* DE */
/* Backlight PWM (Use as gpio) */
(BACKLIGHT_POWER_GPIO | GPIO_GPIO | GPIO_OUT),
};
/* reset the chip select lines to the USB/OTG phys to avoid any hang */
gpio_direction_output(OTG_PHY_CS_GPIO, 1);
gpio_direction_output(USBH2_PHY_CS_GPIO, 1);
/* initialize gpios */
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
imx27_add_nand(&nand_info);
imx27_add_fb(&neso_fb_data);
#ifdef CONFIG_USB
neso_usbh_init();
add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL);
#endif
imx27_add_fec(&fec_info);
devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(MACH_TYPE_NESO);
return 0;
}
static int do_bootm_aimage(struct image_data *data)
{
struct resource *snd_stage_res;
int fd, ret;
struct android_header __header, *header;
void *buf;
int to_read;
struct android_header_comp *cmp;
fd = open(data->os_file, O_RDONLY);
if (fd < 0) {
perror("open");
return 1;
}
header = &__header;
ret = read(fd, header, sizeof(*header));
if (ret < sizeof(*header)) {
printf("could not read %s\n", data->os_file);
goto err_out;
}
printf("Android Image for '%s'\n", header->name);
/*
* As on tftp we do not support lseek and we will just have to seek
* for the size of a page - 1 max just buffer instead to read to dummy
* data
*/
buf = xmalloc(header->page_size);
to_read = header->page_size - sizeof(*header);
ret = read_full(fd, buf, to_read);
if (ret < 0) {
printf("could not read dummy %d from %s\n", to_read, data->os_file);
goto err_out;
}
cmp = &header->kernel;
data->os_res = request_sdram_region("akernel", cmp->load_addr, cmp->size);
if (!data->os_res) {
ret = -ENOMEM;
goto err_out;
}
ret = aimage_load_resource(fd, data->os_res, buf, header->page_size);
if (ret < 0) {
perror("could not read kernel");
goto err_out;
}
/*
* fastboot always expect a ramdisk
* in barebox we can be less restrictive
*/
cmp = &header->ramdisk;
if (cmp->size) {
data->initrd_res = request_sdram_region("ainitrd", cmp->load_addr, cmp->size);
if (!data->initrd_res) {
ret = -ENOMEM;
goto err_out;
}
ret = aimage_load_resource(fd, data->initrd_res, buf, header->page_size);
if (ret < 0) {
perror("could not read initrd");
goto err_out;
}
}
if (!getenv("aimage_noverwrite_bootargs"))
linux_bootargs_overwrite(header->cmdline);
if (!getenv("aimage_noverwrite_tags"))
armlinux_set_bootparams((void*)header->tags_addr);
cmp = &header->second_stage;
if (cmp->size) {
void (*second)(void);
snd_stage_res = request_sdram_region("asecond", cmp->load_addr, cmp->size);
if (!snd_stage_res) {
ret = -ENOMEM;
goto err_out;
}
ret = aimage_load_resource(fd, snd_stage_res, buf, header->page_size);
if (ret < 0) {
perror("could not read initrd");
goto err_out;
}
second = (void*)snd_stage_res->start;
shutdown_barebox();
second();
reset_cpu(0);
}
close(fd);
return __do_bootm_linux(data, 0);
err_out:
linux_bootargs_overwrite(NULL);
close(fd);
return ret;
}
static int eukrea_cpuimx27_devices_init(void)
{
char *envdev = "no";
int i;
unsigned int mode[] = {
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC | GPIO_PUEN,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
PD17_PF_I2C_DATA,
PD18_PF_I2C_CLK,
#ifdef CONFIG_DRIVER_SERIAL_IMX
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
#endif
#ifdef CONFIG_DRIVER_VIDEO_IMX
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA31_PF_OE_ACD,
GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT,
#endif
};
eukrea_cpuimx27_mmu_init();
/* configure 16 bit nor flash on cs0 */
CS0U = 0x00008F03;
CS0L = 0xA0330D01;
CS0A = 0x002208C0;
/* initialize gpios */
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
register_device(&cfi_dev);
#ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB
register_device(&cfi_dev1);
#endif
register_device(&nand_dev);
register_device(&sdram_dev);
PCCR0 |= PCCR0_I2C1_EN;
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
register_device(&i2c_dev);
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
envdev = "NOR";
printf("Using environment in %s Flash\n", envdev);
#ifdef CONFIG_DRIVER_VIDEO_IMX
register_device(&imxfb_dev);
gpio_direction_output(GPIO_PORTE | 5, 0);
gpio_set_value(GPIO_PORTE | 5, 1);
#endif
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(MACH_TYPE_CPUIMX27);
return 0;
}
static int pca100_devices_init(void)
{
int i;
struct device_d *nand;
unsigned int mode[] = {
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC | GPIO_PUEN,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
PD25_PF_CSPI1_RDY,
PD26_PF_CSPI1_SS2,
PD27_PF_CSPI1_SS1,
PD28_PF_CSPI1_SS0,
PD29_PF_CSPI1_SCLK,
PD30_PF_CSPI1_MISO,
PD31_PF_CSPI1_MOSI,
/* USB host 2 */
PA0_PF_USBH2_CLK,
PA1_PF_USBH2_DIR,
PA2_PF_USBH2_DATA7,
PA3_PF_USBH2_NXT,
PA4_PF_USBH2_STP,
PD19_AF_USBH2_DATA4,
PD20_AF_USBH2_DATA3,
PD21_AF_USBH2_DATA6,
PD22_AF_USBH2_DATA0,
PD23_AF_USBH2_DATA2,
PD24_AF_USBH2_DATA1,
PD26_AF_USBH2_DATA5,
/* SDHC */
PB4_PF_SD2_D0,
PB5_PF_SD2_D1,
PB6_PF_SD2_D2,
PB7_PF_SD2_D3,
PB8_PF_SD2_CMD,
PB9_PF_SD2_CLK,
PC7_PF_USBOTG_DATA5,
PC8_PF_USBOTG_DATA6,
PC9_PF_USBOTG_DATA0,
PC10_PF_USBOTG_DATA2,
PC11_PF_USBOTG_DATA1,
PC12_PF_USBOTG_DATA4,
PC13_PF_USBOTG_DATA3,
PE0_PF_USBOTG_NXT,
PE1_PF_USBOTG_STP,
PE2_PF_USBOTG_DIR,
PE24_PF_USBOTG_CLK,
PE25_PF_USBOTG_DATA7,
/* display */
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA26_PF_PS,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA31_PF_OE_ACD,
/* external I2C */
PD17_PF_I2C_DATA,
PD18_PF_I2C_CLK,
};
pca100_usb_init();
/* initizalize gpios */
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
imx27_add_nand(&nand_info);
imx27_add_fec(&fec_info);
imx27_add_mmc1(NULL);
imx27_add_fb(&pca100_fb_data);
#ifdef CONFIG_USB
pca100_usb_register();
#endif
nand = get_device_by_name("nand0");
devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(2149);
return 0;
}
static int pcm038_devices_init(void)
{
int i;
char *envdev;
unsigned int mode[] = {
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC | GPIO_PUEN,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_CLR,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
PD25_PF_CSPI1_RDY,
GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT,
PD29_PF_CSPI1_SCLK,
PD30_PF_CSPI1_MISO,
PD31_PF_CSPI1_MOSI,
/* display */
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA24_PF_REV,
PA25_PF_CLS,
PA26_PF_PS,
PA27_PF_SPL_SPR,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA30_PF_CONTRAST,
PA31_PF_OE_ACD,
/* USB host 2 */
PA0_PF_USBH2_CLK,
PA1_PF_USBH2_DIR,
PA2_PF_USBH2_DATA7,
PA3_PF_USBH2_NXT,
PA4_PF_USBH2_STP,
PD19_AF_USBH2_DATA4,
PD20_AF_USBH2_DATA3,
PD21_AF_USBH2_DATA6,
PD22_AF_USBH2_DATA0,
PD23_AF_USBH2_DATA2,
PD24_AF_USBH2_DATA1,
PD26_AF_USBH2_DATA5,
};
pcm038_mmu_init();
/* configure 16 bit nor flash on cs0 */
CS0U = 0x0000CC03;
CS0L = 0xa0330D01;
CS0A = 0x00220800;
/* configure SRAM on cs1 */
CS1U = 0x0000d843;
CS1L = 0x22252521;
CS1A = 0x22220a00;
/* configure SJA1000 on cs4 */
CS4U = 0x0000DCF6;
CS4L = 0x444A0301;
CS4A = 0x44443302;
/* initizalize gpios */
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
PCCR0 |= PCCR0_CSPI1_EN;
PCCR1 |= PCCR1_PERCLK2_EN;
gpio_direction_output(GPIO_PORTD | 28, 0);
gpio_set_value(GPIO_PORTD | 28, 0);
spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
register_device(&spi_dev);
register_device(&cfi_dev);
register_device(&nand_dev);
register_device(&sdram_dev);
register_device(&sram_dev);
register_device(&imxfb_dev);
#ifdef CONFIG_USB
pcm038_usbh_init();
register_device(&usbh2_dev);
#endif
/* Register the fec device after the PLL re-initialisation
* as the fec depends on the (now higher) ipg clock
*/
register_device(&fec_dev);
switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) {
case GPCR_BOOT_8BIT_NAND_2k:
case GPCR_BOOT_16BIT_NAND_2k:
case GPCR_BOOT_16BIT_NAND_512:
case GPCR_BOOT_8BIT_NAND_512:
devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
envdev = "NAND";
break;
default:
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
envdev = "NOR";
}
printf("Using environment in %s Flash\n", envdev);
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(MACH_TYPE_PCM038);
return 0;
}
static int imx25_devices_init(void)
{
ulong val;
/*
* Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.
* Assert FEC_RESET_B, then power up the PHY by asserting
* FEC_ENABLE, at the same time lifting FEC_RESET_B.
*
* FEC_RESET_B: gpio2[3] is ALT 5 mode of pin A17
* FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin D12
*/
writel(0x8, IOMUXC_BASE_ADDR + 0x0238); /* open drain */
writel(0x0, IOMUXC_BASE_ADDR + 0x028C); /* cmos, no pu/pd */
#define GPIO2_BASE_ADDR 0x53FD0000
#define GPIO4_BASE_ADDR 0x53F9C000
#define GPIO_GDIR 0x04
#define GPIO_DR 0x00
/* make the pins output */
val = (1 << 3) | readl(GPIO2_BASE_ADDR + GPIO_GDIR);
writel(val, GPIO2_BASE_ADDR + GPIO_GDIR);
val = (1 << 8) | readl(GPIO4_BASE_ADDR + GPIO_GDIR);
writel(val, GPIO4_BASE_ADDR + GPIO_GDIR);
/* drop PHY power */
val = readl(GPIO2_BASE_ADDR + GPIO_DR) & ~(1 << 3);
writel(val, GPIO2_BASE_ADDR + GPIO_DR);
/* assert reset */
val = readl(GPIO4_BASE_ADDR + GPIO_DR) & ~(1 << 8);
writel(val, GPIO4_BASE_ADDR + GPIO_DR);
udelay(2);
/* turn on power & lift reset */
val = (1 << 3) | readl(GPIO2_BASE_ADDR + GPIO_DR);
writel(val, GPIO2_BASE_ADDR + GPIO_DR);
val = (1 << 8) | readl(GPIO4_BASE_ADDR + GPIO_DR);
writel(val, GPIO4_BASE_ADDR + GPIO_DR);
#ifdef CONFIG_USB
/* USB does not work yet. Don't know why. Maybe
* the CPLD has to be initialized.
*/
imx25_usb_init();
register_device(&usbh2_dev);
#endif
/* FEC does only work when the CPLD is initialized.
* Currently we do not do this in barebox, so it
* does only work when Linux has been started after
* the last powercycle.
*/
register_device(&fec_dev);
if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14))
nand_info.width = 2;
register_device(&nand_dev);
devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
register_device(&sdram0_dev);
register_device(&sram0_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_MX25_3DS);
return 0;
}
static int pca100_devices_init(void)
{
int i;
struct device_d *nand;
unsigned int mode[] = {
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC | GPIO_PUEN,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_CLR,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
PD25_PF_CSPI1_RDY,
PD26_PF_CSPI1_SS2,
PD27_PF_CSPI1_SS1,
PD28_PF_CSPI1_SS0,
PD29_PF_CSPI1_SCLK,
PD30_PF_CSPI1_MISO,
PD31_PF_CSPI1_MOSI,
/* USB host 2 */
PA0_PF_USBH2_CLK,
PA1_PF_USBH2_DIR,
PA2_PF_USBH2_DATA7,
PA3_PF_USBH2_NXT,
PA4_PF_USBH2_STP,
PD19_AF_USBH2_DATA4,
PD20_AF_USBH2_DATA3,
PD21_AF_USBH2_DATA6,
PD22_AF_USBH2_DATA0,
PD23_AF_USBH2_DATA2,
PD24_AF_USBH2_DATA1,
PD26_AF_USBH2_DATA5,
};
/* disable the usb phys */
imx_gpio_mode((GPIO_PORTB | 23) | GPIO_GPIO | GPIO_IN);
gpio_direction_output(GPIO_PORTB + 23, 1);
imx_gpio_mode((GPIO_PORTB | 24) | GPIO_GPIO | GPIO_IN);
gpio_direction_output(GPIO_PORTB + 24, 1);
/* initizalize gpios */
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
register_device(&nand_dev);
register_device(&sdram_dev);
register_device(&fec_dev);
PCCR1 |= PCCR1_PERCLK2_EN;
#ifdef CONFIG_USB
pca100_usbh_init();
register_device(&usbh2_dev);
#endif
nand = get_device_by_name("nand0");
devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(2149);
return 0;
}
static int pcm038_devices_init(void)
{
int i;
u64 uid = 0;
char *envdev;
long sram_size;
unsigned int mode[] = {
/* FEC */
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC | GPIO_PUEN,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
PCM038_GPIO_FEC_RST | GPIO_GPIO | GPIO_OUT,
/* UART1 */
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
/* CSPI1 */
PD25_PF_CSPI1_RDY,
PD29_PF_CSPI1_SCLK,
PD30_PF_CSPI1_MISO,
PD31_PF_CSPI1_MOSI,
PCM038_GPIO_SPI_CS0 | GPIO_GPIO | GPIO_OUT,
#ifdef CONFIG_MACH_PCM970_BASEBOARD
PCM970_GPIO_SPI_CS1 | GPIO_GPIO | GPIO_OUT,
#endif
/* Display */
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA24_PF_REV,
PA25_PF_CLS,
PA26_PF_PS,
PA27_PF_SPL_SPR,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA30_PF_CONTRAST,
PA31_PF_OE_ACD,
/* USB OTG */
PC7_PF_USBOTG_DATA5,
PC8_PF_USBOTG_DATA6,
PC9_PF_USBOTG_DATA0,
PC10_PF_USBOTG_DATA2,
PC11_PF_USBOTG_DATA1,
PC12_PF_USBOTG_DATA4,
PC13_PF_USBOTG_DATA3,
PE0_PF_USBOTG_NXT,
PCM038_GPIO_OTG_STP | GPIO_GPIO | GPIO_OUT,
PE2_PF_USBOTG_DIR,
PE24_PF_USBOTG_CLK,
PE25_PF_USBOTG_DATA7,
/* I2C1 */
PD17_PF_I2C_DATA | GPIO_PUEN,
PD18_PF_I2C_CLK,
/* I2C2 */
PC5_PF_I2C2_SDA,
PC6_PF_I2C2_SCL,
};
/* configure 16 bit nor flash on cs0 */
imx27_setup_weimcs(0, 0x22C2CF00, 0x75000D01, 0x00000900);
/* configure SRAM on cs1 */
imx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);
/* SRAM can be up to 2MiB */
sram_size = get_ram_size((ulong *)MX27_CS1_BASE_ADDR, SZ_2M);
if (sram_size)
add_mem_device("ram1", MX27_CS1_BASE_ADDR, sram_size,
IORESOURCE_MEM_WRITEABLE);
/* initizalize gpios */
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
imx27_add_spi0(&pcm038_spi_0_data);
pcm038_power_init();
add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0);
imx27_add_nand(&nand_info);
imx27_add_fb(&pcm038_fb_data);
imx27_add_i2c0(NULL);
imx27_add_i2c1(NULL);
/* Register the fec device after the PLL re-initialisation
* as the fec depends on the (now higher) ipg clock
*/
gpio_set_value(PCM038_GPIO_FEC_RST, 1);
imx27_add_fec(&fec_info);
/* Apply delay for STP line to stop ULPI */
gpio_direction_output(PCM038_GPIO_OTG_STP, 1);
mdelay(1);
imx_gpio_mode(PE1_PF_USBOTG_STP);
imx27_add_usbotg(&pcm038_otg_pdata);
switch (bootsource_get()) {
case BOOTSOURCE_NAND:
devfs_add_partition("nand0", 0, SZ_512K,
DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_512K, SZ_128K,
DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
envdev = "NAND";
break;
default:
devfs_add_partition("nor0", 0, SZ_512K,
DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", SZ_512K, SZ_128K,
DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
envdev = "NOR";
}
pr_notice("Using environment in %s Flash\n", envdev);
if (imx_iim_read(1, 0, &uid, 6) == 6)
armlinux_set_serial(uid);
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(MACH_TYPE_PCM038);
return 0;
}