void __init at91_add_device_nand(struct atmel_nand_data *data) { unsigned int csa; if (!data) return; /* enable the address range of CS3 */ csa = at91_sys_read(AT91_EBI_CSA); at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA); /* set the bus interface characteristics */ at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN | AT91_SMC_NWS_(5) | AT91_SMC_TDF_(1) | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */ | AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */ ); /* enable pin */ if (data->enable_pin) at91_set_gpio_output(data->enable_pin, 1); /* ready/busy pin */ if (data->rdy_pin) at91_set_gpio_input(data->rdy_pin, 1); /* card detect pin */ if (data->det_pin) at91_set_gpio_input(data->det_pin, 1); at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */ at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */ nand_data = *data; platform_device_register(&at91rm9200_nand_device); }
/* Consider only one slot : slot 0 */ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) { struct device_d *dev; if (!data) return; /* need bus_width */ if (!data->bus_width) return; /* input/irq */ if (data->detect_pin) { at91_set_gpio_input(data->detect_pin, 1); at91_set_deglitch(data->detect_pin, 1); } if (data->wp_pin) at91_set_gpio_input(data->wp_pin, 1); /* CLK */ at91_set_B_periph(AT91_PIN_PA2, 0); /* CMD */ at91_set_B_periph(AT91_PIN_PA1, 1); /* DAT0, maybe DAT1..DAT3 */ at91_set_B_periph(AT91_PIN_PA0, 1); if (data->bus_width == 4) { at91_set_B_periph(AT91_PIN_PA4, 1); at91_set_B_periph(AT91_PIN_PA5, 1); at91_set_B_periph(AT91_PIN_PA6, 1); } dev = add_generic_device("atmel_mci", 0, NULL, AT91SAM9261_BASE_MCI, SZ_16K, IORESOURCE_MEM, data); }
void __init at91_add_device_nand(struct atmel_nand_data *data) { if (!data) return; switch (data->pmecc_sector_size) { case 512: data->pmecc_lookup_table_offset = 0x10000; break; case 1024: data->pmecc_lookup_table_offset = 0x18000; break; default: pr_err("%s: invalid pmecc_sector_size (%d)\n", __func__, data->pmecc_sector_size); return; } at91_set_A_periph(AT91_PIN_PE21, 1); /* ALE */ at91_set_A_periph(AT91_PIN_PE22, 1); /* CLE */ /* enable pin */ if (gpio_is_valid(data->enable_pin)) at91_set_gpio_output(data->enable_pin, 1); /* ready/busy pin */ if (gpio_is_valid(data->rdy_pin)) at91_set_gpio_input(data->rdy_pin, 1); /* card detect pin */ if (gpio_is_valid(data->det_pin)) at91_set_gpio_input(data->det_pin, 1); add_generic_device_res("atmel_nand", 0, nand_resources, ARRAY_SIZE(nand_resources), data); }
void __init at91_add_device_udc(struct at91_udc_data *data) { if (!data) return; if (data->vbus_pin) { at91_set_gpio_input(data->vbus_pin, 0); at91_set_deglitch(data->vbus_pin, 1); } /* Pullup pin is handled internally by USB device peripheral */ udc_data = *data; platform_device_register(&at91_udc_device); }
int get_productID(void) { int gpio_num,val_gpio; for(gpio_num = AT91_PIN_PC6,val_gpio = 0 ; gpio_num <= AT91_PIN_PC10 ; gpio_num++) { at91_set_gpio_input(gpio_num,PULLUP_ENABLE); udelay(1); val_gpio = at91_get_gpio_value(gpio_num); udelay(1); productID |= ( val_gpio << ( gpio_num - AT91_PIN_PC6)); } return productID; }
void __init at91_add_device_udc(struct at91_udc_data *data) { if (!data) return; if (gpio_is_valid(data->vbus_pin)) { at91_set_gpio_input(data->vbus_pin, 0); at91_set_deglitch(data->vbus_pin, 1); } if (gpio_is_valid(data->pullup_pin)) at91_set_gpio_output(data->pullup_pin, 0); udc_data = *data; platform_device_register(&at91rm9200_udc_device); }
static void cpu9260_nand_hw_init(void) { unsigned long csa; /* Enable CS3 */ csa = at91_sys_read(AT91_MATRIX_EBICSA); at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); /* Configure SMC CS3 for NAND/SmartMedia */ #if defined(CONFIG_CPU9G20) at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(4) | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(4)); at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8 | AT91_SMC_TDF_(3)); #elif defined(CONFIG_CPU9260) at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8 | AT91_SMC_TDF_(2)); #endif at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); }
static void __init ek_add_device_dm9000(void) { struct resource *r = &dm9000_resource[2]; /* Configure chip-select 2 (DM9000) */ sam9_smc_configure(0, 2, &dm9000_smc_config); /* Configure Reset signal as output */ at91_set_gpio_output(AT91_PIN_PC10, 0); /* Configure Interrupt pin as input, no pull-up */ at91_set_gpio_input(AT91_PIN_PC11, 0); r->start = r->end = gpio_to_irq(AT91_PIN_PC11); platform_device_register(&dm9000_device); }
void __init at91_add_device_usbh(struct at91_usbh_data *data) { int i; if (!data) return; /* Enable overcurrent notification */ for (i = 0; i < data->ports; i++) { if (data->overcurrent_pin[i]) at91_set_gpio_input(data->overcurrent_pin[i], 1); } usbh_data = *data; platform_device_register(&at91rm9200_usbh_device); }
static int pm9263_devices_init(void) { at91_set_gpio_input(w1_pdata.pin, 0); add_generic_device_res("w1-gpio", DEVICE_ID_SINGLE, NULL, 0, &w1_pdata); pm_add_device_nand(); pm9263_add_device_eth(); add_cfi_flash_device(0, AT91_CHIPSELECT_0, 4 * 1024 * 1024, 0); devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0"); devfs_add_partition("nor0", 0x40000, 0x10000, DEVFS_PARTITION_FIXED, "env0"); armlinux_set_architecture(MACH_TYPE_PM9263); return 0; }
static void __init ek_add_device_dm9000(void) { struct resource *r = &dm9000_resource[2]; sam9_smc_configure(0, 2, &dm9000_smc_config); at91_set_gpio_output(AT91_PIN_PC10, 0); at91_set_gpio_input(AT91_PIN_PC11, 0); r->start = r->end = gpio_to_irq(AT91_PIN_PC11); platform_device_register(&dm9000_device); }
void __init at91_add_device_usba(struct usba_platform_data *data) { usba_udc_data.pdata.vbus_pin = -EINVAL; usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep); memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep)); if (data && gpio_is_valid(data->vbus_pin)) { at91_set_gpio_input(data->vbus_pin, 0); at91_set_deglitch(data->vbus_pin, 1); usba_udc_data.pdata.vbus_pin = data->vbus_pin; } /* Pullup pin is handled internally by USB device peripheral */ platform_device_register(&at91_usba_udc_device); }
static void qil_a9260_phy_reset(void) { at91_set_gpio_input(AT91_PIN_PA14, 0); at91_set_gpio_input(AT91_PIN_PA15, 0); at91_set_gpio_input(AT91_PIN_PA17, 0); at91_set_gpio_input(AT91_PIN_PA25, 0); at91_set_gpio_input(AT91_PIN_PA26, 0); at91_set_gpio_input(AT91_PIN_PA28, 0); at91sam_phy_reset(IOMEM(AT91SAM9260_BASE_RSTC)); }
void __init at91_add_device_udc(struct at91_udc_data *data) { unsigned long x; if (!data) return; if (data->vbus_pin) { at91_set_gpio_input(data->vbus_pin, 0); at91_set_deglitch(data->vbus_pin, 1); } /* Pullup pin is handled internally */ x = at91_sys_read(AT91_MATRIX_USBPUCR); at91_sys_write(AT91_MATRIX_USBPUCR, x | AT91_MATRIX_USBPUCR_PUON); udc_data = *data; platform_device_register(&at91sam9261_udc_device); }
void __init at91_add_device_usba(struct usba_platform_data *data) { usba_udc_data.pdata.vbus_pin = -EINVAL; usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep); memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));; if (data && data->vbus_pin > 0) { at91_set_gpio_input(data->vbus_pin, 0); at91_set_deglitch(data->vbus_pin, 1); usba_udc_data.pdata.vbus_pin = data->vbus_pin; } /* Pullup pin is handled internally by USB device peripheral */ /* Clocks */ at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk"); at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk"); platform_device_register(&at91_usba_udc_device); }
int get_productID(void) { int gpio_num,val_gpio; #if 0 for(gpio_num = AT91_PIN_PC6,val_gpio = 0 ; gpio_num <= AT91_PIN_PC10 ; gpio_num++) { at91_set_gpio_input(gpio_num,PULLUP_ENABLE); udelay(1); val_gpio = at91_get_gpio_value(gpio_num); udelay(1); productID |= ( val_gpio << ( gpio_num - AT91_PIN_PC6)); } #endif at91_get_gpio_register(AT91_PIN_PA0); at91_get_gpio_register(AT91_PIN_PB0); at91_get_gpio_register(AT91_PIN_PC0); return productID; }
static void __init ek_add_device_dm9000(void) { /* * Configure Chip-Select 2 on SMC for the DM9000. * Note: These timings were calculated for MASTER_CLOCK = 100000000 * according to the DM9000 timings. */ at91_sys_write(AT91_SMC_SETUP(2), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); at91_sys_write(AT91_SMC_PULSE(2), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); at91_sys_write(AT91_SMC_CYCLE(2), AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); at91_sys_write(AT91_SMC_MODE(2), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | AT91_SMC_TDF_(1)); /* Configure Reset signal as output */ at91_set_gpio_output(AT91_PIN_PC10, 0); /* Configure Interrupt pin as input, no pull-up */ at91_set_gpio_input(AT91_PIN_PC11, 0); platform_device_register(&at91sam9261_dm9000_device); }
/* * Miscelaneous platform dependent initialisations */ static void wb45n_nand_hw_init(void) { struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; unsigned long csa; csa = readl(&matrix->ebicsa); /* Enable CS3 */ csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; /* NAND flash on D0 */ csa &= ~AT91_MATRIX_NFD0_ON_D16; writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), &smc->cs[3].setup); writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), &smc->cs[3].pulse); writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6), &smc->cs[3].cycle); writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | AT91_SMC_MODE_EXNW_DISABLE | AT91_SMC_MODE_DBW_8 | AT91_SMC_MODE_TDF_CYCLE(1), &smc->cs[3].mode); at91_periph_clk_enable(ATMEL_ID_PIOCD); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); /* Disable Flash Write Protect Line */ at91_set_gpio_output(AT91_PIN_PD10, 1); at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ }
void __init at91_add_device_usba(struct usba_platform_data *data) { /* * Invalid pins are 0 on AT91, but the usba driver is shared * with AVR32, which use negative values instead. Once/if * gpio_is_valid() is ported to AT91, revisit this code. */ usba_udc_data.pdata.vbus_pin = -EINVAL; usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep); memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep)); if (data && gpio_is_valid(data->vbus_pin)) { at91_set_gpio_input(data->vbus_pin, 0); at91_set_deglitch(data->vbus_pin, 1); usba_udc_data.pdata.vbus_pin = data->vbus_pin; } /* Pullup pin is handled internally by USB device peripheral */ platform_device_register(&at91_usba_udc_device); }
static int pm9g45_devices_init(void) { at91_set_gpio_input(w1_pdata.pin, 0); add_generic_device_res("w1-gpio", DEVICE_ID_SINGLE, NULL, 0, &w1_pdata); pm_add_device_nand(); pm9g45_add_device_mci(); pm9g45_add_device_eth(); pm9g45_add_device_usbh(); devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw"); dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap"); devfs_add_partition("nand0", SZ_128K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw"); dev_add_bb_dev("self_raw", "self0"); devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw"); dev_add_bb_dev("env_raw", "env0"); armlinux_set_architecture(MACH_TYPE_PM9G45); return 0; }
static void at91sam9261ek_nand_hw_init(void) { unsigned long csa; /* Enable CS3 */ csa = at91_sys_read(AT91_MATRIX_EBICSA); at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); /* Configure SMC CS3 for NAND/SmartMedia */ at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | #ifdef CFG_NAND_DBW_16 AT91_SMC_DBW_16 | #else /* CFG_NAND_DBW_8 */ AT91_SMC_DBW_8 | #endif AT91_SMC_TDF_(2)); at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); /* Configure RDY/BSY */ at91_set_gpio_input(AT91_PIN_PC15, 1); /* Enable NandFlash */ at91_set_gpio_output(AT91_PIN_PC14, 1); at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ }
static void sbc35_a9g20_nand_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; unsigned long csa; /* Enable CS3 */ csa = readl(&matrix->ebicsa); csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), &smc->cs[3].setup); writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), &smc->cs[3].pulse); writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), &smc->cs[3].cycle); writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ AT91_SMC_MODE_DBW_8 | #endif AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode); writel(1 << ATMEL_ID_PIOC, &pmc->pcer); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); }
void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) { int i; if (!data) return; /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { if (gpio_is_valid(data->vbus_pin[i])) at91_set_gpio_output(data->vbus_pin[i], 0); } /* Enable overcurrent notification */ for (i = 0; i < data->ports; i++) { if (data->overcurrent_pin[i]) at91_set_gpio_input(data->overcurrent_pin[i], 1); } usbh_ohci_data = *data; platform_device_register(&at91_usbh_ohci_device); }
static void __init csb337_board_init(void) { /* Serial */ at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&csb337_eth_data); /* USB Host */ at91_add_device_usbh(&csb337_usbh_data); /* USB Device */ at91_add_device_udc(&csb337_udc_data); /* I2C */ at91_add_device_i2c(csb337_i2c_devices, ARRAY_SIZE(csb337_i2c_devices)); /* Compact Flash */ at91_set_gpio_input(AT91_PIN_PB22, 1); /* IOIS16 */ at91_add_device_cf(&csb337_cf_data); /* SPI */ at91_add_device_spi(csb337_spi_devices, ARRAY_SIZE(csb337_spi_devices)); /* MMC */ at91_add_device_mmc(0, &csb337_mmc_data); /* NOR flash */ platform_device_register(&csb_flash); }
void __init at91_add_device_usbh(struct at91_usbh_data *data) { int i; if (!data) return; for (i = 0; i < data->ports; i++) { if (gpio_is_valid(data->vbus_pin[i])) at91_set_gpio_output(data->vbus_pin[i], data->vbus_pin_active_low[i]); } for (i = 0; i < data->ports; i++) { if (data->overcurrent_pin[i]) at91_set_gpio_input(data->overcurrent_pin[i], 1); } usbh_data = *data; platform_device_register(&at91_usbh_device); }
static void at91sam9261ek_dm9000_hw_init(void) { /* Configure SMC CS2 for DM9000 */ at91_sys_write(AT91_SMC_SETUP(2), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); at91_sys_write(AT91_SMC_PULSE(2), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); at91_sys_write(AT91_SMC_CYCLE(2), AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); at91_sys_write(AT91_SMC_MODE(2), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | AT91_SMC_TDF_(1)); /* Configure Reset signal as output */ at91_set_gpio_output(AT91_PIN_PC10, 0); /* Configure Interrupt pin as input, no pull-up */ at91_set_gpio_input(AT91_PIN_PC11, 0); }
void __init at91_add_device_eth(struct macb_platform_data *data) { if (!data) return; if (gpio_is_valid(data->phy_irq_pin)) { at91_set_gpio_input(data->phy_irq_pin, 0); at91_set_deglitch(data->phy_irq_pin, 1); } /* Pins used for MII and RMII */ at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */ at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */ at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */ at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */ at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */ at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */ at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */ at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */ at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */ at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */ if (!data->is_rmii) { at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */ at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */ at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */ at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */ at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */ at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */ } eth_data = *data; platform_device_register(&at91sam9263_eth_device); }
void spl_board_init(void) { corvus_request_gpio(); /* * For on the sam9m10g45ek board, the chip wm9711 stay in the test * mode, so it need do some action to exit mode. */ at91_set_gpio_output(AT91_PIN_PD7, 0); at91_set_gpio_output(AT91_PIN_PD8, 0); at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1); at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1); at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); corvus_nand_hw_init(); /* Configure recovery button PINs */ at91_set_gpio_input(AT91_PIN_PB7, 1); /* check if button is pressed */ if (at91_get_gpio_value(AT91_PIN_PB7) == 0) { u32 boot_device; debug("Recovery button pressed\n"); boot_device = spl_boot_device(); switch (boot_device) { #ifdef CONFIG_SPL_NAND_SUPPORT case BOOT_DEVICE_NAND: nand_init(); spl_nand_erase_one(0, 0); break; #endif } } }
void __init at91_add_device_eth(struct macb_platform_data *data) { if (!data) return; if (gpio_is_valid(data->phy_irq_pin)) { at91_set_gpio_input(data->phy_irq_pin, 0); at91_set_deglitch(data->phy_irq_pin, 1); } /* Pins used for MII and RMII */ at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */ at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */ at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */ at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */ at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */ at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */ at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */ at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */ at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */ at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */ if (!data->is_rmii) { at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */ at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */ at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */ at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */ at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */ at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */ at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */ at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */ } eth_data = *data; platform_device_register(&at91rm9200_eth_device); }
void __init at91_add_device_eth(struct at91_eth_data *data) { if (!data) return; if (data->phy_irq_pin) { at91_set_gpio_input(data->phy_irq_pin, 0); at91_set_deglitch(data->phy_irq_pin, 1); } /* Pins used for MII and RMII */ at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */ at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */ at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */ at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */ at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */ at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */ at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */ at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */ at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */ at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */ if (!data->is_rmii) { at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */ at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */ at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */ at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */ at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */ at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */ at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */ at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */ } eth_data = *data; platform_device_register(&at91sam9260_eth_device); }