/** * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU * * @ah: The &struct ath5k_hw * @timeout: Timeout in usec */ static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout) { if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS)) <= timeout) return -EINVAL; AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, ath5k_hw_htoclock(ah, timeout)); return 0; }
/** * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU * * @ah: The &struct ath5k_hw * @timeout: Timeout in usec */ int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout) { if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK), ah->ah_turbo) <= timeout) return -EINVAL; AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, ath5k_hw_htoclock(timeout, ah->ah_turbo)); return 0; }
/** * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU * * @ah: The &struct ath5k_hw * @timeout: Timeout in usec */ int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout) { ATH5K_TRACE(ah->ah_sc); if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK)) <= timeout) return -EINVAL; AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, ath5k_hw_htoclock(ah, timeout)); return 0; }
/** * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU * * @ah: The &struct ath5k_hw * @timeout: Timeout in usec */ int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout) { ATH5K_TRACE(ah->ah_sc); if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS), ah->ah_turbo) <= timeout) return -EINVAL; AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, ath5k_hw_htoclock(timeout, ah->ah_turbo)); return 0; }
/** * ath5k_hw_set_ifs_intervals - Set global inter-frame spaces on DCU * * @ah The &struct ath5k_hw * @slot_time Slot time in us * * Sets the global IFS intervals on DCU (also works on AR5210) for * the given slot time and the current bwmode. */ int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time) { struct ieee80211_channel *channel = ah->ah_current_channel; struct ieee80211_rate *rate; u32 ack_tx_time, eifs, eifs_clock, sifs, sifs_clock; u32 slot_time_clock = ath5k_hw_htoclock(ah, slot_time); if (slot_time < 6 || slot_time_clock > AR5K_SLOT_TIME_MAX) return -EINVAL; sifs = ath5k_hw_get_default_sifs(ah); sifs_clock = ath5k_hw_htoclock(ah, sifs - 2); /* EIFS * Txtime of ack at lowest rate + SIFS + DIFS * (DIFS = SIFS + 2 * Slot time) * * Note: HAL has some predefined values for EIFS * Turbo: (37 + 2 * 6) * Default: (74 + 2 * 9) * Half: (149 + 2 * 13) * Quarter: (298 + 2 * 21) * * (74 + 2 * 6) for AR5210 default and turbo ! * * According to the formula we have * ack_tx_time = 25 for turbo and * ack_tx_time = 42.5 * clock multiplier * for default/half/quarter. * * This can't be right, 42 is what we would get * from ath5k_hw_get_frame_dur_for_bwmode or * ieee80211_generic_frame_duration for zero frame * length and without SIFS ! * * Also we have different lowest rate for 802.11a */ if (channel->band == IEEE80211_BAND_5GHZ) rate = &ah->sbands[IEEE80211_BAND_5GHZ].bitrates[0]; else rate = &ah->sbands[IEEE80211_BAND_2GHZ].bitrates[0]; ack_tx_time = ath5k_hw_get_frame_duration(ah, 10, rate, false); /* ack_tx_time includes an SIFS already */ eifs = ack_tx_time + sifs + 2 * slot_time; eifs_clock = ath5k_hw_htoclock(ah, eifs); /* Set IFS settings on AR5210 */ if (ah->ah_version == AR5K_AR5210) { u32 pifs, pifs_clock, difs, difs_clock; /* Set slot time */ ath5k_hw_reg_write(ah, slot_time_clock, AR5K_SLOT_TIME); /* Set EIFS */ eifs_clock = AR5K_REG_SM(eifs_clock, AR5K_IFS1_EIFS); /* PIFS = Slot time + SIFS */ pifs = slot_time + sifs; pifs_clock = ath5k_hw_htoclock(ah, pifs); pifs_clock = AR5K_REG_SM(pifs_clock, AR5K_IFS1_PIFS); /* DIFS = SIFS + 2 * Slot time */ difs = sifs + 2 * slot_time; difs_clock = ath5k_hw_htoclock(ah, difs); /* Set SIFS/DIFS */ ath5k_hw_reg_write(ah, (difs_clock << AR5K_IFS0_DIFS_S) | sifs_clock, AR5K_IFS0); /* Set PIFS/EIFS and preserve AR5K_INIT_CARR_SENSE_EN */ ath5k_hw_reg_write(ah, pifs_clock | eifs_clock | (AR5K_INIT_CARR_SENSE_EN << AR5K_IFS1_CS_EN_S), AR5K_IFS1); return 0; } /* Set IFS slot time */ ath5k_hw_reg_write(ah, slot_time_clock, AR5K_DCU_GBL_IFS_SLOT); /* Set EIFS interval */ ath5k_hw_reg_write(ah, eifs_clock, AR5K_DCU_GBL_IFS_EIFS); /* Set SIFS interval in usecs */ AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC, AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC, sifs); /* Set SIFS interval in clock cycles */ ath5k_hw_reg_write(ah, sifs_clock, AR5K_DCU_GBL_IFS_SIFS); return 0; }