/* * Read from an indirect register */ u_int32_t uperf_sbus_read_reg(struct uperf_sbus_softc *sc, bus_size_t r) { u_int32_t v; int s; s = splhigh(); bus_space_write_1(sc->sc_bus_t, sc->sc_bus_h, USC_ADDR, r); bus_space_barrier(sc->sc_bus_t, sc->sc_bus_h, USC_ADDR, 1, BUS_SPACE_BARRIER_WRITE); /* Can't use multi reads because we have to gaurantee order */ v = bus_space_read_1(sc->sc_bus_t, sc->sc_bus_h, USC_DATA + 0); bus_space_barrier(sc->sc_bus_t, sc->sc_bus_h, USC_DATA + 0, 1, BUS_SPACE_BARRIER_READ); v <<= 8; v |= bus_space_read_1(sc->sc_bus_t, sc->sc_bus_h, USC_DATA + 1); bus_space_barrier(sc->sc_bus_t, sc->sc_bus_h, USC_DATA + 1, 1, BUS_SPACE_BARRIER_READ); v <<= 8; v |= bus_space_read_1(sc->sc_bus_t, sc->sc_bus_h, USC_DATA + 2); bus_space_barrier(sc->sc_bus_t, sc->sc_bus_h, USC_DATA + 2, 1, BUS_SPACE_BARRIER_READ); v <<= 8; v |= bus_space_read_1(sc->sc_bus_t, sc->sc_bus_h, USC_DATA + 3); bus_space_barrier(sc->sc_bus_t, sc->sc_bus_h, USC_DATA + 3, 1, BUS_SPACE_BARRIER_READ); splx(s); return (v); }
void le_lebuffer_wrcsr(struct am7990_softc *sc, u_int16_t port, u_int16_t val) { struct le_softc *lesc = (struct le_softc *)sc; bus_space_write_2(lesc->sc_bustag, lesc->sc_reg, LEREG1_RAP, port); bus_space_barrier(lesc->sc_bustag, lesc->sc_reg, LEREG1_RAP, 2, BUS_SPACE_BARRIER_WRITE); bus_space_write_2(lesc->sc_bustag, lesc->sc_reg, LEREG1_RDP, val); bus_space_barrier(lesc->sc_bustag, lesc->sc_reg, LEREG1_RDP, 2, BUS_SPACE_BARRIER_WRITE); #if defined(SUN4M) /* * We need to flush the Sbus->Mbus write buffers. This can most * easily be accomplished by reading back the register that we * just wrote (thanks to Chris Torek for this solution). */ if (CPU_ISSUN4M) { volatile u_int16_t discard; discard = bus_space_read_2(lesc->sc_bustag, lesc->sc_reg, LEREG1_RDP); } #endif }
int HAIKU_CHECK_DISABLE_INTERRUPTS(device_t dev) { struct le_pci_softc *lesc = (struct le_pci_softc *)device_get_softc(dev); HAIKU_INTR_REGISTER_STATE; uint16_t value; HAIKU_INTR_REGISTER_ENTER(); /* get current flags */ bus_space_write_2(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RAP, LE_CSR0); bus_space_barrier(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RAP, 2, BUS_SPACE_BARRIER_WRITE); value = bus_space_read_2(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RDP); /* is there a pending interrupt? */ if (value & LE_C0_INTR) { /* set the new flags, disable interrupts */ bus_space_write_2(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RAP, LE_CSR0); bus_space_barrier(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RAP, 2, BUS_SPACE_BARRIER_WRITE); bus_space_write_2(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RDP, value & ~LE_C0_INEA); lesc->sc_am79900.lsc.sc_lastisr |= value; } HAIKU_INTR_REGISTER_LEAVE(); return value & LE_C0_INTR; }
/* * Write to an indirect register */ void uperf_sbus_write_reg(struct uperf_sbus_softc *sc, bus_size_t r, u_int32_t v) { int s; s = splhigh(); bus_space_write_1(sc->sc_bus_t, sc->sc_bus_h, USC_ADDR, r); bus_space_barrier(sc->sc_bus_t, sc->sc_bus_h, USC_ADDR, 1, BUS_SPACE_BARRIER_WRITE); /* Can't use multi writes because we have to gaurantee order */ bus_space_write_1(sc->sc_bus_t, sc->sc_bus_h, USC_DATA + 0, (v >> 24) & 0xff); bus_space_barrier(sc->sc_bus_t, sc->sc_bus_h, USC_DATA + 0, 1, BUS_SPACE_BARRIER_WRITE); bus_space_write_1(sc->sc_bus_t, sc->sc_bus_h, USC_DATA + 1, (v >> 16) & 0xff); bus_space_barrier(sc->sc_bus_t, sc->sc_bus_h, USC_DATA + 1, 1, BUS_SPACE_BARRIER_WRITE); bus_space_write_1(sc->sc_bus_t, sc->sc_bus_h, USC_DATA + 2, (v >> 8) & 0xff); bus_space_barrier(sc->sc_bus_t, sc->sc_bus_h, USC_DATA + 2, 1, BUS_SPACE_BARRIER_WRITE); bus_space_write_1(sc->sc_bus_t, sc->sc_bus_h, USC_DATA + 3, (v >> 0) & 0xff); bus_space_barrier(sc->sc_bus_t, sc->sc_bus_h, USC_DATA + 3, 1, BUS_SPACE_BARRIER_WRITE); splx(s); }
/* * write (fill) 0 to SONIC data buffer. */ void snc_nec16_zerobuf(struct snc_softc *sc, u_int32_t offset, size_t size) { bus_space_tag_t memt = sc->sc_memt; bus_space_handle_t memh = sc->sc_memh; u_int16_t noffset, onoffset; size_t osize = size; noffset = snc_nec16_select_bank(sc, offset, 0); onoffset = noffset; /* XXX: should check if offset + size < 0x2000. */ if (size > 3) { if (noffset & 3) { size_t asize = 4 - (noffset & 3); bus_space_set_region_1(memt, memh, noffset, 0, asize); noffset += asize; size -= asize; } bus_space_set_region_4(memt, memh, noffset, 0, size >> 2); noffset += size & ~3; size -= size & ~3; } if (size) bus_space_set_region_1(memt, memh, noffset, 0, size); bus_space_barrier(memt, memh, onoffset, osize, BUS_SPACE_BARRIER_WRITE); }
/* * read from SONIC data buffer. */ void snc_nec16_copyfrombuf(struct snc_softc *sc, void *dst, u_int32_t offset, size_t size) { bus_space_tag_t memt = sc->sc_memt; bus_space_handle_t memh = sc->sc_memh; u_int16_t noffset; u_int8_t* bptr = dst; noffset = snc_nec16_select_bank(sc, offset, 0); /* XXX: should check if offset + size < 0x2000. */ bus_space_barrier(memt, memh, noffset, size, BUS_SPACE_BARRIER_READ); if (size > 3) { if (noffset & 3) { size_t asize = 4 - (noffset & 3); bus_space_read_region_1(memt, memh, noffset, bptr, asize); bptr += asize; noffset += asize; size -= asize; } bus_space_read_region_4(memt, memh, noffset, (u_int32_t *) bptr, size >> 2); bptr += size & ~3; noffset += size & ~3; size &= 3; } if (size) bus_space_read_region_1(memt, memh, noffset, bptr, size); }
void panel_repeat(void *v) { struct panel_softc *sc = (struct panel_softc *)v; uint8_t reg; reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 0); #if NAUDIO > 0 && NWSKBD > 0 /* * Volume button autorepeat. */ if (sys_config.system_subtype == IP22_INDY) panel_volume_adjust(sc, reg); #endif if (hpc_is_intr_pending(sc->sc_irq)) { /* * Keep acking everything to get the interrupt finally * unlatched. */ bus_space_write_1(sc->sc_iot, sc->sc_ioh, 0, IOC_PANEL_POWER_STATE | IOC_PANEL_POWER_IRQ | IOC_PANEL_VDOWN_IRQ | IOC_PANEL_VDOWN_HOLD | IOC_PANEL_VUP_IRQ | IOC_PANEL_VUP_HOLD); bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); timeout_add_msec(&sc->sc_repeat_tmo, PANEL_REPEAT_NEXT); } else { hpc_intr_enable(sc->sc_ih); } }
int pxa2x0_i2s_attach_sub(struct pxa2x0_i2s_softc *sc) { int rv; KASSERT(sc->sc_intr_lock != NULL); rv = bus_space_map(sc->sc_iot, PXA2X0_I2S_BASE, PXA2X0_I2S_SIZE, 0, &sc->sc_ioh); if (rv) { sc->sc_size = 0; return 1; } sc->sc_dr.ds_addr = PXA2X0_I2S_BASE + I2S_SADR; sc->sc_dr.ds_len = 4; sc->sc_sadiv = SADIV_3_058MHz; bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, sc->sc_size, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); pxa2x0_i2s_init(sc); return 0; }
int pxa2x0_i2c_attach_sub(struct pxa2x0_i2c_softc *sc) { int error; error = bus_space_map(sc->sc_iot, sc->sc_addr, sc->sc_size, 0, &sc->sc_ioh); if (error) { aprint_error_dev(sc->sc_dev, "unable to map register\n"); sc->sc_size = 0; return error; } bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, sc->sc_size, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); sc->sc_icr = ICR_GCD | ICR_SCLE | ICR_IUE; #if 0 if (ISSET(sc->sc_flags, PI2CF_ENABLE_INTR)) sc->sc_icr |= ICR_BEIE | ICR_DRFIE | ICR_ITEIE; #endif if (ISSET(sc->sc_flags, PI2CF_FAST_MODE)) sc->sc_icr |= ICR_FM; pxa2x0_i2c_init(sc); return 0; }
void qlw_write(struct qlw_softc *sc, bus_size_t offset, u_int16_t value) { bus_space_write_2(sc->sc_iot, sc->sc_ioh, offset, value); bus_space_barrier(sc->sc_iot, sc->sc_ioh, offset, 2, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); }
void bcm2835_mbox_read(bus_space_tag_t iot, bus_space_handle_t ioh, uint8_t chan, uint32_t *data) { uint32_t mbox; KASSERT((chan & 0xf) == chan); for (;;) { uint8_t rchan; uint32_t rdata; bus_space_barrier(iot, ioh, 0, BCM2835_MBOX_SIZE, BUS_SPACE_BARRIER_READ); if ((bus_space_read_4(iot, ioh, BCM2835_MBOX0_STATUS) & BCM2835_MBOX_STATUS_EMPTY) != 0) continue; mbox = bus_space_read_4(iot, ioh, BCM2835_MBOX0_READ); rchan = BCM2835_MBOX_CHAN(mbox); rdata = BCM2835_MBOX_DATA(mbox); if (rchan == chan) { *data = rdata; return; } } }
void che_write(struct cheg_softc *sc, bus_size_t r, u_int32_t v) { bus_space_write_4(sc->sc_memt, sc->sc_memh, r, v); bus_space_barrier(sc->sc_memt, sc->sc_memh, r, 4, BUS_SPACE_BARRIER_WRITE); }
u_int32_t che_read(struct cheg_softc *sc, bus_size_t r) { bus_space_barrier(sc->sc_memt, sc->sc_memh, r, 4, BUS_SPACE_BARRIER_READ); return (bus_space_read_4(sc->sc_memt, sc->sc_memh, r)); }
int armada38x_open_bootrom_win(void) { bus_space_handle_t vaddr_iowind; uint32_t val; int rv; rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_BRIDGE_BASE, MV_CPU_SUBSYS_REGS_LEN, 0, &vaddr_iowind); if (rv != 0) return (rv); val = (MV_BOOTROM_WIN_SIZE & IO_WIN_SIZE_MASK) << IO_WIN_SIZE_SHIFT; val |= (MBUS_BOOTROM_ATTR & IO_WIN_ATTR_MASK) << IO_WIN_ATTR_SHIFT; val |= (MBUS_BOOTROM_TGT_ID & IO_WIN_TGT_MASK) << IO_WIN_TGT_SHIFT; /* Enable window and Sync Barrier */ val |= (0x1 & IO_WIN_SYNC_MASK) << IO_WIN_SYNC_SHIFT; val |= (0x1 & IO_WIN_ENA_MASK) << IO_WIN_ENA_SHIFT; /* Configure IO Window Control Register */ bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_CTRL_OFFSET, val); /* Configure IO Window Base Register */ bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_BASE_OFFSET, MV_BOOTROM_MEM_ADDR); bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_CPU_SUBSYS_REGS_LEN, BUS_SPACE_BARRIER_WRITE); bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN); return (rv); }
void athn_pci_write_barrier(struct athn_softc *sc) { struct athn_pci_softc *psc = (struct athn_pci_softc *)sc; bus_space_barrier(psc->sc_st, psc->sc_sh, 0, psc->sc_mapsize, BUS_SPACE_BARRIER_WRITE); }
Static void athn_pci_write_barrier(struct athn_softc *sc) { struct athn_pci_softc *psc = (struct athn_pci_softc *)sc; bus_space_barrier(psc->psc_iot, psc->psc_ioh, 0, psc->psc_mapsz, BUS_SPACE_BARRIER_WRITE); }
/* * Low-level inline support functions */ static __inline void reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value) { bus_space_write_4(sc->regs_t, sc->regs_h, reg, value); bus_space_barrier(sc->regs_t, sc->regs_h, reg, 4, BUS_SPACE_BARRIER_WRITE); }
static inline void twe_outl(struct twe_softc *sc, int off, u_int32_t val) { bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, BUS_SPACE_BARRIER_WRITE); }
void athn_cardbus_write_barrier(struct athn_softc *sc) { struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc; bus_space_barrier(csc->sc_st, csc->sc_sh, 0, csc->sc_mapsize, BUS_SPACE_BARRIER_WRITE); }
static inline u_int32_t twe_inl(struct twe_softc *sc, int off) { bus_space_barrier(sc->sc_iot, sc->sc_ioh, off, 4, BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, off)); }
u_int8_t nviic_read(struct nviic_controller *nc, bus_size_t r) { struct nviic_softc *sc = nc->nc_sc; bus_space_barrier(sc->sc_iot, nc->nc_ioh, r, 1, BUS_SPACE_BARRIER_READ); return (bus_space_read_1(sc->sc_iot, nc->nc_ioh, r)); }
static inline uint8_t bt3c_read_control(struct bt3c_softc *sc) { bus_space_barrier(sc->sc_pcioh.iot, sc->sc_pcioh.ioh, 0, BT3C_IOR_LEN, BUS_SPACE_BARRIER_READ); return bus_space_read_1(sc->sc_pcioh.iot, sc->sc_pcioh.ioh, BT3C_IOR_CNTL); }
static inline void bt3c_write_control(struct bt3c_softc *sc, uint8_t data) { bus_space_barrier(sc->sc_pcioh.iot, sc->sc_pcioh.ioh, 0, BT3C_IOR_LEN, BUS_SPACE_BARRIER_WRITE); bus_space_write_1(sc->sc_pcioh.iot, sc->sc_pcioh.ioh, BT3C_IOR_CNTL, data); }
u_int16_t qlw_read(struct qlw_softc *sc, bus_size_t offset) { u_int16_t v; v = bus_space_read_2(sc->sc_iot, sc->sc_ioh, offset); bus_space_barrier(sc->sc_iot, sc->sc_ioh, offset, 2, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); return (v); }
void nviic_write(struct nviic_controller *nc, bus_size_t r, u_int8_t v) { struct nviic_softc *sc = nc->nc_sc; bus_space_write_1(sc->sc_iot, nc->nc_ioh, r, v); bus_space_barrier(sc->sc_iot, nc->nc_ioh, r, 1, BUS_SPACE_BARRIER_WRITE); }
static void le_pci_wrcsr(struct lance_softc *sc, uint16_t port, uint16_t val) { struct le_pci_softc *lesc = (struct le_pci_softc *)sc; bus_space_write_2(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RAP, port); bus_space_barrier(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RAP, 2, BUS_SPACE_BARRIER_WRITE); bus_space_write_2(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RDP, val); }
static uint16_t le_isa_rdcsr(struct lance_softc *sc, uint16_t port) { struct le_isa_softc *lesc = (struct le_isa_softc *)sc; bus_space_write_2(lesc->sc_regt, lesc->sc_regh, lesc->sc_rap, port); bus_space_barrier(lesc->sc_regt, lesc->sc_regh, lesc->sc_rap, 2, BUS_SPACE_BARRIER_WRITE); return (bus_space_read_2(lesc->sc_regt, lesc->sc_regh, lesc->sc_rdp)); }
static void le_isa_wrcsr(struct lance_softc *sc, uint16_t port, uint16_t val) { struct le_isa_softc *lesc = (struct le_isa_softc *)sc; bus_space_write_2(lesc->sc_regt, lesc->sc_regh, lesc->sc_rap, port); bus_space_barrier(lesc->sc_regt, lesc->sc_regh, lesc->sc_rap, 2, BUS_SPACE_BARRIER_WRITE); bus_space_write_2(lesc->sc_regt, lesc->sc_regh, lesc->sc_rdp, val); }
static uint16_t le_pci_rdcsr(struct lance_softc *sc, uint16_t port) { struct le_pci_softc *lesc = (struct le_pci_softc *)sc; bus_space_write_2(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RAP, port); bus_space_barrier(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RAP, 2, BUS_SPACE_BARRIER_WRITE); return (bus_space_read_2(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RDP)); }
u_int16_t le_lebuffer_rdcsr(struct am7990_softc *sc, u_int16_t port) { struct le_softc *lesc = (struct le_softc *)sc; bus_space_write_2(lesc->sc_bustag, lesc->sc_reg, LEREG1_RAP, port); bus_space_barrier(lesc->sc_bustag, lesc->sc_reg, LEREG1_RAP, 2, BUS_SPACE_BARRIER_WRITE); return (bus_space_read_2(lesc->sc_bustag, lesc->sc_reg, LEREG1_RDP)); }