static int gpu_set_clock(struct exynos_context *platform, int clk) { long g3d_rate_prev = -1; unsigned long g3d_rate = clk * MHZ; int ret = 0; int level = 0; if (aclk_g3d == 0) return -1; #ifdef CONFIG_MALI_RT_PM if (platform->exynos_pm_domain) mutex_lock(&platform->exynos_pm_domain->access_lock); #endif /* CONFIG_MALI_RT_PM */ if (!gpu_is_power_on()) { ret = -1; GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "%s: can't set clock in the power-off state!\n", __func__); goto err; } g3d_rate_prev = clk_get_rate(aclk_g3d); /* if changed the VPLL rate, set rate for VPLL and wait for lock time */ if (g3d_rate != g3d_rate_prev) { ret = clk_set_parent(mout_g3d, fin_pll); if (ret < 0) { GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to clk_set_parent [fin_pll]\n", __func__); goto err; } /*change g3d pll*/ ret = clk_set_rate(fout_g3d_pll, g3d_rate); if (ret < 0) { GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to clk_set_rate [fout_g3d_pll]\n", __func__); goto err; } level = gpu_dvfs_get_level(g3d_rate/MHZ); if (level < 0) { GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to gpu_dvfs_get_level \n", __func__); goto err; } ret = clk_set_rate(sclk_hpm_g3d, (clk_get_rate(aclk_g3d)/hpm_freq_table[level])); if(ret < 0) GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to clk_set_rate [sclk_hpm_g3d]\n", __func__); ret = clk_set_parent(mout_g3d, fout_g3d_pll); if (ret < 0) { GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to clk_set_parent [fout_g3d_pll]\n", __func__); goto err; } g3d_rate_prev = g3d_rate; } platform->cur_clock = gpu_get_cur_clock(platform); if (platform->cur_clock != clk_get_rate(fout_g3d_pll)/MHZ) GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "clock value is wrong (aclk_g3d: %d, fout_g3d_pll: %d)\n", platform->cur_clock, (int) clk_get_rate(fout_g3d_pll)/MHZ); GPU_LOG(DVFS_DEBUG, LSI_CLOCK_VALUE, g3d_rate/MHZ, platform->cur_clock, "clock set: %ld, clock get: %d\n", g3d_rate/MHZ, platform->cur_clock); err: #ifdef CONFIG_MALI_RT_PM if (platform->exynos_pm_domain) mutex_unlock(&platform->exynos_pm_domain->access_lock); #endif /* CONFIG_MALI_RT_PM */ return ret; }
static int serial_pxa_startup(struct uart_port *port) { struct uart_pxa_port *up = (struct uart_pxa_port *)port; unsigned long flags; int retval; if (port->line == 3) /* HWUART */ up->mcr |= UART_MCR_AFE; else up->mcr = 0; up->port.uartclk = clk_get_rate(up->clk); /* * Allocate the IRQ */ retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up); if (retval) return retval; /* * Clear the FIFO buffers and disable them. * (they will be reenabled in set_termios()) */ serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); serial_out(up, UART_FCR, 0); /* * Clear the interrupt registers. */ (void) serial_in(up, UART_LSR); (void) serial_in(up, UART_RX); (void) serial_in(up, UART_IIR); (void) serial_in(up, UART_MSR); /* * Now, initialize the UART */ serial_out(up, UART_LCR, UART_LCR_WLEN8); spin_lock_irqsave(&up->port.lock, flags); up->port.mctrl |= TIOCM_OUT2; serial_pxa_set_mctrl(&up->port, up->port.mctrl); spin_unlock_irqrestore(&up->port.lock, flags); /* * Finally, enable interrupts. Note: Modem status interrupts * are set via set_termios(), which will be occurring imminently * anyway, so we don't enable them here. */ up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE; serial_out(up, UART_IER, up->ier); /* * And clear the interrupt registers again for luck. */ (void) serial_in(up, UART_LSR); (void) serial_in(up, UART_RX); (void) serial_in(up, UART_IIR); (void) serial_in(up, UART_MSR); return 0; }
/* * To avoid duplicating clock code, allow machine driver to * get the clockrate from here. */ u32 s3c24xx_i2s_get_clockrate(void) { return clk_get_rate(s3c24xx_i2s.iis_clk); }
int __init exynos_cpufreq_cluster1_init(struct exynos_dvfs_info *info) { unsigned long rate; struct device_node *pmic_node; int ret, tmp; set_volt_table_CA57(); mout_atlas_pll = clk_get(NULL, "mout_atlas_pll"); if (IS_ERR(mout_atlas_pll)) { pr_err("failed get mout_atlas_pll clk\n"); goto err_mout_atlas_pll; } mout_atlas = clk_get(NULL, "mout_atlas"); if (IS_ERR(mout_atlas)) { pr_err("failed get mout_atlas clk\n"); goto err_mout_atlas; } if (clk_set_parent(mout_atlas, mout_atlas_pll)) { pr_err("Unable to set parent %s of clock %s.\n", mout_atlas_pll->name, mout_atlas->name); goto err_clk_set_parent_atlas; } mout_bus0_pll_atlas = clk_get(NULL, "mout_bus0_pll_atlas"); if (IS_ERR(mout_bus0_pll_atlas)) { pr_err("failed get mout_bus0_pll_atlas clk\n"); goto err_mout_bus0_pll_atlas; } if (clk_prepare_enable(mout_atlas_pll) || clk_prepare_enable(mout_atlas)) { pr_err("Unable to enable Atlas clocks \n"); goto err_clk_prepare_enable; } rate = clk_get_rate(mout_bus0_pll_atlas) / 1000; info->mpll_freq_khz = rate; info->pll_safe_idx = L17; info->max_support_idx = max_support_idx_CA57; info->min_support_idx = min_support_idx_CA57; /* booting frequency is 1.7GHz */ info->boot_cpu_min_qos = exynos7420_freq_table_CA57[L8].frequency; info->boot_cpu_max_qos = exynos7420_freq_table_CA57[L8].frequency; #ifdef CONFIG_SEC_PM /* booting max frequency is 1.5GHz when JIG cable is attached */ info->jig_boot_cpu_max_qos = exynos7420_freq_table_CA57[L10].frequency; /* This low freq used for FOTA(dex2oat) update */ info->low_boot_cpu_max_qos = exynos7420_freq_table_CA57[L12].frequency; #endif #if defined(CONFIG_PMU_COREMEM_RATIO) info->region_bus_table = exynos7420_region_bus_table_CA57; #else info->bus_table = exynos7420_bus_table_CA57; #endif info->cpu_clk = mout_atlas_pll; /* reboot limit frequency is 800MHz */ info->reboot_limit_freq = exynos7420_freq_table_CA57[L17].frequency; info->volt_table = exynos7420_volt_table_CA57; info->abb_table = NULL; //exynos7420_abb_table_CA57; info->freq_table = exynos7420_freq_table_CA57; info->set_freq = exynos7420_set_frequency_CA57; info->need_apll_change = exynos7420_pms_change_CA57; info->is_alive = exynos7420_is_alive_CA57; info->set_ema = exynos7420_set_ema_CA57; pmic_node = of_find_compatible_node(NULL, NULL, "samsung,s2mps15-pmic"); if (!pmic_node) { pr_err("%s: faile to get pmic dt_node\n", __func__); } else { ret = of_property_read_u32(pmic_node, "smpl_warn_en", &en_smpl_warn); if (ret) pr_err("%s: faile to get Property of smpl_warn_en\n", __func__); } if (en_smpl_warn) { info->check_smpl = exynos7420_check_smpl_CA57; /* ATLAS_RATIO_SMPL */ tmp = __raw_readl(EXYNOS7420_ATLAS_SMPL_CTRL0); tmp &= 0x7F; tmp |= 0x44; __raw_writel(tmp, EXYNOS7420_ATLAS_SMPL_CTRL0); pr_info("%s SMPL_WARN ENABLE (DIV:%d) ", __func__, tmp&0x3F); exynos_cpufreq_smpl_warn_register_notifier(&exynos7420_cpufreq_smpl_warn_notifier); } return 0; err_clk_prepare_enable: err_mout_bus0_pll_atlas: err_clk_set_parent_atlas: clk_put(mout_atlas); err_mout_atlas: clk_put(mout_atlas_pll); err_mout_atlas_pll: pr_debug("%s: failed initialization\n", __func__); return -EINVAL; }
static unsigned long blizzard_get_clock_rate(void) { return clk_get_rate(blizzard.sys_ck); }
static int rk29_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; unsigned int pll_out = 0, dai_fmt = rtd->dai_link->dai_fmt; int div_bclk,div_mclk; int ret; struct clk *general_pll; DBG("Enter::%s----%d\n", __FUNCTION__, __LINE__); /* set codec DAI configuration */ ret = snd_soc_dai_set_fmt(codec_dai, dai_fmt); if (ret < 0) { printk("%s():failed to set the format for codec side\n", __FUNCTION__); return ret; } /* set cpu DAI configuration */ ret = snd_soc_dai_set_fmt(cpu_dai, dai_fmt); if (ret < 0) { printk("%s():failed to set the format for cpu side\n", __FUNCTION__); return ret; } switch(params_rate(params)) { case 8000: case 16000: case 24000: case 32000: case 48000: pll_out = 12288000; break; case 11025: case 22050: case 44100: pll_out = 11289600; break; default: DBG("Enter:%s, %d, Error rate=%d\n",__FUNCTION__,__LINE__,params_rate(params)); return -EINVAL; break; } DBG("Enter:%s, %d, rate=%d\n",__FUNCTION__,__LINE__,params_rate(params)); //pll_out = 12000000; //snd_soc_dai_set_pll(codec_dai, NULL, 12000000, pll_out); snd_soc_dai_set_clkdiv(codec_dai, WM8900_LRCLK_MODE, 0x000); if ((dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM) { snd_soc_dai_set_clkdiv(codec_dai, WM8900_BCLK_DIV, WM8900_BCLK_DIV_4); snd_soc_dai_set_clkdiv(codec_dai, WM8900_DAC_LRCLK,(pll_out/4)/params_rate(params)); snd_soc_dai_set_clkdiv(codec_dai, WM8900_ADC_LRCLK,(pll_out/4)/params_rate(params)); } else { general_pll=clk_get(NULL, "general_pll"); if(clk_get_rate(general_pll)>260000000) { div_bclk=(pll_out/4)/params_rate(params)-1; div_mclk=3; } else if(clk_get_rate(general_pll)>130000000) { div_bclk=(pll_out/2)/params_rate(params)-1; div_mclk=1; } else { pll_out=pll_out/4; div_bclk=(pll_out)/params_rate(params)-1; div_mclk=0; } DBG("func is%s,gpll=%ld,pll_out=%u,div_mclk=%d\n", __FUNCTION__,clk_get_rate(general_pll),pll_out,div_mclk); snd_soc_dai_set_sysclk(cpu_dai, 0, pll_out, 0); snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_BCLK,div_bclk); snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_MCLK, div_mclk); } DBG("Enter:%s, %d, LRCK=%d\n",__FUNCTION__,__LINE__,(pll_out/4)/params_rate(params)); return 0; }
void __init s3c2443_init_clocks(int xtal) { struct clk *clkp; unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); int ret; int ptr; /* s3c2443 parents h and p clocks from prediv */ clk_h.parent = &clk_prediv; clk_p.parent = &clk_prediv; s3c24xx_register_baseclocks(xtal); s3c2443_setup_clocks(); s3c2443_clk_initparents(); for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { clkp = clks[ptr]; ret = s3c24xx_register_clock(clkp); if (ret < 0) { printk(KERN_ERR "Failed to register clock %s (%d)\n", clkp->name, ret); } } clk_epll.rate = s3c2443_get_epll(epllcon, xtal); clk_epll.parent = &clk_epllref; clk_usb_bus.parent = &clk_usb_bus_host; /* ensure usb bus clock is within correct rate of 48MHz */ if (clk_get_rate(&clk_usb_bus_host) != (48 * 1000 * 1000)) { printk(KERN_INFO "Warning: USB host bus not at 48MHz\n"); clk_set_rate(&clk_usb_bus_host, 48*1000*1000); } printk("S3C2443: epll %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n", (epllcon & S3C2443_PLLCON_OFF) ? "off":"on", print_mhz(clk_get_rate(&clk_epll)), print_mhz(clk_get_rate(&clk_usb_bus))); /* register clocks from clock array */ s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); /* We must be careful disabling the clocks we are not intending to * be using at boot time, as subsystems such as the LCD which do * their own DMA requests to the bus can cause the system to lockup * if they where in the middle of requesting bus access. * * Disabling the LCD clock if the LCD is active is very dangerous, * and therefore the bootloader should be careful to not enable * the LCD clock if it is not needed. */ /* install (and disable) the clocks we do not need immediately */ clkp = init_clocks_disable; for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { ret = s3c24xx_register_clock(clkp); if (ret < 0) { printk(KERN_ERR "Failed to register clock %s (%d)\n", clkp->name, ret); } (clkp->enable)(clkp, 0); } s3c_pwmclk_init(); }
static unsigned long spdif_clk_get_rate(struct clk *clk) { return clk_get_rate(clk->parent) / 4; }
static inline unsigned long fec_clk_get_rate(struct fec_priv *fec) { return clk_get_rate(fec->clk); }
static int spi_imx_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; const struct of_device_id *of_id = of_match_device(spi_imx_dt_ids, &pdev->dev); struct spi_imx_master *mxc_platform_info = dev_get_platdata(&pdev->dev); struct spi_master *master; struct spi_imx_data *spi_imx; struct resource *res; int i, ret, num_cs; if (!np && !mxc_platform_info) { dev_err(&pdev->dev, "can't get the platform data\n"); return -EINVAL; } ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs); if (ret < 0) { if (mxc_platform_info) num_cs = mxc_platform_info->num_chipselect; else return ret; } master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data) + sizeof(int) * num_cs); if (!master) return -ENOMEM; platform_set_drvdata(pdev, master); master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); master->bus_num = pdev->id; master->num_chipselect = num_cs; spi_imx = spi_master_get_devdata(master); spi_imx->bitbang.master = master; for (i = 0; i < master->num_chipselect; i++) { int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); if (!gpio_is_valid(cs_gpio) && mxc_platform_info) cs_gpio = mxc_platform_info->chipselect[i]; spi_imx->chipselect[i] = cs_gpio; if (!gpio_is_valid(cs_gpio)) continue; ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i], DRIVER_NAME); if (ret) { dev_err(&pdev->dev, "can't get cs gpios\n"); goto out_master_put; } } spi_imx->bitbang.chipselect = spi_imx_chipselect; spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; spi_imx->bitbang.txrx_bufs = spi_imx_transfer; spi_imx->bitbang.master->setup = spi_imx_setup; spi_imx->bitbang.master->cleanup = spi_imx_cleanup; spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; init_completion(&spi_imx->xfer_done); spi_imx->devtype_data = of_id ? of_id->data : (struct spi_imx_devtype_data *) pdev->id_entry->driver_data; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); spi_imx->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(spi_imx->base)) { ret = PTR_ERR(spi_imx->base); goto out_master_put; } spi_imx->irq = platform_get_irq(pdev, 0); if (spi_imx->irq < 0) { ret = -EINVAL; goto out_master_put; } ret = devm_request_irq(&pdev->dev, spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx); if (ret) { dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret); goto out_master_put; } spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); if (IS_ERR(spi_imx->clk_ipg)) { ret = PTR_ERR(spi_imx->clk_ipg); goto out_master_put; } spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); if (IS_ERR(spi_imx->clk_per)) { ret = PTR_ERR(spi_imx->clk_per); goto out_master_put; } ret = clk_prepare_enable(spi_imx->clk_per); if (ret) goto out_master_put; ret = clk_prepare_enable(spi_imx->clk_ipg); if (ret) goto out_put_per; spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); spi_imx->devtype_data->reset(spi_imx); spi_imx->devtype_data->intctrl(spi_imx, 0); master->dev.of_node = pdev->dev.of_node; ret = spi_bitbang_start(&spi_imx->bitbang); if (ret) { dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); goto out_clk_put; } dev_info(&pdev->dev, "probed\n"); clk_disable(spi_imx->clk_ipg); clk_disable(spi_imx->clk_per); return ret; out_clk_put: clk_disable_unprepare(spi_imx->clk_ipg); out_put_per: clk_disable_unprepare(spi_imx->clk_per); out_master_put: spi_master_put(master); return ret; }
/* * General clocks * * clk_get_rate */ static unsigned long lradc_clk_get_rate(struct clk *clk) { return clk_get_rate(clk->parent) / 16; }
static int omap_i2c_init(struct omap_i2c_dev *dev) { u16 psc = 0, scll = 0, sclh = 0, buf = 0; u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0; unsigned long fclk_rate = 12000000; unsigned long timeout; unsigned long internal_clk = 0; struct clk *fclk; if (dev->rev >= OMAP_I2C_OMAP1_REV_2) { /* Disable I2C controller before soft reset */ omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & ~(OMAP_I2C_CON_EN)); omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); /* For some reason we need to set the EN bit before the * reset done bit gets set. */ timeout = jiffies + OMAP_I2C_TIMEOUT; omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & SYSS_RESETDONE_MASK)) { if (time_after(jiffies, timeout)) { dev_warn(dev->dev, "timeout waiting " "for controller reset\n"); return -ETIMEDOUT; } msleep(1); } /* SYSC register is cleared by the reset; rewrite it */ if (dev->rev == OMAP_I2C_REV_ON_2430) { omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_AUTOIDLE_MASK); } else if (dev->rev >= OMAP_I2C_REV_ON_3430) { dev->syscstate = SYSC_AUTOIDLE_MASK; dev->syscstate |= SYSC_ENAWAKEUP_MASK; dev->syscstate |= (SYSC_IDLEMODE_SMART << __ffs(SYSC_SIDLEMODE_MASK)); dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK << __ffs(SYSC_CLOCKACTIVITY_MASK)); omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate); /* * Enabling all wakup sources to stop I2C freezing on * WFI instruction. * REVISIT: Some wkup sources might not be needed. */ dev->westate = OMAP_I2C_WE_ALL; omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate); } } omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) { /* * The I2C functional clock is the armxor_ck, so there's * no need to get "armxor_ck" separately. Now, if OMAP2420 * always returns 12MHz for the functional clock, we can * do this bit unconditionally. */ fclk = clk_get(dev->dev, "fck"); fclk_rate = clk_get_rate(fclk); clk_put(fclk); /* TRM for 5912 says the I2C clock must be prescaled to be * between 7 - 12 MHz. The XOR input clock is typically * 12, 13 or 19.2 MHz. So we should have code that produces: * * XOR MHz Divider Prescaler * 12 1 0 * 13 2 1 * 19.2 2 1 */ if (fclk_rate > 12000000) psc = fclk_rate / 12000000; } if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) { /* * HSI2C controller internal clk rate should be 19.2 Mhz for * HS and for all modes on 2430. On 34xx we can use lower rate * to get longer filter period for better noise suppression. * The filter is iclk (fclk for HS) period. */ if (dev->speed > 400 || dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK) internal_clk = 19200; else if (dev->speed > 100) internal_clk = 9600; else internal_clk = 4000; fclk = clk_get(dev->dev, "fck"); fclk_rate = clk_get_rate(fclk) / 1000; clk_put(fclk); /* Compute prescaler divisor */ psc = fclk_rate / internal_clk; psc = psc - 1; /* If configured for High Speed */ if (dev->speed > 400) { unsigned long scl; /* For first phase of HS mode */ scl = internal_clk / 400; fsscll = scl - (scl / 3) - 7; fssclh = (scl / 3) - 5; /* For second phase of HS mode */ scl = fclk_rate / dev->speed; hsscll = scl - (scl / 3) - 7; hssclh = (scl / 3) - 5; } else if (dev->speed > 100) { unsigned long scl; /* Fast mode */ scl = internal_clk / dev->speed; fsscll = scl - (scl / 3) - 7; fssclh = (scl / 3) - 5; } else { /* Standard mode */ fsscll = internal_clk / (dev->speed * 2) - 7; fssclh = internal_clk / (dev->speed * 2) - 5; } scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; } else { /* Program desired operating rate */ fclk_rate /= (psc + 1) * 1000; if (psc > 2) psc = 2; scll = fclk_rate / (dev->speed * 2) - 7 + psc; sclh = fclk_rate / (dev->speed * 2) - 7 + psc; } /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc); /* SCL low and high time values */ omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll); omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh); if (dev->fifo_size) { /* Note: setup required fifo size - 1. RTRSH and XTRSH */ buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR | (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR; omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf); } /* Take the I2C module out of reset: */ omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); dev->errata = 0; if (dev->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207) dev->errata |= I2C_OMAP_ERRATA_I207; /* Enable interrupts */ dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | OMAP_I2C_IE_AL) | ((dev->fifo_size) ? (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) { dev->pscstate = psc; dev->scllstate = scll; dev->sclhstate = sclh; dev->bufstate = buf; } return 0; }
static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); return clk_get_rate(pltfm_host->clk) / 256 / 16; }
/***************************************************************************** * UART ****************************************************************************/ static unsigned long __init uart_get_clk_rate(struct clk *clk) { clk_prepare_enable(clk); return clk_get_rate(clk); }
static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, const char *fck_source, const char *property, const char **timer_name, int posted) { char name[10]; /* 10 = sizeof("gptXX_Xck0") */ const char *oh_name = NULL; struct device_node *np; struct omap_hwmod *oh; struct resource irq, mem; struct clk *src; int r = 0; if (of_have_populated_dt()) { np = omap_get_timer_dt(omap_timer_match, property); if (!np) return -ENODEV; of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); if (!oh_name) return -ENODEV; timer->irq = irq_of_parse_and_map(np, 0); if (!timer->irq) return -ENXIO; timer->io_base = of_iomap(np, 0); of_node_put(np); } else { if (omap_dm_timer_reserve_systimer(timer->id)) return -ENODEV; sprintf(name, "timer%d", timer->id); oh_name = name; } oh = omap_hwmod_lookup(oh_name); if (!oh) return -ENODEV; *timer_name = oh->name; if (!of_have_populated_dt()) { r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq); if (r) return -ENXIO; timer->irq = irq.start; r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem); if (r) return -ENXIO; /* Static mapping, never released */ timer->io_base = ioremap(mem.start, mem.end - mem.start); } if (!timer->io_base) return -ENXIO; /* After the dmtimer is using hwmod these clocks won't be needed */ timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); if (IS_ERR(timer->fclk)) return PTR_ERR(timer->fclk); src = clk_get(NULL, fck_source); if (IS_ERR(src)) return PTR_ERR(src); if (clk_get_parent(timer->fclk) != src) { r = clk_set_parent(timer->fclk, src); if (r < 0) { pr_warn("%s: %s cannot set source\n", __func__, oh->name); clk_put(src); return r; } } clk_put(src); omap_hwmod_setup_one(oh_name); omap_hwmod_enable(oh); __omap_dm_timer_init_regs(timer); if (posted) __omap_dm_timer_enable_posted(timer); /* Check that the intended posted configuration matches the actual */ if (posted != timer->posted) return -EINVAL; timer->rate = clk_get_rate(timer->fclk); timer->reserved = 1; return r; }
static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData) { #if defined(PVR_OMAP4_TIMING_PRCM) struct clk *psCLK; IMG_INT res; struct clk *sys_ck; IMG_INT rate; #endif PVRSRV_ERROR eError; IMG_CPU_PHYADDR sTimerRegPhysBase; IMG_HANDLE hTimerEnable; IMG_UINT32 *pui32TimerEnable; PVR_ASSERT(psSysSpecData->sTimerRegPhysBase.uiAddr == 0); #if defined(PVR_OMAP4_TIMING_PRCM) psCLK = clk_get(NULL, "gpt11_fck"); if (IS_ERR(psCLK)) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 functional clock")); goto ExitError; } psSysSpecData->psGPT11_FCK = psCLK; psCLK = clk_get(NULL, "gpt11_ick"); if (IS_ERR(psCLK)) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 interface clock")); goto ExitError; } psSysSpecData->psGPT11_ICK = psCLK; sys_ck = clk_get(NULL, "sys_clkin_ck"); if (IS_ERR(sys_ck)) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get System clock")); goto ExitError; } if(clk_get_parent(psSysSpecData->psGPT11_FCK) != sys_ck) { PVR_TRACE(("Setting GPTIMER11 parent to System Clock")); res = clk_set_parent(psSysSpecData->psGPT11_FCK, sys_ck); if (res < 0) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't set GPTIMER11 parent clock (%d)", res)); goto ExitError; } } rate = clk_get_rate(psSysSpecData->psGPT11_FCK); PVR_TRACE(("GPTIMER11 clock is %dMHz", HZ_TO_MHZ(rate))); res = clk_enable(psSysSpecData->psGPT11_FCK); if (res < 0) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 functional clock (%d)", res)); goto ExitError; } res = clk_enable(psSysSpecData->psGPT11_ICK); if (res < 0) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 interface clock (%d)", res)); goto ExitDisableGPT11FCK; } #endif sTimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_TSICR_SYS_PHYS_BASE; pui32TimerEnable = OSMapPhysToLin(sTimerRegPhysBase, 4, PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED, &hTimerEnable); if (pui32TimerEnable == IMG_NULL) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed")); goto ExitDisableGPT11ICK; } if(!(*pui32TimerEnable & 4)) { PVR_TRACE(("Setting GPTIMER11 mode to posted (currently is non-posted)")); *pui32TimerEnable |= 4; } OSUnMapPhysToLin(pui32TimerEnable, 4, PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED, hTimerEnable); sTimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_ENABLE_SYS_PHYS_BASE; pui32TimerEnable = OSMapPhysToLin(sTimerRegPhysBase, 4, PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED, &hTimerEnable); if (pui32TimerEnable == IMG_NULL) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed")); goto ExitDisableGPT11ICK; } *pui32TimerEnable = 3; OSUnMapPhysToLin(pui32TimerEnable, 4, PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED, hTimerEnable); psSysSpecData->sTimerRegPhysBase = sTimerRegPhysBase; eError = PVRSRV_OK; goto Exit; ExitDisableGPT11ICK: #if defined(PVR_OMAP4_TIMING_PRCM) clk_disable(psSysSpecData->psGPT11_ICK); ExitDisableGPT11FCK: clk_disable(psSysSpecData->psGPT11_FCK); ExitError: #endif eError = PVRSRV_ERROR_CLOCK_REQUEST_FAILED; Exit: return eError; }
/* * The realtime counter also called master counter, is a free-running * counter, which is related to real time. It produces the count used * by the CPU local timer peripherals in the MPU cluster. The timer counts * at a rate of 6.144 MHz. Because the device operates on different clocks * in different power modes, the master counter shifts operation between * clocks, adjusting the increment per clock in hardware accordingly to * maintain a constant count rate. */ static void __init realtime_counter_init(void) { void __iomem *base; static struct clk *sys_clk; unsigned long rate; unsigned int reg, num, den; base = ioremap(REALTIME_COUNTER_BASE, SZ_32); if (!base) { pr_err("%s: ioremap failed\n", __func__); return; } sys_clk = clk_get(NULL, "sys_clkin"); if (IS_ERR(sys_clk)) { pr_err("%s: failed to get system clock handle\n", __func__); iounmap(base); return; } rate = clk_get_rate(sys_clk); /* Numerator/denumerator values refer TRM Realtime Counter section */ switch (rate) { case 12000000: num = 64; den = 125; break; case 13000000: num = 768; den = 1625; break; case 19200000: num = 8; den = 25; break; case 20000000: num = 192; den = 625; break; case 26000000: num = 384; den = 1625; break; case 27000000: num = 256; den = 1125; break; case 38400000: default: /* Program it for 38.4 MHz */ num = 4; den = 25; break; } /* Program numerator and denumerator registers */ reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & NUMERATOR_DENUMERATOR_MASK; reg |= num; __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); reg = __raw_readl(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & NUMERATOR_DENUMERATOR_MASK; reg |= den; __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); arch_timer_freq = (rate / den) * num; set_cntfreq(); iounmap(base); }
static int tegra_camera_clk_set_rate(struct tegra_camera_dev *dev) { struct clk *clk, *clk_parent; struct tegra_camera_clk_info *info = &dev->info; unsigned long parent_rate, parent_div_rate, parent_div_rate_pre; if (!info) { dev_err(dev->dev, "%s: no clock info %d\n", __func__, info->id); return -EINVAL; } if (info->id != TEGRA_CAMERA_MODULE_VI && info->id != TEGRA_CAMERA_MODULE_EMC) { dev_err(dev->dev, "%s: set rate only aplies to vi module %d\n", __func__, info->id); return -EINVAL; } switch (info->clk_id) { case TEGRA_CAMERA_VI_CLK: clk = dev->vi_clk; break; case TEGRA_CAMERA_VI_SENSOR_CLK: clk = dev->vi_sensor_clk; break; case TEGRA_CAMERA_EMC_CLK: clk = dev->emc_clk; #ifndef CONFIG_ARCH_TEGRA_2x_SOC dev_dbg(dev->dev, "%s: emc_clk rate=%lu\n", __func__, info->rate); clk_set_rate(dev->emc_clk, info->rate); #endif goto set_rate_end; default: dev_err(dev->dev, "%s: invalid clk id for set rate %d\n", __func__, info->clk_id); return -EINVAL; } clk_parent = clk_get_parent(clk); parent_rate = clk_get_rate(clk_parent); dev_dbg(dev->dev, "%s: clk_id=%d, parent_rate=%lu, clk_rate=%lu\n", __func__, info->clk_id, parent_rate, info->rate); parent_div_rate = parent_rate; parent_div_rate_pre = parent_rate; /* * The requested clock rate from user space should be respected. * This loop is to search the clock rate that is higher than requested * clock. */ while (parent_div_rate >= info->rate) { parent_div_rate_pre = parent_div_rate; parent_div_rate = clk_round_rate(clk, parent_div_rate-1); } dev_dbg(dev->dev, "%s: set_rate=%lu", __func__, parent_div_rate_pre); clk_set_rate(clk, parent_div_rate_pre); if (info->clk_id == TEGRA_CAMERA_VI_CLK) { /* * bit 25: 0 = pd2vi_Clk, 1 = vi_sensor_clk * bit 24: 0 = internal clock, 1 = external clock(pd2vi_clk) */ if (info->flag == TEGRA_CAMERA_ENABLE_PD2VI_CLK) tegra_clk_cfg_ex(clk, TEGRA_CLK_VI_INP_SEL, 2); #ifdef CONFIG_ARCH_TEGRA_2x_SOC u32 val; void __iomem *apb_misc = IO_ADDRESS(TEGRA_APB_MISC_BASE); val = readl(apb_misc + 0x42c); writel(val | 0x1, apb_misc + 0x42c); #endif } set_rate_end: info->rate = clk_get_rate(clk); dev_dbg(dev->dev, "%s: get_rate=%lu", __func__, info->rate); return 0; }
static u32 pxav2_get_max_clock(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); return clk_get_rate(pltfm_host->clk); }
void __init_or_cpufreq s5pv210_setup_clocks(void) { struct clk *xtal_clk; unsigned long vpllsrc; unsigned long armclk; unsigned long hclk_msys; unsigned long hclk_dsys; unsigned long hclk_psys; unsigned long pclk_msys; unsigned long pclk_dsys; unsigned long pclk_psys; unsigned long apll; unsigned long mpll; unsigned long epll; unsigned long vpll; unsigned int ptr; u32 clkdiv0, clkdiv1; /* Set functions for clk_fout_epll */ clk_fout_epll.enable = s5p_epll_enable; clk_fout_epll.ops = &s5pv210_epll_ops; printk(KERN_DEBUG "%s: registering clocks\n", __func__); clkdiv0 = __raw_readl(S5P_CLK_DIV0); clkdiv1 = __raw_readl(S5P_CLK_DIV1); printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", __func__, clkdiv0, clkdiv1); xtal_clk = clk_get(NULL, "xtal"); BUG_ON(IS_ERR(xtal_clk)); xtal = clk_get_rate(xtal_clk); clk_put(xtal_clk); printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON), __raw_readl(S5P_EPLL_CON1), pll_4600); vpllsrc = clk_get_rate(&clk_vpllsrc.clk); vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502); clk_fout_apll.ops = &clk_fout_apll_ops; clk_fout_mpll.rate = mpll; clk_fout_epll.rate = epll; clk_fout_vpll.rate = vpll; printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", apll, mpll, epll, vpll); armclk = clk_get_rate(&clk_armclk.clk); hclk_msys = clk_get_rate(&clk_hclk_msys.clk); hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk); hclk_psys = clk_get_rate(&clk_hclk_psys.clk); pclk_msys = clk_get_rate(&clk_pclk_msys.clk); pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk); pclk_psys = clk_get_rate(&clk_pclk_psys.clk); printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n" "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n", armclk, hclk_msys, hclk_dsys, hclk_psys, pclk_msys, pclk_dsys, pclk_psys); clk_f.rate = armclk; clk_h.rate = hclk_psys; clk_p.rate = pclk_psys; for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) s3c_set_clksrc(&clksrcs[ptr], true); }
/** * This function mainly configures the clock frequency of MCLK (HCKT/HCKR) * * @Parameters: * clk_id: The clock source of HCKT/HCKR * (Input from outside; output from inside, FSYS or EXTAL) * freq: The required clock rate of HCKT/HCKR * dir: The clock direction of HCKT/HCKR * * Note: If the direction is input, we do not care about clk_id. */ static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, unsigned int freq, int dir) { struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); struct clk *clksrc = esai_priv->extalclk; bool tx = clk_id <= ESAI_HCKT_EXTAL; bool in = dir == SND_SOC_CLOCK_IN; u32 ratio, ecr = 0; unsigned long clk_rate; int ret; /* Bypass divider settings if the requirement doesn't change */ if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx]) return 0; /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */ esai_priv->sck_div[tx] = true; /* Set the direction of HCKT/HCKR pins */ regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD); if (in) goto out; switch (clk_id) { case ESAI_HCKT_FSYS: case ESAI_HCKR_FSYS: clksrc = esai_priv->fsysclk; break; case ESAI_HCKT_EXTAL: ecr |= ESAI_ECR_ETI; case ESAI_HCKR_EXTAL: ecr |= ESAI_ECR_ERI; break; default: return -EINVAL; } if (IS_ERR(clksrc)) { dev_err(dai->dev, "no assigned %s clock\n", clk_id % 2 ? "extal" : "fsys"); return PTR_ERR(clksrc); } clk_rate = clk_get_rate(clksrc); ratio = clk_rate / freq; if (ratio * freq > clk_rate) ret = ratio * freq - clk_rate; else if (ratio * freq < clk_rate) ret = clk_rate - ratio * freq; else ret = 0; /* Block if clock source can not be divided into the required rate */ if (ret != 0 && clk_rate / ret < 1000) { dev_err(dai->dev, "failed to derive required HCK%c rate\n", tx ? 'T' : 'R'); return -EINVAL; } /* Only EXTAL source can be output directly without using PSR and PM */ if (ratio == 1 && clksrc == esai_priv->extalclk) { /* Bypass all the dividers if not being needed */ ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO; goto out; } else if (ratio < 2) { /* The ratio should be no less than 2 if using other sources */ dev_err(dai->dev, "failed to derive required HCK%c rate\n", tx ? 'T' : 'R'); return -EINVAL; } ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0); if (ret) return ret; esai_priv->sck_div[tx] = false; out: esai_priv->hck_dir[tx] = dir; esai_priv->hck_rate[tx] = freq; regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR, tx ? ESAI_ECR_ETI | ESAI_ECR_ETO : ESAI_ECR_ERI | ESAI_ECR_ERO, ecr); return 0; }
static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk) { return clk_get_rate(clk->parent) / 2; }
static u32 exynos_usb_phy_set_clock(struct platform_device *pdev) { struct clk *ref_clk; u32 refclk_freq = 0; if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412()) ref_clk = clk_get(&pdev->dev, "xusbxti"); else ref_clk = clk_get(&pdev->dev, "ext_xtal"); if (IS_ERR(ref_clk)) { dev_err(&pdev->dev, "Failed to get reference clock\n"); return PTR_ERR(ref_clk); } if (soc_is_exynos4210()) { switch (clk_get_rate(ref_clk)) { case 12 * MHZ: refclk_freq = EXYNOS4210_CLKSEL_12M; break; case 48 * MHZ: refclk_freq = EXYNOS4210_CLKSEL_48M; break; case 24 * MHZ: default: /* default reference clock */ refclk_freq = EXYNOS4210_CLKSEL_24M; break; } } else if (soc_is_exynos4212() | soc_is_exynos4412()) { switch (clk_get_rate(ref_clk)) { case 96 * 100000: refclk_freq = EXYNOS4212_CLKSEL_9600K; break; case 10 * MHZ: refclk_freq = EXYNOS4212_CLKSEL_10M; break; case 12 * MHZ: refclk_freq = EXYNOS4212_CLKSEL_12M; break; case 192 * 100000: refclk_freq = EXYNOS4212_CLKSEL_19200K; break; case 20 * MHZ: refclk_freq = EXYNOS4212_CLKSEL_20M; break; case 24 * MHZ: default: /* default reference clock */ refclk_freq = EXYNOS4212_CLKSEL_24M; break; } } else { switch (clk_get_rate(ref_clk)) { case 96 * 100000: refclk_freq = EXYNOS5_CLKSEL_9600K; break; case 10 * MHZ: refclk_freq = EXYNOS5_CLKSEL_10M; break; case 12 * MHZ: refclk_freq = EXYNOS5_CLKSEL_12M; break; case 192 * 100000: refclk_freq = EXYNOS5_CLKSEL_19200K; break; case 20 * MHZ: refclk_freq = EXYNOS5_CLKSEL_20M; break; case 50 * MHZ: refclk_freq = EXYNOS5_CLKSEL_50M; break; case 24 * MHZ: default: /* default reference clock */ refclk_freq = EXYNOS5_CLKSEL_24M; break; } } clk_put(ref_clk); return refclk_freq; }
int tegra_das_get_mclk_rate(void) { return clk_get_rate(aud_manager->mclk); }
static void __init global_timer_of_register(struct device_node *np) { struct clk *gt_clk; int err = 0; /* * In A9 r2p0 the comparators for each processor with the global timer * fire when the timer value is greater than or equal to. In previous * revisions the comparators fired when the timer value was equal to. */ if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9 && (read_cpuid_id() & 0xf0000f) < 0x200000) { pr_warn("global-timer: non support for this cpu version.\n"); return; } gt_ppi = irq_of_parse_and_map(np, 0); if (!gt_ppi) { pr_warn("global-timer: unable to parse irq\n"); return; } gt_base = of_iomap(np, 0); if (!gt_base) { pr_warn("global-timer: invalid base address\n"); return; } gt_clk = of_clk_get(np, 0); if (!IS_ERR(gt_clk)) { err = clk_prepare_enable(gt_clk); if (err) goto out_unmap; } else { pr_warn("global-timer: clk not found\n"); err = -EINVAL; goto out_unmap; } gt_clk_rate = clk_get_rate(gt_clk); gt_evt = alloc_percpu(struct clock_event_device); if (!gt_evt) { pr_warn("global-timer: can't allocate memory\n"); err = -ENOMEM; goto out_clk; } err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt, "gt", gt_evt); if (err) { pr_warn("global-timer: can't register interrupt %d (%d)\n", gt_ppi, err); goto out_free; } err = register_cpu_notifier(>_cpu_nb); if (err) { pr_warn("global-timer: unable to register cpu notifier.\n"); goto out_irq; } /* Immediately configure the timer on the boot CPU */ gt_clocksource_init(); gt_clockevents_init(this_cpu_ptr(gt_evt)); return; out_irq: free_percpu_irq(gt_ppi, gt_evt); out_free: free_percpu(gt_evt); out_clk: clk_disable_unprepare(gt_clk); out_unmap: iounmap(gt_base); WARN(err, "ARM Global timer register failed (%d)\n", err); }
/* * General clocks * * clk_get_rate */ static unsigned long rtc_clk_get_rate(struct clk *clk) { /* ref_xtal_clk is implemented as the only parent */ return clk_get_rate(clk->parent) / 768; }
static int serial_pxa_probe(struct platform_device *dev) { struct uart_pxa_port *sport; struct resource *mmres, *irqres; int ret; mmres = platform_get_resource(dev, IORESOURCE_MEM, 0); irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0); if (!mmres || !irqres) return -ENODEV; sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL); if (!sport) return -ENOMEM; sport->clk = clk_get(&dev->dev, "UARTCLK"); if (IS_ERR(sport->clk)) { ret = PTR_ERR(sport->clk); goto err_free; } sport->port.type = PORT_PXA; sport->port.iotype = UPIO_MEM; sport->port.mapbase = mmres->start; sport->port.irq = irqres->start; sport->port.fifosize = 64; sport->port.ops = &serial_pxa_pops; sport->port.line = dev->id; sport->port.dev = &dev->dev; sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; sport->port.uartclk = clk_get_rate(sport->clk); /* * Is it worth keeping this? */ if (mmres->start == __PREG(FFUART)) sport->name = "FFUART"; else if (mmres->start == __PREG(BTUART)) sport->name = "BTUART"; else if (mmres->start == __PREG(STUART)) sport->name = "STUART"; else if (mmres->start == __PREG(HWUART)) sport->name = "HWUART"; else sport->name = "???"; sport->port.membase = ioremap(mmres->start, mmres->end - mmres->start + 1); if (!sport->port.membase) { ret = -ENOMEM; goto err_clk; } serial_pxa_ports[dev->id] = sport; uart_add_one_port(&serial_pxa_reg, &sport->port); platform_set_drvdata(dev, sport); return 0; err_clk: clk_put(sport->clk); err_free: kfree(sport); return ret; }
static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, int gptimer_id, const char *fck_source) { char name[10]; /* 10 = sizeof("gptXX_Xck0") */ struct omap_hwmod *oh; struct resource irq_rsrc, mem_rsrc; size_t size; int res = 0; int r; sprintf(name, "timer%d", gptimer_id); omap_hwmod_setup_one(name); oh = omap_hwmod_lookup(name); if (!oh) return -ENODEV; r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc); if (r) return -ENXIO; timer->irq = irq_rsrc.start; r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc); if (r) return -ENXIO; timer->phys_base = mem_rsrc.start; size = mem_rsrc.end - mem_rsrc.start; /* Static mapping, never released */ timer->io_base = ioremap(timer->phys_base, size); if (!timer->io_base) return -ENXIO; /* After the dmtimer is using hwmod these clocks won't be needed */ timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); if (IS_ERR(timer->fclk)) return -ENODEV; omap_hwmod_enable(oh); if (omap_dm_timer_reserve_systimer(gptimer_id)) return -ENODEV; if (gptimer_id != 12) { struct clk *src; src = clk_get(NULL, fck_source); if (IS_ERR(src)) { res = -EINVAL; } else { res = __omap_dm_timer_set_source(timer->fclk, src); if (IS_ERR_VALUE(res)) pr_warning("%s: timer%i cannot set source\n", __func__, gptimer_id); clk_put(src); } } __omap_dm_timer_init_regs(timer); __omap_dm_timer_reset(timer, 1, 1); timer->posted = 1; timer->rate = clk_get_rate(timer->fclk); timer->reserved = 1; return res; }
/** * sdc_init_panel() - initialize a synchronous LCD panel. * @mx3fb: mx3fb context. * @panel: panel type. * @pixel_clk: desired pixel clock frequency in Hz. * @width: width of panel in pixels. * @height: height of panel in pixels. * @pixel_fmt: pixel format of buffer as FOURCC ASCII code. * @h_start_width: number of pixel clocks between the HSYNC signal pulse * and the start of valid data. * @h_sync_width: width of the HSYNC signal in units of pixel clocks. * @h_end_width: number of pixel clocks between the end of valid data * and the HSYNC signal for next line. * @v_start_width: number of lines between the VSYNC signal pulse and the * start of valid data. * @v_sync_width: width of the VSYNC signal in units of lines * @v_end_width: number of lines between the end of valid data and the * VSYNC signal for next frame. * @sig: bitfield of signal polarities for LCD interface. * @return: 0 on success or negative error code on failure. */ static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel, uint32_t pixel_clk, uint16_t width, uint16_t height, enum pixel_fmt pixel_fmt, uint16_t h_start_width, uint16_t h_sync_width, uint16_t h_end_width, uint16_t v_start_width, uint16_t v_sync_width, uint16_t v_end_width, struct ipu_di_signal_cfg sig) { unsigned long lock_flags; uint32_t reg; uint32_t old_conf; uint32_t div; struct clk *ipu_clk; dev_dbg(mx3fb->dev, "panel size = %d x %d", width, height); if (v_sync_width == 0 || h_sync_width == 0) return -EINVAL; /* Init panel size and blanking periods */ reg = ((uint32_t) (h_sync_width - 1) << 26) | ((uint32_t) (width + h_start_width + h_end_width - 1) << 16); mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF); #ifdef DEBUG printk(KERN_CONT " hor_conf %x,", reg); #endif reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L | ((uint32_t) (height + v_start_width + v_end_width - 1) << 16); mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF); #ifdef DEBUG printk(KERN_CONT " ver_conf %x\n", reg); #endif mx3fb->h_start_width = h_start_width; mx3fb->v_start_width = v_start_width; switch (panel) { case IPU_PANEL_SHARP_TFT: mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1); mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2); mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF); break; case IPU_PANEL_TFT: mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF); break; default: return -EINVAL; } /* Init clocking */ /* * Calculate divider: fractional part is 4 bits so simply multiple by * 2^4 to get fractional part, as long as we stay under ~250MHz and on * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz */ ipu_clk = clk_get(mx3fb->dev, NULL); if (!IS_ERR(ipu_clk)) { div = clk_get_rate(ipu_clk) * 16 / pixel_clk; clk_put(ipu_clk); } else { div = 0; } if (div < 0x40) { /* Divider less than 4 */ dev_dbg(mx3fb->dev, "InitPanel() - Pixel clock divider less than 4\n"); div = 0x40; } dev_dbg(mx3fb->dev, "pixel clk = %u, divider %u.%u\n", pixel_clk, div >> 4, (div & 7) * 125); spin_lock_irqsave(&mx3fb->lock, lock_flags); /* * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits * fewer. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing * debug. DISP3_IF_CLK_UP_WR is 0 */ mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF); /* DI settings */ old_conf = mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF) & 0x78FFFFFF; old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT | sig.clksel_en << DI_D3_CLK_SEL_SHIFT | sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT; mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF); old_conf = mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL) & 0xE0FFFFFF; old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT | sig.clk_pol << DI_D3_CLK_POL_SHIFT | sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT | sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT | sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT; mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL); switch (pixel_fmt) { case IPU_PIX_FMT_RGB24: mx3fb_write_reg(mx3fb, di_mappings[0], DI_DISP3_B0_MAP); mx3fb_write_reg(mx3fb, di_mappings[1], DI_DISP3_B1_MAP); mx3fb_write_reg(mx3fb, di_mappings[2], DI_DISP3_B2_MAP); mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | ((di_mappings[3] - 1) << 12), DI_DISP_ACC_CC); break; case IPU_PIX_FMT_RGB666: mx3fb_write_reg(mx3fb, di_mappings[4], DI_DISP3_B0_MAP); mx3fb_write_reg(mx3fb, di_mappings[5], DI_DISP3_B1_MAP); mx3fb_write_reg(mx3fb, di_mappings[6], DI_DISP3_B2_MAP); mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | ((di_mappings[7] - 1) << 12), DI_DISP_ACC_CC); break; case IPU_PIX_FMT_BGR666: mx3fb_write_reg(mx3fb, di_mappings[8], DI_DISP3_B0_MAP); mx3fb_write_reg(mx3fb, di_mappings[9], DI_DISP3_B1_MAP); mx3fb_write_reg(mx3fb, di_mappings[10], DI_DISP3_B2_MAP); mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | ((di_mappings[11] - 1) << 12), DI_DISP_ACC_CC); break; default: mx3fb_write_reg(mx3fb, di_mappings[12], DI_DISP3_B0_MAP); mx3fb_write_reg(mx3fb, di_mappings[13], DI_DISP3_B1_MAP); mx3fb_write_reg(mx3fb, di_mappings[14], DI_DISP3_B2_MAP); mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | ((di_mappings[15] - 1) << 12), DI_DISP_ACC_CC); break; } spin_unlock_irqrestore(&mx3fb->lock, lock_flags); dev_dbg(mx3fb->dev, "DI_DISP_IF_CONF = 0x%08X\n", mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF)); dev_dbg(mx3fb->dev, "DI_DISP_SIG_POL = 0x%08X\n", mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL)); dev_dbg(mx3fb->dev, "DI_DISP3_TIME_CONF = 0x%08X\n", mx3fb_read_reg(mx3fb, DI_DISP3_TIME_CONF)); return 0; }
static inline void __init apollon_init_smc91x(void) { unsigned long base; unsigned int rate; struct clk *gpmc_fck; int eth_cs; int err; gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */ if (IS_ERR(gpmc_fck)) { WARN_ON(1); return; } clk_enable(gpmc_fck); rate = clk_get_rate(gpmc_fck); eth_cs = APOLLON_ETH_CS; /* Make sure CS1 timings are correct */ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200); if (rate >= 160000000) { gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); } else if (rate >= 130000000) { gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); } else {/* rate = 100000000 */ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2); } if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) { printk(KERN_ERR "Failed to request GPMC CS for smc91x\n"); goto out; } apollon_smc91x_resources[0].start = base + 0x300; apollon_smc91x_resources[0].end = base + 0x30f; udelay(100); omap_mux_init_gpio(APOLLON_ETHR_GPIO_IRQ, 0); err = gpio_request_one(APOLLON_ETHR_GPIO_IRQ, GPIOF_IN, "SMC91x irq"); if (err) { printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", APOLLON_ETHR_GPIO_IRQ); gpmc_cs_free(APOLLON_ETH_CS); } out: clk_disable(gpmc_fck); clk_put(gpmc_fck); }