void __init ux500_init_irq(void) { void __iomem *dist_base; void __iomem *cpu_base; if (cpu_is_u5500()) { dist_base = __io_address(U5500_GIC_DIST_BASE); cpu_base = __io_address(U5500_GIC_CPU_BASE); } else if (cpu_is_u8500()) { dist_base = __io_address(U8500_GIC_DIST_BASE); cpu_base = __io_address(U8500_GIC_CPU_BASE); } else ux500_unknown_soc(); #ifdef CONFIG_OF if (of_have_populated_dt()) of_irq_init(ux500_dt_irq_match); else #endif gic_init(0, 29, dist_base, cpu_base); if (cpu_is_u5500()) db5500_prcmu_early_init(); if (cpu_is_u8500()) db8500_prcmu_early_init(); clk_init(); }
void __init ux500_init_irq(void) { void __iomem *dist_base; void __iomem *cpu_base; if (cpu_is_u5500()) { dist_base = __io_address(U5500_GIC_DIST_BASE); cpu_base = __io_address(U5500_GIC_CPU_BASE); } else if (cpu_is_u8500()) { dist_base = __io_address(U8500_GIC_DIST_BASE); cpu_base = __io_address(U8500_GIC_CPU_BASE); } else ux500_unknown_soc(); gic_init(0, 29, dist_base, cpu_base); /* * Init clocks here so that they are available for system timer * initialization. */ if (cpu_is_u5500()) db5500_prcmu_early_init(); if (cpu_is_u8500()) prcmu_early_init(); clk_init(); }
void __init ux500_init_irq(void) { void __iomem *dist_base; void __iomem *cpu_base; gic_arch_extn.irq_set_wake = ux500_gic_irq_set_wake; if (cpu_is_u5500()) { dist_base = __io_address(U5500_GIC_DIST_BASE); cpu_base = __io_address(U5500_GIC_CPU_BASE); } else if (cpu_is_u8500() || cpu_is_u9540()) { dist_base = __io_address(U8500_GIC_DIST_BASE); cpu_base = __io_address(U8500_GIC_CPU_BASE); } else ux500_unknown_soc(); gic_init(0, 29, dist_base, cpu_base); /* * On WD reboot gic is in some cases decoupled. * This will make sure that the GIC is correctly configured. */ ux500_pm_gic_recouple(); /* * Init clocks here so that they are available for system timer * initialization. */ prcmu_early_init(); /* backwards compatible */ if (!arm_pm_restart) arm_pm_restart = ux500_restart; clk_init(); }
static void __init ux500_timer_init(void) { void __iomem *prcmu_timer_base; if (cpu_is_u5500()) { mtu_base = __io_address(U5500_MTU0_BASE); prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE); } else if (cpu_is_u8500()) { mtu_base = __io_address(U8500_MTU0_BASE); prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE); } else { ux500_unknown_soc(); } /* * Here we register the timerblocks active in the system. * Localtimers (twd) is started when both cpu is up and running. * MTU register a clocksource, clockevent and sched_clock. * Since the MTU is located in the VAPE power domain * it will be cleared in sleep which makes it unsuitable. * We however need it as a timer tick (clockevent) * during boot to calibrate delay until twd is started. * RTC-RTT have problems as timer tick during boot since it is * depending on delay which is not yet calibrated. RTC-RTT is in the * always-on powerdomain and is used as clockevent instead of twd when * sleeping. * The PRCMU timer 4(3 for DB5500) register a clocksource and * sched_clock with higher rating then MTU since is always-on. * */ nmdk_timer_init(); clksrc_dbx500_prcmu_init(prcmu_timer_base); ux500_twd_init(); }
static int __init ux500_debug_last_io_init(void) { size_t size; size = sizeof(struct ux500_debug_last_io) * num_possible_cpus(); ux500_last_io = dma_alloc_coherent(NULL, size, &ux500_last_io_phys, GFP_KERNEL); if (!ux500_last_io) { ; return -ENOMEM; } if (cpu_is_u5500()) l2x0_base = __io_address(U5500_L2CC_BASE); else if (cpu_is_u8500() || cpu_is_u9540()) l2x0_base = __io_address(U8500_L2CC_BASE); /* * CONFIG_UX500_DEBUG_LAST_IO is only intended for debugging. * It should not be left enabled. */ WARN_ON(1); return 0; }
static int __init ux500_l2x0_init(void) { uint32_t aux_val = 0x3e000000; if (cpu_is_u5500()) l2x0_base = __io_address(U5500_L2CC_BASE); else if (cpu_is_u8500() || cpu_is_u9540()) l2x0_base = __io_address(U8500_L2CC_BASE); else ux500_unknown_soc(); /* u9540's L2 has 128KB way size */ if (cpu_is_u9540()) aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT); /* 128KB way size */ else aux_val |= (0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT); /* 64KB way size */ /* 8 way associativity, force WA */ l2x0_init(l2x0_base, aux_val, 0xc0000fff); /* Override invalidate function */ outer_cache.disable = ux500_l2x0_disable; outer_cache.inv_all = ux500_l2x0_inv_all; return 0; }
static void __init wakeup_secondary(void) { void __iomem *backupram; if (cpu_is_u5500()) backupram = __io_address(U5500_BACKUPRAM0_BASE); else if (cpu_is_u8500() || cpu_is_u9540()) backupram = __io_address(U8500_BACKUPRAM0_BASE); else ux500_unknown_soc(); /* * write the address of secondary startup into the backup ram register * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the * backup ram register at offset 0x1FF0, which is what boot rom code * is waiting for. This would wake up the secondary core from WFE */ #define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4 __raw_writel(virt_to_phys(u8500_secondary_startup), backupram + UX500_CPU1_JUMPADDR_OFFSET); #define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0 __raw_writel(0xA1FEED01, backupram + UX500_CPU1_WAKEMAGIC_OFFSET); /* make sure write buffer is drained */ mb(); }
static int __init init_display_devices(void) { if (cpu_is_u8500()) return handle_display_devices_in_u8500(); else if (cpu_is_u9540()) return handle_display_devices_in_u9540(); else return 0; }
int __init clk_init(void) { if (cpu_is_u8500()) { prcmu_base = __io_address(U8500_PRCMU_BASE); } else if (cpu_is_u5500()) { prcmu_base = __io_address(U5500_PRCMU_BASE); } else { pr_err("clock: Unknown DB Asic.\n"); return -EIO; } if (cpu_is_u8500()) db8500_clk_init(); else if (cpu_is_u5500()) db5500_clk_init(); return 0; }
static void __iomem *scu_base_addr(void) { if (cpu_is_u5500()) return __io_address(U5500_SCU_BASE); else if (cpu_is_u8500() || cpu_is_u9540()) return __io_address(U8500_SCU_BASE); else ux500_unknown_soc(); return NULL; }
u32 ux500_pm_gpio_read_wake_up_status(unsigned int bank_num) { if (WARN_ON(cpu_is_u5500() && bank_num >= ARRAY_SIZE(u5500_gpio_banks))) return 0; if (WARN_ON(cpu_is_u8500() && bank_num >= ARRAY_SIZE(u8500_gpio_banks))) return 0; return ux500_gpio_wks[bank_num]; }
void __init mtu_timer_init(void) { unsigned long rate; struct clk *clk0; clk0 = clk_get_sys("mtu0", NULL); BUG_ON(IS_ERR(clk0)); rate = clk_get_rate(clk0); clk_enable(clk0); /* * Set scale and timer for sched_clock */ setup_sched_clock(rate); u8500_cycle = (rate + HZ/2) / HZ; /* Save global pointer to mtu, used by functions above */ if (cpu_is_u5500()) { mtu0_base = ioremap(U5500_MTU0_BASE, SZ_4K); } else if (cpu_is_u8500()) { mtu0_base = ioremap(U8500_MTU0_BASE, SZ_4K); } else { ux500_unknown_soc(); } /* Restart clock source */ mtu_clocksource_reset(); /* Now the scheduling clock is ready */ u8500_clksrc.read = u8500_read_timer; u8500_clksrc.mult = clocksource_hz2mult(rate, u8500_clksrc.shift); clocksource_register(&u8500_clksrc); /* Register irq and clockevents */ /* We can sleep for max 10s (actually max is longer) */ clockevents_calc_mult_shift(&u8500_mtu_clkevt, rate, 10); u8500_mtu_clkevt.max_delta_ns = clockevent_delta2ns(0xffffffff, &u8500_mtu_clkevt); u8500_mtu_clkevt.min_delta_ns = clockevent_delta2ns(0xff, &u8500_mtu_clkevt); setup_irq(IRQ_MTU0, &u8500_timer_irq); clockevents_register_device(&u8500_mtu_clkevt); #ifdef ARCH_HAS_READ_CURRENT_TIMER set_delay_fn(mtu_timer_delay_loop); #endif }
static int __init prefetch_ctrl_init(void) { int err; int origin_err; /* Selects trustzone application needed for the job. */ struct tee_uuid static_uuid = { L2X0_UUID_TEE_TA_START_LOW, L2X0_UUID_TEE_TA_START_MID, L2X0_UUID_TEE_TA_START_HIGH, L2X0_UUID_TEE_TA_START_CLOCKSEQ, }; /* Get PL310 base address. It will be used as readonly. */ if (cpu_is_u5500()) l2x0_base = __io_address(U5500_L2CC_BASE); else if (cpu_is_u8500() || cpu_is_u9540()) l2x0_base = __io_address(U8500_L2CC_BASE); else ux500_unknown_soc(); err = teec_initialize_context(NULL, &context); if (err) { pr_err("l2x0-prefetch: unable to initialize tee context," " err = %d\n", err); err = -EINVAL; goto error0; } err = teec_open_session(&context, &session, &static_uuid, TEEC_LOGIN_PUBLIC, NULL, NULL, &origin_err); if (err) { pr_err("l2x0-prefetch: unable to open tee session," " tee error = %d, origin error = %d\n", err, origin_err); err = -EINVAL; goto error1; } outer_cache.prefetch_enable = prefetch_enable; outer_cache.prefetch_disable = prefetch_disable; pr_info("l2x0-prefetch: initialized.\n"); return 0; error1: (void)teec_finalize_context(&context); error0: return err; }
static int ux500_l2x0_init(void) { if (cpu_is_u5500()) l2x0_base = __io_address(U5500_L2CC_BASE); else if (cpu_is_u8500()) l2x0_base = __io_address(U8500_L2CC_BASE); else ux500_unknown_soc(); /* 64KB way size, 8 way associativity, force WA */ l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); /* Override invalidate function */ outer_cache.disable = ux500_l2x0_disable; outer_cache.inv_all = ux500_l2x0_inv_all; return 0; }
/* * Save VAPE context */ void context_vape_save(void) { atomic_notifier_call_chain(&context_ape_notifier_list, CONTEXT_APE_SAVE, NULL); if (cpu_is_u5500()) u5500_context_save_icn(); if (cpu_is_u8500()) u8500_context_save_icn(); if (cpu_is_u9540()) u9540_context_save_icn(); save_stm_ape(); save_tpiu(); save_prcc(); }
/* * Restore VAPE context */ void context_vape_restore(void) { restore_prcc(); restore_tpiu(); restore_stm_ape(); if (cpu_is_u5500()) u5500_context_restore_icn(); if (cpu_is_u8500()) u8500_context_restore_icn(); if (cpu_is_u9540()) u9540_context_restore_icn(); atomic_notifier_call_chain(&context_ape_notifier_list, CONTEXT_APE_RESTORE, NULL); }
void __init ux500_init_irq(void) { void __iomem *dist_base; if (cpu_is_u5500()) { gic_cpu_base_addr = __io_address(U5500_GIC_CPU_BASE); dist_base = __io_address(U5500_GIC_DIST_BASE); } else if (cpu_is_u8500()) { gic_cpu_base_addr = __io_address(U8500_GIC_CPU_BASE); dist_base = __io_address(U8500_GIC_DIST_BASE); } else ux500_unknown_soc(); gic_dist_init(0, dist_base, 29); gic_cpu_init(0, gic_cpu_base_addr); /* * Init clocks here so that they are available for system timer * initialization. */ prcmu_early_init(); arm_pm_restart = ux500_restart; clk_init(); }
static int __init context_init(void) { int i; void __iomem *ux500_backup_ptr; /* allocate backup pointer for RAM data */ ux500_backup_ptr = (void *)__get_free_pages(GFP_KERNEL, get_order(U8500_BACKUPRAM_SIZE)); if (!ux500_backup_ptr) { pr_warning("context: could not allocate backup memory\n"); return -ENOMEM; } /* * ROM code addresses to store backup contents, * pass the physical address of back up to ROM code */ writel(virt_to_phys(ux500_backup_ptr), IO_ADDRESS(U8500_EXT_RAM_LOC_BACKUPRAM_ADDR)); if (cpu_is_u5500()) { writel(IO_ADDRESS(U5500_PUBLIC_BOOT_ROM_BASE), IO_ADDRESS(U8500_CPU0_BACKUPRAM_ADDR_PUBLIC_BOOT_ROM_LOG_ADDR)); writel(IO_ADDRESS(U5500_PUBLIC_BOOT_ROM_BASE), IO_ADDRESS(U8500_CPU1_BACKUPRAM_ADDR_PUBLIC_BOOT_ROM_LOG_ADDR)); context_tpiu.base = ioremap(U5500_TPIU_BASE, SZ_4K); context_stm_ape.base = ioremap(U5500_STM_REG_BASE, SZ_4K); context_scu.base = ioremap(U5500_SCU_BASE, SZ_4K); context_prcc[0].base = ioremap(U5500_CLKRST1_BASE, SZ_4K); context_prcc[1].base = ioremap(U5500_CLKRST2_BASE, SZ_4K); context_prcc[2].base = ioremap(U5500_CLKRST3_BASE, SZ_4K); context_prcc[3].base = ioremap(U5500_CLKRST5_BASE, SZ_4K); context_prcc[4].base = ioremap(U5500_CLKRST6_BASE, SZ_4K); context_gic_dist_common.base = ioremap(U5500_GIC_DIST_BASE, SZ_4K); per_cpu(context_gic_cpu, 0).base = ioremap(U5500_GIC_CPU_BASE, SZ_4K); } else if (cpu_is_u8500() || cpu_is_u9540()) { /* Give logical address to backup RAM. For both CPUs */ if (cpu_is_u9540()) { writel(IO_ADDRESS_DB9540_ROM(U9540_PUBLIC_BOOT_ROM_BASE), IO_ADDRESS(U8500_CPU0_BACKUPRAM_ADDR_PUBLIC_BOOT_ROM_LOG_ADDR)); writel(IO_ADDRESS_DB9540_ROM(U9540_PUBLIC_BOOT_ROM_BASE), IO_ADDRESS(U8500_CPU1_BACKUPRAM_ADDR_PUBLIC_BOOT_ROM_LOG_ADDR)); } else { writel(IO_ADDRESS(U8500_PUBLIC_BOOT_ROM_BASE), IO_ADDRESS(U8500_CPU0_BACKUPRAM_ADDR_PUBLIC_BOOT_ROM_LOG_ADDR)); writel(IO_ADDRESS(U8500_PUBLIC_BOOT_ROM_BASE), IO_ADDRESS(U8500_CPU1_BACKUPRAM_ADDR_PUBLIC_BOOT_ROM_LOG_ADDR)); } context_tpiu.base = ioremap(U8500_TPIU_BASE, SZ_4K); context_stm_ape.base = ioremap(U8500_STM_REG_BASE, SZ_4K); context_scu.base = ioremap(U8500_SCU_BASE, SZ_4K); /* PERIPH4 is always on, so no need saving prcc */ context_prcc[0].base = ioremap(U8500_CLKRST1_BASE, SZ_4K); context_prcc[1].base = ioremap(U8500_CLKRST2_BASE, SZ_4K); context_prcc[2].base = ioremap(U8500_CLKRST3_BASE, SZ_4K); context_prcc[3].base = ioremap(U8500_CLKRST5_BASE, SZ_4K); context_prcc[4].base = ioremap(U8500_CLKRST6_BASE, SZ_4K); context_gic_dist_common.base = ioremap(U8500_GIC_DIST_BASE, SZ_4K); per_cpu(context_gic_cpu, 0).base = ioremap(U8500_GIC_CPU_BASE, SZ_4K); } per_cpu(context_gic_dist_cpu, 0).base = context_gic_dist_common.base; for (i = 1; i < num_possible_cpus(); i++) { per_cpu(context_gic_cpu, i).base = per_cpu(context_gic_cpu, 0).base; per_cpu(context_gic_dist_cpu, i).base = per_cpu(context_gic_dist_cpu, 0).base; } for (i = 0; i < ARRAY_SIZE(context_prcc); i++) { const int clusters[] = {1, 2, 3, 5, 6}; char clkname[10]; snprintf(clkname, sizeof(clkname), "PERIPH%d", clusters[i]); context_prcc[i].clk = clk_get_sys(clkname, NULL); BUG_ON(IS_ERR(context_prcc[i].clk)); } if (cpu_is_u8500()) { u8500_context_init(); } else if (cpu_is_u5500()) { u5500_context_init(); } else if (cpu_is_u9540()) { u9540_context_init(); } else { printk(KERN_ERR "context: unknown hardware!\n"); return -EINVAL; } return 0; }
/* * This function will create the framebuffer for the display that is registered. */ static int display_postregistered_callback(struct notifier_block *nb, unsigned long event, void *dev) { struct mcde_display_device *ddev = dev; u16 width, height; u16 virtual_height; struct fb_info *fbi; #if defined(CONFIG_DISPDEV) || defined(CONFIG_COMPDEV) struct mcde_fb *mfb; #endif if (event != MCDE_DSS_EVENT_DISPLAY_REGISTERED) return 0; if (ddev->id < 0 || ddev->id >= MCDE_NR_OF_DISPLAYS) return 0; mcde_dss_get_native_resolution(ddev, &width, &height); #ifdef CONFIG_MCDE_DISPLAY_PRIMARY_TRIPPLE_BUFFERED if (ddev->id == PRIMARY_DISPLAY_ID) virtual_height = height * 3; else #endif virtual_height = height * 2; #ifndef CONFIG_MCDE_DISPLAY_HDMI_FB_AUTO_CREATE if (ddev->id == AV8100_DISPLAY_ID) goto out; #endif /* Create frame buffer */ fbi = mcde_fb_create(ddev, width, height, width, virtual_height, ddev->default_pixel_format, FB_ROTATE_UR); if (IS_ERR(fbi)) { dev_warn(&ddev->dev, "Failed to create fb for display %s\n", ddev->name); goto display_postregistered_callback_err; } else { dev_info(&ddev->dev, "Framebuffer created (%s)\n", ddev->name); } #ifdef CONFIG_DISPDEV mfb = to_mcde_fb(fbi); /* Create a dispdev overlay for this display */ if (dispdev_create(ddev, true, mfb->ovlys[0]) < 0) { dev_warn(&ddev->dev, "Failed to create disp for display %s\n", ddev->name); goto display_postregistered_callback_err; } else { dev_info(&ddev->dev, "Disp dev created for (%s)\n", ddev->name); } #endif #ifdef CONFIG_COMPDEV /* Only create compdev for the main display */ if (ddev->id == PRIMARY_DISPLAY_ID) { bool mcde_rotation = false; /* Use mcde rotation for U8500 only */ if (cpu_is_u8500()) mcde_rotation = true; mfb = to_mcde_fb(fbi); /* Create a compdev overlay for this display */ if (compdev_create(ddev, mfb->ovlys[0], mcde_rotation, NULL) < 0) { dev_warn(&ddev->dev, "Failed to create compdev for display %s\n", ddev->name); goto display_postregistered_callback_err; } else { dev_info(&ddev->dev, "compdev created for (%s)\n", ddev->name); } } #endif out: return 0; display_postregistered_callback_err: return -1; }
static long ux500_wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; int interval; static const struct watchdog_info ident = { .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, .firmware_version = 1, .identity = "Ux500 WDT", }; switch (cmd) { case WDIOC_GETSUPPORT: return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: return put_user(0, p); case WDIOC_SETOPTIONS: { int options; int ret = -EINVAL; if (get_user(options, p)) return -EFAULT; if (options & WDIOS_DISABLECARD) { ux500_wdt_ops->disable(wdog_id); wdt_en = false; ret = 0; } if (options & WDIOS_ENABLECARD) { ux500_wdt_ops->enable(wdog_id); wdt_en = true; ret = 0; } return ret; } case WDIOC_KEEPALIVE: return ux500_wdt_ops->kick(wdog_id); case WDIOC_SETTIMEOUT: if (get_user(interval, p)) return -EFAULT; if (cpu_is_u8500()) { /* 28 bit resolution in ms, becomes 268435.455 s */ if (interval > 268435 || interval < 0) return -EINVAL; } else if (cpu_is_u5500()) { /* 32 bit resolution in ms, becomes 4294967.295 s */ if (interval > 4294967 || interval < 0) return -EINVAL; } else return -EINVAL; timeout = interval; ux500_wdt_ops->disable(wdog_id); ux500_wdt_ops->load(wdog_id, timeout * 1000); ux500_wdt_ops->enable(wdog_id); /* Fall through */ case WDIOC_GETTIMEOUT: return put_user(timeout, p); default: return -ENOTTY; } return 0; } #ifdef CONFIG_SAMSUNG_LOG_BUF void wdog_disable() { ux500_wdt_ops->disable(wdog_id); wdt_en = false; }
bool cpu_is_u8500v22(void) { return cpu_is_u8500() && (dbx500_revision() == 0xB2); }