コード例 #1
0
ファイル: sh_pci.c プロジェクト: SJTU-IPADS/COREMU-QEMU
PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
                            void *opaque, int devfn_min, int nirq)
{
    SHPCIC *p;
    int reg;

    p = qemu_mallocz(sizeof(SHPCIC));
    p->bus = pci_register_bus(NULL, "pci",
                              set_irq, map_irq, opaque, devfn_min, nirq);

    p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),
                                 -1, NULL, NULL);
    reg = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, p,
                                 DEVICE_NATIVE_ENDIAN);
    cpu_register_physical_memory(0x1e200000, 0x224, reg);
    cpu_register_physical_memory(0xfe200000, 0x224, reg);

    p->iobr = 0xfe240000;
    isa_mmio_init(p->iobr, 0x40000);

    pci_config_set_vendor_id(p->dev->config, PCI_VENDOR_ID_HITACHI);
    pci_config_set_device_id(p->dev->config, PCI_DEVICE_ID_HITACHI_SH7751R);
    p->dev->config[0x04] = 0x80;
    p->dev->config[0x05] = 0x00;
    p->dev->config[0x06] = 0x90;
    p->dev->config[0x07] = 0x02;

    return p->bus;
}
コード例 #2
0
ファイル: arm_gic.c プロジェクト: AmesianX/winkvm
void *arm_gic_init(uint32_t base, void *parent, int parent_irq)
{
    gic_state *s;
    int iomemtype;

    s = (gic_state *)qemu_mallocz(sizeof(gic_state));
    if (!s)
        return NULL;
    s->handler = gic_set_irq;
    s->parent = parent;
    s->parent_irq = parent_irq;
    if (base != 0xffffffff) {
        iomemtype = cpu_register_io_memory(0, gic_cpu_readfn,
                                           gic_cpu_writefn, s);
        cpu_register_physical_memory(base, 0x00000fff, iomemtype);
        iomemtype = cpu_register_io_memory(0, gic_dist_readfn,
                                           gic_dist_writefn, s);
        cpu_register_physical_memory(base + 0x1000, 0x00000fff, iomemtype);
        s->base = base;
    } else {
        s->base = 0;
    }
    gic_reset(s);
    return s;
}
コード例 #3
0
ファイル: pxa2xx_pcmcia.c プロジェクト: EgoIncarnate/qemu-rr
PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base)
{
    int iomemtype;
    PXA2xxPCMCIAState *s;

    s = (PXA2xxPCMCIAState *)
            qemu_mallocz(sizeof(PXA2xxPCMCIAState));

    /* Socket I/O Memory Space */
    iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_io_readfn,
                    pxa2xx_pcmcia_io_writefn, s);
    cpu_register_physical_memory(base | 0x00000000, 0x04000000, iomemtype);

    /* Then next 64 MB is reserved */

    /* Socket Attribute Memory Space */
    iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_attr_readfn,
                    pxa2xx_pcmcia_attr_writefn, s);
    cpu_register_physical_memory(base | 0x08000000, 0x04000000, iomemtype);

    /* Socket Common Memory Space */
    iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_common_readfn,
                    pxa2xx_pcmcia_common_writefn, s);
    cpu_register_physical_memory(base | 0x0c000000, 0x04000000, iomemtype);

    if (base == 0x30000000)
        s->slot.slot_string = "PXA PC Card Socket 1";
    else
        s->slot.slot_string = "PXA PC Card Socket 0";
    s->slot.irq = qemu_allocate_irqs(pxa2xx_pcmcia_set_irq, s, 1)[0];
    pcmcia_socket_register(&s->slot);

    return s;
}
コード例 #4
0
ファイル: ds1225y.c プロジェクト: ESOS-Lab/VSSIM
/* Initialisation routine */
void *ds1225y_init(target_phys_addr_t mem_base, const char *filename)
{
    ds1225y_t *s;
    int mem_indexRW, mem_indexRP;
    QEMUFile *file;

    s = qemu_mallocz(sizeof(ds1225y_t));
    s->chip_size = 0x2000; /* Fixed for ds1225y chip: 8 KiB */
    s->contents = qemu_mallocz(s->chip_size);
    s->protection = 7;

    /* Read current file */
    file = qemu_fopen(filename, "rb");
    if (file) {
        /* Read nvram contents */
        qemu_get_buffer(file, s->contents, s->chip_size);
        qemu_fclose(file);
    }
    s->file = qemu_fopen(filename, "wb");
    if (s->file) {
        /* Write back contents, as 'wb' mode cleaned the file */
        qemu_put_buffer(s->file, s->contents, s->chip_size);
        qemu_fflush(s->file);
    }

    /* Read/write memory */
    mem_indexRW = cpu_register_io_memory(nvram_read, nvram_write, s);
    cpu_register_physical_memory(mem_base, s->chip_size, mem_indexRW);
    /* Read/write protected memory */
    mem_indexRP = cpu_register_io_memory(nvram_read, nvram_write_protected, s);
    cpu_register_physical_memory(mem_base + s->chip_size, s->chip_size, mem_indexRP);
    return s;
}
コード例 #5
0
ファイル: ppc4xx_pci.c プロジェクト: astarasikov/qemu
/* XXX Interrupt acknowledge cycles not supported. */
PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
                        target_phys_addr_t config_space,
                        target_phys_addr_t int_ack,
                        target_phys_addr_t special_cycle,
                        target_phys_addr_t registers)
{
    PPC4xxPCIState *controller;
    int index;
    static int ppc4xx_pci_id;
    uint8_t *pci_conf;

    controller = qemu_mallocz(sizeof(PPC4xxPCIState));

    controller->pci_state.bus = pci_register_bus(ppc4xx_pci_set_irq,
                                                 ppc4xx_pci_map_irq,
                                                 pci_irqs, 0, 4);

    controller->pci_dev = pci_register_device(controller->pci_state.bus,
                                              "host bridge", sizeof(PCIDevice),
                                              0, NULL, NULL);
    pci_conf = controller->pci_dev->config;
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_440GX);
    pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);

    /* CFGADDR */
    index = cpu_register_io_memory(0, pci4xx_cfgaddr_read,
                                   pci4xx_cfgaddr_write, controller);
    if (index < 0)
        goto free;
    cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);

    /* CFGDATA */
    index = cpu_register_io_memory(0, pci4xx_cfgdata_read,
                                   pci4xx_cfgdata_write,
                                   &controller->pci_state);
    if (index < 0)
        goto free;
    cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index);

    /* Internal registers */
    index = cpu_register_io_memory(0, pci_reg_read, pci_reg_write, controller);
    if (index < 0)
        goto free;
    cpu_register_physical_memory(registers, PCI_REG_SIZE, index);

    qemu_register_reset(ppc4xx_pci_reset, controller);

    /* XXX load/save code not tested. */
    register_savevm("ppc4xx_pci", ppc4xx_pci_id++, 1,
                    ppc4xx_pci_save, ppc4xx_pci_load, controller);

    return controller->pci_state.bus;

free:
    printf("%s error\n", __func__);
    qemu_free(controller);
    return NULL;
}
コード例 #6
0
ファイル: an5206.c プロジェクト: mithleshvrts/qemu-kvm-rhel6
static void an5206_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    CPUState *env;
    int kernel_size;
    uint64_t elf_entry;
    target_phys_addr_t entry;

    if (!cpu_model)
        cpu_model = "m5206";
    env = cpu_init(cpu_model);
    if (!env) {
        hw_error("Unable to find m68k CPU definition\n");
    }

    /* Initialize CPU registers.  */
    env->vbr = 0;
    /* TODO: allow changing MBAR and RAMBAR.  */
    env->mbar = AN5206_MBAR_ADDR | 1;
    env->rambar0 = AN5206_RAMBAR_ADDR | 1;

    /* DRAM at address zero */
    cpu_register_physical_memory(0, ram_size,
        qemu_ram_alloc(NULL, "an5206.ram", ram_size) | IO_MEM_RAM);

    /* Internal SRAM.  */
    cpu_register_physical_memory(AN5206_RAMBAR_ADDR, 512,
        qemu_ram_alloc(NULL, "an5206.sram", 512) | IO_MEM_RAM);

    mcf5206_init(AN5206_MBAR_ADDR, env);

    /* Load kernel.  */
    if (!kernel_filename) {
        fprintf(stderr, "Kernel image must be specified\n");
        exit(1);
    }

    kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL,
                           1, ELF_MACHINE, 0);
    entry = elf_entry;
    if (kernel_size < 0) {
        kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL);
    }
    if (kernel_size < 0) {
        kernel_size = load_image_targphys(kernel_filename, KERNEL_LOAD_ADDR,
                                          ram_size - KERNEL_LOAD_ADDR);
        entry = KERNEL_LOAD_ADDR;
    }
    if (kernel_size < 0) {
        fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
        exit(1);
    }

    env->pc = entry;
}
コード例 #7
0
ファイル: versatile_pci.c プロジェクト: 16aug/nvmeqemu
static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base)
{
    PCIVPBState *s = (PCIVPBState *)dev;
    /* Selfconfig area.  */
    cpu_register_physical_memory(base + 0x01000000, 0x1000000, s->mem_config);
    /* Normal config area.  */
    cpu_register_physical_memory(base + 0x02000000, 0x1000000, s->mem_config);

    if (s->realview) {
        /* IO memory area.  */
        isa_mmio_init(base + 0x03000000, 0x00100000);
    }
}
コード例 #8
0
ファイル: versatile_pci.c プロジェクト: AmesianX/winkvm
PCIBus *pci_vpb_init(void *pic, int irq, int realview)
{
    PCIBus *s;
    PCIDevice *d;
    int mem_config;
    uint32_t base;
    const char * name;

    pci_vpb_irq = irq;
    if (realview) {
        base = 0x60000000;
        name = "RealView EB PCI Controller";
    } else {
        base = 0x40000000;
        name = "Versatile/PB PCI Controller";
    }
    s = pci_register_bus(pci_vpb_set_irq, pci_vpb_map_irq, pic, 11 << 3, 4);
    /* ??? Register memory space.  */

    mem_config = cpu_register_io_memory(0, pci_vpb_config_read,
                                        pci_vpb_config_write, s);
    /* Selfconfig area.  */
    cpu_register_physical_memory(base + 0x01000000, 0x1000000, mem_config);
    /* Normal config area.  */
    cpu_register_physical_memory(base + 0x02000000, 0x1000000, mem_config);

    d = pci_register_device(s, name, sizeof(PCIDevice), -1, NULL, NULL);

    if (realview) {
        /* IO memory area.  */
        isa_mmio_init(base + 0x03000000, 0x00100000);
    }

    d->config[0x00] = 0xee; // vendor_id
    d->config[0x01] = 0x10;
    /* Both boards have the same device ID.  Oh well.  */
    d->config[0x02] = 0x00; // device_id
    d->config[0x03] = 0x03;
    d->config[0x04] = 0x00;
    d->config[0x05] = 0x00;
    d->config[0x06] = 0x20;
    d->config[0x07] = 0x02;
    d->config[0x08] = 0x00; // revision
    d->config[0x09] = 0x00; // programming i/f
    d->config[0x0A] = 0x40; // class_sub = pci host
    d->config[0x0B] = 0x0b; // class_base = PCI_bridge
    d->config[0x0D] = 0x10; // latency_timer

    return s;
}
コード例 #9
0
ファイル: r2d.c プロジェクト: AmesianX/winkvm
static void r2d_init(int ram_size, int vga_ram_size,
              const char *boot_device, DisplayState * ds,
	      const char *kernel_filename, const char *kernel_cmdline,
	      const char *initrd_filename, const char *cpu_model)
{
    CPUState *env;
    struct SH7750State *s;

    if (!cpu_model)
        cpu_model = "any";

    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find CPU definition\n");
        exit(1);
    }

    /* Allocate memory space */
    cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, 0);
    /* Register peripherals */
    s = sh7750_init(env);
    /* Todo: register on board registers */
    {
      int kernel_size;

      kernel_size = load_image(kernel_filename, phys_ram_base);

      if (kernel_size < 0) {
        fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
        exit(1);
      }

      env->pc = SDRAM_BASE | 0xa0000000; /* Start from P2 area */
    }
}
コード例 #10
0
ファイル: prep_pci.c プロジェクト: EgoIncarnate/qemu-rr
PCIBus *pci_prep_init(qemu_irq *pic)
{
    PREPPCIState *s;
    PCIDevice *d;
    int PPC_io_memory;

    s = qemu_mallocz(sizeof(PREPPCIState));
    s->bus = pci_register_bus(NULL, "pci",
                              prep_set_irq, prep_map_irq, pic, 0, 4);

    pci_host_conf_register_ioport(0xcf8, s);

    pci_host_data_register_ioport(0xcfc, s);

    PPC_io_memory = cpu_register_io_memory(PPC_PCIIO_read,
                                           PPC_PCIIO_write, s);
    cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);

    /* PCI host bridge */
    d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
                            sizeof(PCIDevice), 0, NULL, NULL);
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN);
    d->config[0x08] = 0x00; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer

    return s->bus;
}
コード例 #11
0
ファイル: dp8393x.c プロジェクト: mithleshvrts/qemu-kvm-rhel6
void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
                  qemu_irq irq, void* mem_opaque,
                  void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write))
{
    dp8393xState *s;

    qemu_check_nic_model(nd, "dp83932");

    s = qemu_mallocz(sizeof(dp8393xState));

    s->mem_opaque = mem_opaque;
    s->memory_rw = memory_rw;
    s->it_shift = it_shift;
    s->irq = irq;
    s->watchdog = qemu_new_timer(vm_clock, dp8393x_watchdog, s);
    s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */

    s->conf.macaddr = nd->macaddr;
    s->conf.vlan = nd->vlan;
    s->conf.peer = nd->netdev;

    s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, nd->model, nd->name, s);

    qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
    qemu_register_reset(nic_reset, s);
    nic_reset(s);

    s->mmio_index = cpu_register_io_memory(dp8393x_read, dp8393x_write, s);
    cpu_register_physical_memory(base, 0x40 << it_shift, s->mmio_index);
}
コード例 #12
0
ファイル: serialice-lua.c プロジェクト: coreboot/serialice
static int serialice_register_physical(lua_State * luastate)
{
    int n = lua_gettop(luastate);
    static uint8_t num = 1;
    uint32_t addr, size;
    ram_addr_t phys;
    char ram_name[16];

    if (n != 2) {
        fprintf(stderr,
                "ERROR: Not called as SerialICE_register_physical(<addr> <size>)\n");
        return 0;
    }

    addr = lua_tointeger(luastate, 1);
    size = lua_tointeger(luastate, 2);

    if (num > 99) {
        fprintf(stderr,"To much memory ranges registered\n");
        exit(1);
    }
    printf("Registering physical memory at 0x%08x (0x%08x bytes)\n", addr, size);
    sprintf(ram_name, "serialice_ram%u", num);
    phys = qemu_ram_alloc(NULL, ram_name, size);
    cpu_register_physical_memory(addr, size, phys);
    num++;
    return 0;
}
コード例 #13
0
static void mainstone_common_init(ram_addr_t ram_size,
                const char *kernel_filename,
                const char *kernel_cmdline, const char *initrd_filename,
                const char *cpu_model, enum mainstone_model_e model, int arm_id)
{
    uint32_t sector_len = 256 * 1024;
    target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
    PXA2xxState *cpu;
    qemu_irq *mst_irq;
    DriveInfo *dinfo;
    int i;

    if (!cpu_model)
        cpu_model = "pxa270-c5";

    /* Setup CPU & memory */
    cpu = pxa270_init(mainstone_binfo.ram_size, cpu_model);
    cpu_register_physical_memory(0, MAINSTONE_ROM,
                    qemu_ram_alloc(NULL, "mainstone.rom",
                                   MAINSTONE_ROM) | IO_MEM_ROM);

    /* Setup initial (reset) machine state */
    cpu->env->regs[15] = mainstone_binfo.loader_start;

    /* There are two 32MiB flash devices on the board */
    for (i = 0; i < 2; i ++) {
        dinfo = drive_get(IF_PFLASH, 0, i);
        if (!dinfo) {
            fprintf(stderr, "Two flash images must be given with the "
                    "'pflash' parameter\n");
            exit(1);
        }

        if (!pflash_cfi01_register(mainstone_flash_base[i],
                                qemu_ram_alloc(NULL, "mainstone.flash",
                                                  MAINSTONE_FLASH),
                                dinfo->bdrv, sector_len,
                                MAINSTONE_FLASH / sector_len, 4, 0, 0, 0, 0)) {
            fprintf(stderr, "qemu: Error registering flash memory.\n");
            exit(1);
        }
    }

    mst_irq = mst_irq_init(cpu, MST_FPGA_PHYS, PXA2XX_PIC_GPIO_0);

    /* setup keypad */
    printf("map addr %p\n", &map);
    pxa27x_register_keypad(cpu->kp, map, 0xe0);

    /* MMC/SD host */
    pxa2xx_mmci_handlers(cpu->mmc, NULL, mst_irq[MMC_IRQ]);

    smc91c111_init(&nd_table[0], MST_ETH_PHYS, mst_irq[ETHERNET_IRQ]);

    mainstone_binfo.kernel_filename = kernel_filename;
    mainstone_binfo.kernel_cmdline = kernel_cmdline;
    mainstone_binfo.initrd_filename = initrd_filename;
    mainstone_binfo.board_id = arm_id;
    arm_load_kernel(cpu->env, &mainstone_binfo);
}
コード例 #14
0
ファイル: pl031.c プロジェクト: AmesianX/winkvm
void pl031_init(uint32_t base, qemu_irq irq)
{
    int iomemtype;
    pl031_state *s;
    time_t ti;
    struct tm *tm;

    s = qemu_mallocz(sizeof(pl031_state));
    if (!s)
        cpu_abort(cpu_single_env, "pl031_init: Out of memory\n");

    iomemtype = cpu_register_io_memory(0, pl031_readfn, pl031_writefn, s);
    if (iomemtype == -1)
        cpu_abort(cpu_single_env, "pl031_init: Can't register I/O memory\n");

    cpu_register_physical_memory(base, 0x00001000, iomemtype);

    s->base = base;
    s->irq  = irq;
    /* ??? We assume vm_clock is zero at this point.  */
    time(&ti);
    if (rtc_utc)
        tm = gmtime(&ti);
    else
        tm = localtime(&ti);
    s->tick_offset = mktime(tm);

    s->timer = qemu_new_timer(vm_clock, pl031_interrupt, s);
}
コード例 #15
0
void *esp_init(target_phys_addr_t espaddr, int it_shift,
               espdma_memory_read_write dma_memory_read,
               espdma_memory_read_write dma_memory_write,
               void *dma_opaque, qemu_irq irq, qemu_irq *reset)
{
    ESPState *s;
    int esp_io_memory;

    s = qemu_mallocz(sizeof(ESPState));
    if (!s)
        return NULL;

    s->irq = irq;
    s->it_shift = it_shift;
    s->dma_memory_read = dma_memory_read;
    s->dma_memory_write = dma_memory_write;
    s->dma_opaque = dma_opaque;

    esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
    cpu_register_physical_memory(espaddr, ESP_REGS << it_shift, esp_io_memory);

    esp_reset(s);

    register_savevm("esp", espaddr, 3, esp_save, esp_load, s);
    qemu_register_reset(esp_reset, s);

    *reset = *qemu_allocate_irqs(parent_esp_reset, s, 1);

    return s;
}
コード例 #16
0
void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
               qemu_irq **parent_irq)
{
    unsigned int i;
    int sbi_io_memory;
    SBIState *s;

    s = qemu_mallocz(sizeof(SBIState));
    if (!s)
        return NULL;

    for (i = 0; i < MAX_CPUS; i++) {
        s->cpu_irqs[i] = parent_irq[i];
    }

    sbi_io_memory = cpu_register_io_memory(0, sbi_mem_read, sbi_mem_write, s);
    cpu_register_physical_memory(addr, SBI_SIZE, sbi_io_memory);

    register_savevm("sbi", addr, 1, sbi_save, sbi_load, s);
    qemu_register_reset(sbi_reset, s);
    *irq = qemu_allocate_irqs(sbi_set_irq, s, 32);
    *cpu_irq = qemu_allocate_irqs(sbi_set_timer_irq_cpu, s, MAX_CPUS);
    sbi_reset(s);

    return s;
}
コード例 #17
0
ファイル: sh_pci.c プロジェクト: SJTU-IPADS/COREMU-QEMU
static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
{
    SHPCIC *pcic = p;
    switch(addr) {
    case 0 ... 0xfc:
        cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val);
        break;
    case 0x1c0:
        pcic->par = val;
        break;
    case 0x1c4:
        pcic->mbr = val & 0xff000001;
        break;
    case 0x1c8:
        if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) {
            cpu_register_physical_memory(pcic->iobr & 0xfffc0000, 0x40000,
                                         IO_MEM_UNASSIGNED);
            pcic->iobr = val & 0xfffc0001;
            isa_mmio_init(pcic->iobr & 0xfffc0000, 0x40000);
        }
        break;
    case 0x220:
        pci_data_write(pcic->bus, pcic->par, val, 4);
        break;
    }
}
コード例 #18
0
ファイル: pxa2xx_timer.c プロジェクト: hackndev/qemu
static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
                qemu_irq *irqs)
{
    int i;
    int iomemtype;
    pxa2xx_timer_info *s;

    s = (pxa2xx_timer_info *) qemu_mallocz(sizeof(pxa2xx_timer_info));
    s->base = base;
    s->irq_enabled = 0;
    s->oldclock = 0;
    s->clock = 0;
    s->lastload = qemu_get_clock(vm_clock);
    s->reset3 = 0;

    for (i = 0; i < 4; i ++) {
        s->timer[i].value = 0;
        s->timer[i].irq = irqs[i];
        s->timer[i].info = s;
        s->timer[i].num = i;
        s->timer[i].level = 0;
        s->timer[i].qtimer = qemu_new_timer(vm_clock,
                        pxa2xx_timer_tick, &s->timer[i]);
    }

    iomemtype = cpu_register_io_memory(0, pxa2xx_timer_readfn,
                    pxa2xx_timer_writefn, s);
    cpu_register_physical_memory(base, 0x00001000, iomemtype);

    register_savevm("pxa2xx_timer", 0, 0,
                    pxa2xx_timer_save, pxa2xx_timer_load, s);

    return s;
}
コード例 #19
0
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq)
{
    RTCState *s;
    int io_memory;

    s = qemu_mallocz(sizeof(RTCState));
    if (!s)
        return NULL;

    s->irq = irq;
    s->cmos_data[RTC_REG_A] = 0x26;
    s->cmos_data[RTC_REG_B] = 0x02;
    s->cmos_data[RTC_REG_C] = 0x00;
    s->cmos_data[RTC_REG_D] = 0x80;

    rtc_set_date_from_host(s);

    s->periodic_timer = qemu_new_timer(vm_clock,
                                       rtc_periodic_timer, s);
    s->second_timer = qemu_new_timer(vm_clock,
                                     rtc_update_second, s);
    s->second_timer2 = qemu_new_timer(vm_clock,
                                      rtc_update_second2, s);

    s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
    qemu_mod_timer(s->second_timer2, s->next_second_time);

    io_memory = cpu_register_io_memory(0, rtc_mm_read, rtc_mm_write, s);
    cpu_register_physical_memory(base, 2 << it_shift, io_memory);

    register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
    return s;
}
コード例 #20
0
ファイル: slavio_serial.c プロジェクト: tumf/xen-3.3.1
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
                               int disabled)
{
    int slavio_serial_io_memory, i;
    SerialState *s;

    s = qemu_mallocz(sizeof(SerialState));
    if (!s)
        return;
    for (i = 0; i < 2; i++) {
        s->chn[i].irq = irq;
        s->chn[i].chn = 1 - i;
        s->chn[i].chr = NULL;
    }
    s->chn[0].otherchn = &s->chn[1];
    s->chn[1].otherchn = &s->chn[0];
    s->chn[0].type = mouse;
    s->chn[1].type = kbd;
    s->chn[0].disabled = disabled;
    s->chn[1].disabled = disabled;

    slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read,
                                                     slavio_serial_mem_write,
                                                     s);
    cpu_register_physical_memory(base, SERIAL_SIZE, slavio_serial_io_memory);

    qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0,
                                 "QEMU Sun Mouse");
    qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]);
    register_savevm("slavio_serial_mouse", base, 2, slavio_serial_save,
                    slavio_serial_load, s);
    qemu_register_reset(slavio_serial_reset, s);
    slavio_serial_reset(s);
}
コード例 #21
0
ファイル: etraxfs_dma.c プロジェクト: tumf/xen-3.3.1
void *etraxfs_dmac_init(CPUState *env, 
			target_phys_addr_t base, int nr_channels)
{
	struct fs_dma_ctrl *ctrl = NULL;
	int i;

	ctrl = qemu_mallocz(sizeof *ctrl);
	if (!ctrl)
		return NULL;

	ctrl->base = base;
	ctrl->env = env;
	ctrl->nr_channels = nr_channels;
	ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);
	if (!ctrl->channels)
		goto err;

	for (i = 0; i < nr_channels; i++)
	{
		ctrl->channels[i].regmap = cpu_register_io_memory(0,
								  dma_read, 
								  dma_write, 
								  ctrl);
		cpu_register_physical_memory (base + i * 0x2000,
					      sizeof ctrl->channels[i].regs, 
					      ctrl->channels[i].regmap);
	}

	return ctrl;
  err:
	qemu_free(ctrl->channels);
	qemu_free(ctrl);
	return NULL;
}
コード例 #22
0
ファイル: s3c2410_spi.c プロジェクト: Mwyann/x49gp
static int
s3c2410_spi_init(x49gp_module_t *module)
{
    s3c2410_spi_t *spi;
    int iotype;

#ifdef DEBUG_X49GP_MODULES
    printf("%s: %s:%u\n", module->name, __FUNCTION__, __LINE__);
#endif

    spi = malloc(sizeof(s3c2410_spi_t));
    if (NULL == spi) {
        fprintf(stderr, "%s:%u: Out of memory\n",
                __FUNCTION__, __LINE__);
        return -ENOMEM;
    }
    if (s3c2410_spi_data_init(spi)) {
        free(spi);
        return -ENOMEM;
    }

    module->user_data = spi;
    spi->x49gp = module->x49gp;

#ifdef QEMU_OLD
    iotype = cpu_register_io_memory(0, s3c2410_spi_readfn,
                                    s3c2410_spi_writefn, spi);
#else
    iotype = cpu_register_io_memory(s3c2410_spi_readfn,
                                    s3c2410_spi_writefn, spi);
#endif
    printf("%s: iotype %08x\n", __FUNCTION__, iotype);
    cpu_register_physical_memory(S3C2410_SPI_BASE, S3C2410_MAP_SIZE, iotype);
    return 0;
}
コード例 #23
0
ファイル: pcie_host.c プロジェクト: 16aug/nvmeqemu
void pcie_host_mmcfg_unmap(PCIExpressHost *e)
{
    if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) {
        cpu_register_physical_memory(e->base_addr, e->size, IO_MEM_UNASSIGNED);
        e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
    }
}
コード例 #24
0
ファイル: slavio_serial.c プロジェクト: AmesianX/winkvm
void slavio_serial_ms_kbd_init(int base, int irq)
{
    int slavio_serial_io_memory, i;
    SerialState *s;

    s = qemu_mallocz(sizeof(SerialState));
    if (!s)
        return;
    for (i = 0; i < 2; i++) {
	s->chn[i].irq = irq;
	s->chn[i].chn = 1 - i;
	s->chn[i].chr = NULL;
    }
    s->chn[0].otherchn = &s->chn[1];
    s->chn[1].otherchn = &s->chn[0];
    s->chn[0].type = mouse;
    s->chn[1].type = kbd;

    slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read, slavio_serial_mem_write, s);
    cpu_register_physical_memory(base, SERIAL_MAXADDR, slavio_serial_io_memory);

    qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0, "QEMU Sun Mouse");
    qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]);
    qemu_register_reset(slavio_serial_reset, s);
    slavio_serial_reset(s);
}
コード例 #25
0
ファイル: slavio_serial.c プロジェクト: AmesianX/winkvm
SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, CharDriverState *chr2)
{
    int slavio_serial_io_memory, i;
    SerialState *s;

    s = qemu_mallocz(sizeof(SerialState));
    if (!s)
        return NULL;

    slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read, slavio_serial_mem_write, s);
    cpu_register_physical_memory(base, SERIAL_MAXADDR, slavio_serial_io_memory);

    s->chn[0].chr = chr1;
    s->chn[1].chr = chr2;

    for (i = 0; i < 2; i++) {
	s->chn[i].irq = irq;
	s->chn[i].chn = 1 - i;
	s->chn[i].type = ser;
	if (s->chn[i].chr) {
	    qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive,
                                  serial_receive1, serial_event, &s->chn[i]);
	}
    }
    s->chn[0].otherchn = &s->chn[1];
    s->chn[1].otherchn = &s->chn[0];
    register_savevm("slavio_serial", base, 2, slavio_serial_save, slavio_serial_load, s);
    qemu_register_reset(slavio_serial_reset, s);
    slavio_serial_reset(s);
    return s;
}
コード例 #26
0
void *etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr)
{
	struct etraxfs_dma_client *dma = NULL;	
	struct fs_eth *eth = NULL;

	qemu_check_nic_model(nd, "fseth");

	dma = qemu_mallocz(sizeof *dma * 2);
	eth = qemu_mallocz(sizeof *eth);

	dma[0].client.push = eth_tx_push;
	dma[0].client.opaque = eth;
	dma[1].client.opaque = eth;
	dma[1].client.pull = NULL;

	eth->dma_out = dma;
	eth->dma_in = dma + 1;

	/* Connect the phy.  */
	eth->phyaddr = phyaddr & 0x1f;
	tdk_init(&eth->phy);
	mdio_attach(&eth->mdio_bus, &eth->phy, eth->phyaddr);

	eth->ethregs = cpu_register_io_memory(eth_read, eth_write, eth);
	cpu_register_physical_memory (base, 0x5c, eth->ethregs);

	memcpy(eth->conf.macaddr.a, nd->macaddr, sizeof(nd->macaddr));
	eth->conf.vlan = nd->vlan;
	eth->conf.peer = nd->netdev;

	eth->nic = qemu_new_nic(&net_etraxfs_info, &eth->conf,
				nd->model, nd->name, eth);

	return dma;
}
コード例 #27
0
ファイル: r2d.c プロジェクト: agocke/qemu
static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
              const char *boot_device,
	      const char *kernel_filename, const char *kernel_cmdline,
	      const char *initrd_filename, const char *cpu_model)
{
    CPUState *env;
    struct SH7750State *s;
    ram_addr_t sdram_addr, sm501_vga_ram_addr;
    qemu_irq *irq;
    PCIBus *pci;
    int i;

    if (!cpu_model)
        cpu_model = "SH7751R";

    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find CPU definition\n");
        exit(1);
    }

    /* Allocate memory space */
    sdram_addr = qemu_ram_alloc(SDRAM_SIZE);
    cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
    /* Register peripherals */
    s = sh7750_init(env);
    irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
    pci = sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4);

    sm501_vga_ram_addr = qemu_ram_alloc(SM501_VRAM_SIZE);
    sm501_init(0x10000000, sm501_vga_ram_addr, SM501_VRAM_SIZE,
	       serial_hds[2]);

    /* onboard CF (True IDE mode, Master only). */
    mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
        drives_table[drive_get_index(IF_IDE, 0, 0)].bdrv, NULL);

    /* NIC: rtl8139 on-board, and 2 slots. */
    pci_nic_init(pci, &nd_table[0], 2 << 3, "rtl8139");
    for (i = 1; i < nb_nics; i++)
        pci_nic_init(pci, &nd_table[i], -1, "ne2k_pci");

    /* Todo: register on board registers */
    {
      int kernel_size;
      /* initialization which should be done by firmware */
      stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
      stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */

      kernel_size = load_image(kernel_filename, phys_ram_base);

      if (kernel_size < 0) {
        fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
        exit(1);
      }

      env->pc = SDRAM_BASE | 0xa0000000; /* Start from P2 area */
    }
}
コード例 #28
0
ファイル: isa_mmio.c プロジェクト: AmesianX/winkvm
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size)
{
    if (!isa_mmio_iomemtype) {
        isa_mmio_iomemtype = cpu_register_io_memory(0, isa_mmio_read,
                                                    isa_mmio_write, NULL);
    }
    cpu_register_physical_memory(base, size, isa_mmio_iomemtype);
}
コード例 #29
0
ファイル: versatile_pci.c プロジェクト: evirt/qemu-gl
static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base)
{
    PCIVPBState *s = (PCIVPBState *)dev;
    /* Selfconfig area.  */
    cpu_register_physical_memory(base + 0x01000000, 0x1000000, s->mem_config);
    /* Normal config area.  */
    cpu_register_physical_memory(base + 0x02000000, 0x1000000, s->mem_config);

    if (s->realview) {
        /* IO memory area.  */
#ifdef TARGET_WORDS_BIGENDIAN
        isa_mmio_init(base + 0x03000000, 0x00100000, 1);
#else
        isa_mmio_init(base + 0x03000000, 0x00100000, 0);
#endif
    }
}
コード例 #30
0
ファイル: pxa2xx_lcd.c プロジェクト: ESOS-Lab/VSSIM
PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq)
{
    int iomemtype;
    PXA2xxLCDState *s;

    s = (PXA2xxLCDState *) qemu_mallocz(sizeof(PXA2xxLCDState));
    s->invalidated = 1;
    s->irq = irq;

    pxa2xx_lcdc_orientation(s, graphic_rotate);

    iomemtype = cpu_register_io_memory(pxa2xx_lcdc_readfn,
                    pxa2xx_lcdc_writefn, s);
    cpu_register_physical_memory(base, 0x00100000, iomemtype);

    s->ds = graphic_console_init(pxa2xx_update_display,
                                 pxa2xx_invalidate_display,
                                 pxa2xx_screen_dump, NULL, s);

    switch (ds_get_bits_per_pixel(s->ds)) {
    case 0:
        s->dest_width = 0;
        break;
    case 8:
        s->line_fn[0] = pxa2xx_draw_fn_8;
        s->line_fn[1] = pxa2xx_draw_fn_8t;
        s->dest_width = 1;
        break;
    case 15:
        s->line_fn[0] = pxa2xx_draw_fn_15;
        s->line_fn[1] = pxa2xx_draw_fn_15t;
        s->dest_width = 2;
        break;
    case 16:
        s->line_fn[0] = pxa2xx_draw_fn_16;
        s->line_fn[1] = pxa2xx_draw_fn_16t;
        s->dest_width = 2;
        break;
    case 24:
        s->line_fn[0] = pxa2xx_draw_fn_24;
        s->line_fn[1] = pxa2xx_draw_fn_24t;
        s->dest_width = 3;
        break;
    case 32:
        s->line_fn[0] = pxa2xx_draw_fn_32;
        s->line_fn[1] = pxa2xx_draw_fn_32t;
        s->dest_width = 4;
        break;
    default:
        fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
        exit(1);
    }

    register_savevm("pxa2xx_lcdc", 0, 0,
                    pxa2xx_lcdc_save, pxa2xx_lcdc_load, s);

    return s;
}