//========================================================================== // This function is called from the generic ADC package to enable the // channel in response to a CYG_IO_SET_CONFIG_ADC_DISABLE config operation. // It should take any steps needed to stop the channel generating samples. //========================================================================== static void at91_adc_disable(cyg_adc_channel *chan) { at91_adc_info *info = chan->device->dev_priv; cyg_uint32 sr; info->chan_mask &= ~ AT91_ADC_CHER_CHx(chan->channel); // Disable the channel HAL_WRITE_UINT32((info->adc_base + AT91_ADC_CHDR), \ AT91_ADC_CHER_CHx(chan->channel)); // // If no channel is enabled the we disable interrupts now // if (!info->chan_mask) { cyg_drv_interrupt_mask(info->timer_vector); // Clear interrupt HAL_READ_UINT32(info->tc_base+AT91_TC_SR, sr); // Disable timer interrupt HAL_WRITE_UINT32(info->tc_base+AT91_TC_IDR, AT91_TC_IER_CPC); // Disable the clock HAL_WRITE_UINT32(info->tc_base+AT91_TC_CCR, AT91_TC_CCR_CLKDIS); } }
static cyg_uint32 netxeth_ISR(cyg_vector_t vector, cyg_addrword_t data) { cyg_drv_interrupt_mask(vector); cyg_drv_interrupt_acknowledge(vector); return CYG_ISR_HANDLED | CYG_ISR_CALL_DSR; }
// Disable the transmitter on the device static void edb7xxx_serial_stop_xmit(serial_channel *chan) { edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv; cyg_drv_interrupt_mask(edb7xxx_chan->tx_int_num); edb7xxx_chan->tx_enabled = false; }
// This ISR is called when the ethernet interrupt occurs static int quicc_eth_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs) { cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_CPM_SCC1); cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_CPM_SCC1); return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Run the DSR }
__externC CYG_WORD32 cyg_hal_cpu_message_dsr(CYG_WORD32 vector, CYG_ADDRWORD data) { struct smp_msg_t *m = &smp_msg[HAL_SMP_CPU_THIS()]; CYG_WORD32 reschedule; #ifdef CYGSEM_KERNEL_SCHED_TIMESLICE CYG_WORD32 timeslice; #endif cyg_drv_interrupt_mask(vector); HAL_SPINLOCK_SPIN(m->lock); reschedule = m->reschedule; #ifdef CYGSEM_KERNEL_SCHED_TIMESLICE timeslice = m->timeslice; m->reschedule = m->timeslice = false; #else m->reschedule = false; #endif HAL_SPINLOCK_CLEAR(m->lock); cyg_drv_interrupt_unmask(vector); if (reschedule) { cyg_scheduler_set_need_reschedule(); } #ifdef CYGSEM_KERNEL_SCHED_TIMESLICE if (timeslice) { cyg_scheduler_timeslice_cpu(); } #endif return 0; }
// Serial I/O - low level interrupt handler (ISR) static cyg_uint32 vrc437x_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) { cyg_drv_interrupt_mask(VRC437X_SCC_INT); cyg_drv_interrupt_acknowledge(VRC437X_SCC_INT); return CYG_ISR_CALL_DSR; // Cause DSR to be run }
static void mn10300_serial_stop_xmit(serial_channel *chan) { #ifndef CYGPKG_IO_SERIAL_MN10300_POLLED_MODE mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; cyg_uint16 cr; cyg_uint16 sr; // Wait until the transmitter has actually stopped before turning it off. do { sr = mn10300_read_sr( mn10300_chan ); } while( sr & SR_TXF ); HAL_READ_UINT16( mn10300_chan->base+SERIAL_CTR, cr ); DISABLE_TRANSMIT_INTERRUPT(mn10300_chan); HAL_WRITE_UINT16( mn10300_chan->base+SERIAL_CTR, cr ); cyg_drv_interrupt_mask(mn10300_chan->tx_int); #endif }
// Function to initialize the device. Called at bootstrap time. static bool edb7xxx_serial_init(struct cyg_devtab_entry *tab) { serial_channel *chan = (serial_channel *)tab->priv; edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv; #ifdef CYGDBG_IO_INIT diag_printf("EDB7XXX SERIAL init - dev: %x.%d\n", edb7xxx_chan->control, edb7xxx_chan->tx_int_num); #endif (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices if (chan->out_cbuf.len != 0) { cyg_drv_interrupt_create(edb7xxx_chan->tx_int_num, 99, // Priority - unused (cyg_addrword_t)chan, // Data item passed to interrupt handler edb7xxx_serial_tx_ISR, edb7xxx_serial_tx_DSR, &edb7xxx_chan->serial_tx_interrupt_handle, &edb7xxx_chan->serial_tx_interrupt); cyg_drv_interrupt_attach(edb7xxx_chan->serial_tx_interrupt_handle); cyg_drv_interrupt_mask(edb7xxx_chan->tx_int_num); edb7xxx_chan->tx_enabled = false; } if (chan->in_cbuf.len != 0) { cyg_drv_interrupt_create(edb7xxx_chan->rx_int_num, 99, // Priority - unused (cyg_addrword_t)chan, // Data item passed to interrupt handler edb7xxx_serial_rx_ISR, edb7xxx_serial_rx_DSR, &edb7xxx_chan->serial_rx_interrupt_handle, &edb7xxx_chan->serial_rx_interrupt); cyg_drv_interrupt_attach(edb7xxx_chan->serial_rx_interrupt_handle); cyg_drv_interrupt_unmask(edb7xxx_chan->rx_int_num); } edb7xxx_serial_config_port(chan, &chan->config, true); return true; }
// Disable the transmitter on the device (nope, remains in use by hal_diag) static void ebsa285_serial_stop_xmit(serial_channel *chan) { ebsa285_serial_info *ebsa285_chan = (ebsa285_serial_info *)chan->dev_priv; cyg_drv_interrupt_mask(ebsa285_chan->tx.int_num); ebsa285_chan->tx_active = 0; }
// Serial I/O - low level interrupt handler (ISR) static cyg_uint32 mpc8xxx_sxx_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) { serial_channel *chan = (serial_channel *)data; mpc8xxx_sxx_serial_info *smc_chan = (mpc8xxx_sxx_serial_info *)chan->dev_priv; cyg_drv_interrupt_mask(smc_chan->int_num); return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Cause DSR to be run }
static cyg_uint32 phy_isr(cyg_vector_t vector, cyg_addrword_t data) { cyg_drv_interrupt_mask(vector); cyg_drv_interrupt_acknowledge(vector); // os_printf("PHY ISR on interrupt %d", vector); //just call the DSR return (CYG_ISR_CALL_DSR | CYG_ISR_HANDLED); }
// This ISR is called when the ethernet interrupt occurs static int tsec_eth_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs) { cyg_drv_interrupt_mask(vector); cyg_drv_interrupt_acknowledge(vector); // os_printf("TSEC ISR on interrupt %d", vector); return (CYG_ISR_HANDLED | CYG_ISR_CALL_DSR); // Run the DSR }
// Serial I/O - low level Ms interrupt handler (ISR) static cyg_uint32 edb7xxx_serial_ms_ISR(cyg_vector_t vector, cyg_addrword_t data) { serial_channel *chan = (serial_channel *)data; edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv; cyg_drv_interrupt_mask(edb7xxx_chan->ms_int_num); cyg_drv_interrupt_acknowledge(edb7xxx_chan->ms_int_num); return CYG_ISR_CALL_DSR; // Cause DSR to be run }
static int s3esk_eth_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs) { struct eth_drv_sc *sc = (struct eth_drv_sc *)data; struct s3esk_eth_info *qi = (struct s3esk_eth_info *)sc->driver_private; cyg_drv_interrupt_mask(qi->int_vector); return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Run the DSR }
//-------------------------------------- // Disable the transmitter on the device //-------------------------------------- static void mpc555_serial_stop_xmit(serial_channel * chan) { mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; cyg_drv_dsr_lock(); mpc555_chan->tx_interrupt_enable = false; cyg_drv_interrupt_mask(mpc555_chan->tx_interrupt_num); cyg_drv_dsr_unlock(); }
// Serial I/O - low level interrupt handler (ISR) static cyg_uint32 smdk2410_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) { serial_channel *chan = (serial_channel *)data; smdk2410_serial_info *smdk2410_chan = (smdk2410_serial_info *)chan->dev_priv; cyg_drv_interrupt_mask(smdk2410_chan->int_num); cyg_drv_interrupt_acknowledge(smdk2410_chan->int_num); return CYG_ISR_CALL_DSR; // Cause DSR to be run }
// Serial I/O - low level interrupt handler (ISR) static cyg_uint32 zynq_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) { serial_channel *chan = (serial_channel *)data; zynq_serial_info *zynq_chan = (zynq_serial_info *)chan->dev_priv; cyg_drv_interrupt_mask(zynq_chan->int_num); cyg_drv_interrupt_acknowledge(zynq_chan->int_num); return (CYG_ISR_HANDLED | CYG_ISR_CALL_DSR); // Cause DSR to be run }
//---------------------------------------- // The low level receive interrupt handler //---------------------------------------- static cyg_uint32 mpc555_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) { serial_channel * chan = (serial_channel *)data; mpc555_serial_info * mpc555_chan = (mpc555_serial_info *)chan->dev_priv; cyg_drv_interrupt_mask(mpc555_chan->rx_interrupt_num); cyg_drv_interrupt_acknowledge(mpc555_chan->rx_interrupt_num); return CYG_ISR_CALL_DSR; // cause the DSR to run }
static cyg_uint32 mn10300_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data) { serial_channel *chan = (serial_channel *)data; mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; cyg_drv_interrupt_mask(mn10300_chan->tx_int); cyg_drv_interrupt_acknowledge(mn10300_chan->tx_int); return CYG_ISR_CALL_DSR; // Cause DSR to be run }
void hal_stm32_dma_delete( hal_stm32_dma_stream *stream ) { dma_diag("ctlr %08x stream %d chan %d\n", stream->ctlr, stream->stream, CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc) ); // Clear CCR, disables stream HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CCR(stream->stream), 0 ); // Mask, detach and delete interrupt object cyg_drv_interrupt_mask( CYGHWR_HAL_STM32_DMA_INTERRUPT(stream->desc) ); cyg_drv_interrupt_detach( stream->handle ); cyg_drv_interrupt_delete( stream->handle ); }
HRESULT avsTestStartCapture (int time) { avsLogItems = 0; uint32 timeEnd, timeCur, wasBigger, isBigger; //timerRegWrite(TIMER2_CTRL_REG, 4); //timerRegWrite(TIMER2_LOAD_CNT, 0xffffffff); //timerRegWrite(TIMER2_CTRL_REG, 5); InstallAvsHandler (); timeCur = *((volatile int *)(LLCBASE+CY_TMR_REG_DP)); timeEnd = timeCur + time*0x02000000; wasBigger = (timeEnd > timeCur) ? 1 : 0; cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_AVS0); cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_AVS1); cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_AVS2); //avsRegWrite(APBA_PARTITION4_FLUSH,1); while (1) { if (avsLogItems >= AVS_LOG_SIZE) break; timeCur = *((volatile int *)(LLCBASE+CY_TMR_REG_DP)); isBigger = (timeEnd > timeCur) ? 1 : 0; if (wasBigger != isBigger) break; TCTaskYield(); } cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_AVS0); cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_AVS1); cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_AVS2); sysDebugPrintf("Captured %i items\n\r",avsLogItems); return NO_ERROR; }
// This ISR is called when the ethernet interrupt occurs static int saa9730_isr(cyg_vector_t vector, cyg_addrword_t data) { struct saa9730_priv_data *spd = (struct saa9730_priv_data *)data; unsigned long __base = spd->base; #ifndef CYGPKG_REDBOOT SAA9730_EVM_IER_SW &= ~(SAA9730_EVM_LAN_INT|SAA9730_EVM_MASTER); SAA9730_EVM_ISR = SAA9730_EVM_LAN_INT; cyg_drv_interrupt_mask(vector); #endif #ifdef DEBUG db_printf("saa9730_isr\n"); #endif return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Run the DSR }
static cyg_uint32 spi_at91_ISR(cyg_vector_t vector, cyg_addrword_t data) { cyg_uint32 stat; // Read the status register and disable // the SPI int events that have occoured HAL_READ_UINT32(AT91_SPI+AT91_SPI_SR, stat); HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_IDR, stat); cyg_drv_interrupt_mask(vector); cyg_drv_interrupt_acknowledge(vector); return CYG_ISR_CALL_DSR; }
__externC CYG_WORD32 cyg_hal_cpu_message_isr(CYG_WORD32 vector, CYG_ADDRWORD data) { struct smp_msg_t *m; m = &smp_msg[HAL_SMP_CPU_THIS()]; cyg_drv_interrupt_mask(vector); HAL_SPINLOCK_SPIN( m->lock ); cyg_drv_interrupt_acknowledge(vector); CYG_WORD32 ret = 1; if (m->reschedule) m->reschedule_count++; if (m->timeslice) m->timeslice_count++; if (m->reschedule || m->timeslice) ret |= 2; /* Call DSR */ while (m->head != m->tail) { CYG_WORD32 msg = m->msgs[m->head]; switch (msg & HAL_SMP_MESSAGE_TYPE) { case HAL_SMP_MESSAGE_RESCHEDULE: ret |= 2; /* Call DSR */ break; case HAL_SMP_MESSAGE_MASK: case HAL_SMP_MESSAGE_UNMASK: case HAL_SMP_MESSAGE_REVECTOR: break; } /* Update the head pointer after handling the message, so that * the wait in cyg_hal_cpu_message() completes after the action * requested. */ m->head = (m->head + 1) & (SMP_MSGBUF_SIZE-1); } HAL_SPINLOCK_CLEAR(m->lock); cyg_drv_interrupt_unmask(vector); return ret; }
// This ISR is called when the ethernet interrupt occurs static int ppc405_eth_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs) { struct eth_drv_sc *sc = (struct eth_drv_sc *)data; struct ppc405_eth_info *qi = (struct ppc405_eth_info *)sc->driver_private; cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_MAL_SERR); cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_MAL_TX_EOB); cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_MAL_RX_EOB); cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_MAL_TX_DE); cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_MAL_RX_DE); cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_EMAC0); qi->ints = vector; return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Run the DSR }
bool mn10300_serial_init(struct cyg_devtab_entry *tab) { serial_channel *chan = (serial_channel *)tab->priv; mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices #ifndef CYGPKG_IO_SERIAL_MN10300_POLLED_MODE if (chan->out_cbuf.len != 0) { // Install and enable the receive interrupt cyg_drv_interrupt_create(mn10300_chan->rx_int, 4, // Priority - what goes here? (cyg_addrword_t)chan, // Data item passed to interrupt handler mn10300_serial_rx_ISR, mn10300_serial_rx_DSR, &mn10300_chan->rx_interrupt_handle, &mn10300_chan->rx_interrupt); cyg_drv_interrupt_attach(mn10300_chan->rx_interrupt_handle); cyg_drv_interrupt_unmask(mn10300_chan->rx_int); // Install and enable the transmit interrupt cyg_drv_interrupt_create(mn10300_chan->tx_int, 4, // Priority - what goes here? (cyg_addrword_t)chan, // Data item passed to interrupt handler mn10300_serial_tx_ISR, mn10300_serial_tx_DSR, &mn10300_chan->tx_interrupt_handle, &mn10300_chan->tx_interrupt); cyg_drv_interrupt_attach(mn10300_chan->tx_interrupt_handle); cyg_drv_interrupt_mask(mn10300_chan->tx_int); } #endif mn10300_serial_config_port(chan, &chan->config, true); return true; }
// Shut down hardware void netxeth_stop(struct eth_drv_sc *sc) { PNETX_ETH_PORT_INFO ptPortInfo = sc->driver_private; cyg_uint32 uiPhyData; cyg_drv_interrupt_mask(ptPortInfo->ulInterrupt); xc_stop(ptPortInfo->ulPort); //Put Phy into Power down mode PhyMDIO(s_abPhyAddresses[ptPortInfo->ulPort], MDIO_READ, DRV_CB12_CONTROL, &uiPhyData); uiPhyData |= DRV_CB12_CONTROL_POWER_DOWN; PhyMDIO(s_abPhyAddresses[ptPortInfo->ulPort], MDIO_WRITE, DRV_CB12_CONTROL, &uiPhyData); /* Disable all interrupts */ ptPortInfo->pulxPECBase[(REL_Adr_dram_start + REL_Adr_ETHMAC_INTERRUPTS_ENABLE_IND_HI) / sizeof(cyg_uint32)] = 0; ptPortInfo->pulxPECBase[(REL_Adr_dram_start + REL_Adr_ETHMAC_INTERRUPTS_ENABLE_IND_LO) / sizeof(cyg_uint32)] = 0; ptPortInfo->pulxPECBase[(REL_Adr_dram_start + REL_Adr_ETHMAC_INTERRUPTS_ENABLE_CON_HI) / sizeof(cyg_uint32)] = 0; ptPortInfo->pulxPECBase[(REL_Adr_dram_start + REL_Adr_ETHMAC_INTERRUPTS_ENABLE_CON_LO) / sizeof(cyg_uint32)] = 0; //empty all fifo's from this channel s_ptFifoArea->ulPFifoReset |= 0xFF << (ptPortInfo->ulPort * 8); s_ptFifoArea->ulPFifoReset &= ~(0xFF << (ptPortInfo->ulPort * 8)); }
// This ISR is called when the card interrupt occurs static int cf_irq_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs) { cyg_drv_interrupt_mask(SA1110_CF_IRQ); return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Run the DSR }
// This ISR is called when the touch panel interrupt occurs static int lcd_panel_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs) { cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_EINT2); return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Run the DSR }
//========================================================================== // This function is called from the device IO infrastructure to initialize // the device. It should perform any work needed to start up the device, // short of actually starting the generation of samples. This function will // be called for each channel, so if there is initialization that only needs // to be done once, such as creating and interrupt object, then care should // be taken to do this. This function should also call cyg_adc_device_init() // to initialize the generic parts of the driver. //========================================================================== static bool at91_adc_init(struct cyg_devtab_entry *tab) { cyg_adc_channel *chan = (cyg_adc_channel *)tab->priv; cyg_adc_device *device = chan->device; at91_adc_info *info = device->dev_priv; cyg_uint32 regval; if (!info->int_handle) { cyg_drv_interrupt_create(info->timer_vector, info->timer_intprio, (cyg_addrword_t)device, &at91_adc_isr, &at91_adc_dsr, &(info->int_handle), &(info->int_data)); cyg_drv_interrupt_attach(info->int_handle); cyg_drv_interrupt_mask(info->timer_vector); // Reset ADC HAL_WRITE_UINT32((info->adc_base + AT91_ADC_CR), AT91_ADC_CR_SWRST); // Disable counter interrupts HAL_WRITE_UINT32(info->tc_base+AT91_TC_CCR, AT91_TC_CCR_CLKDIS); HAL_WRITE_UINT32(info->tc_base+AT91_TC_IDR, 0xffffffff); // Clear status bit HAL_READ_UINT32(info->tc_base + AT91_TC_SR, regval); // Enable peripheral clocks for TC HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_PCER, \ ((AT91_PMC_PCER_TC0) << info->timer_id)); // // Disable all interrupts, all channels // HAL_WRITE_UINT32((info->adc_base + AT91_ADC_CHDR), \ AT91_ADC_CHER_CH0 |\ AT91_ADC_CHER_CH1 |\ AT91_ADC_CHER_CH2 |\ AT91_ADC_CHER_CH3 |\ AT91_ADC_CHER_CH4 |\ AT91_ADC_CHER_CH5 |\ AT91_ADC_CHER_CH6 |\ AT91_ADC_CHER_CH7); HAL_WRITE_UINT32((info->adc_base + AT91_ADC_IDR), \ AT91_ADC_CHER_CH0 |\ AT91_ADC_CHER_CH1 |\ AT91_ADC_CHER_CH2 |\ AT91_ADC_CHER_CH3 |\ AT91_ADC_CHER_CH4 |\ AT91_ADC_CHER_CH5 |\ AT91_ADC_CHER_CH6 |\ AT91_ADC_CHER_CH7); // // setup the default sample rate // at91_adc_set_rate(chan, chan->device->config.rate); // setup ADC mode HAL_WRITE_UINT32((info->adc_base + AT91_ADC_MR), \ ( ( info->adc_prescal << AT91_ADC_MR_PRESCAL_SHIFT ) & \ AT91_ADC_MR_PRESCAL_MASK ) | \ ( ( info->adc_startup_time << AT91_ADC_MR_STARTUP_SHIFT ) & \ AT91_ADC_MR_STARTUP_MASK ) | \ ( ( info->adc_shtim << AT91_ADC_MR_SHTIM_SHIFT ) & \ AT91_ADC_MR_SHTIM_MASK ) | \ AT91_ADC_MR_TRGSEL_TIOA0 | \ info->resolution); } // if (!info->int_handle) cyg_adc_device_init(device); // initialize generic parts of driver return true; }