void AudDrv_Suspend_Clk_Off(void) { unsigned long flags; spin_lock_irqsave(&auddrv_Clk_lock, flags); if (Aud_AFE_Clk_cntr > 0) { PRINTK_AUD_CLK("AudDrv_Suspend_Clk_Off Aud_AFE_Clk_cntr:%d ANA_Clk(%d)\n", Aud_AFE_Clk_cntr, Aud_ANA_Clk_cntr); #ifdef PM_MANAGER_API //Disable AFE clock and I2S clock Afe_Set_Reg(AUDIO_TOP_CON0, 0x00004044, 0x00004044); // bit2: afe power off, bit6: I2S power off if (disable_clock(MT_CG_AUDIO_AFE, "AUDIO")) { xlog_printk(ANDROID_LOG_ERROR, "Sound", "AudDrv_Suspend_Clk_Off() disable_clock MT_CG_AUDIO_AFE fail"); } if (Aud_I2S_Clk_cntr > 0) { if (disable_clock(MT_CG_AUDIO_I2S, "AUDIO")) { xlog_printk(ANDROID_LOG_ERROR, "Sound", "AudDrv_Suspend_Clk_Off() disable_clock MT_CG_AUDIO_I2S fail"); } } #else Afe_Set_Reg(AUDIO_TOP_CON0, 0x00004044, 0x00004044); // bit2: afe power off, bit6: I2S power off #endif } spin_unlock_irqrestore(&auddrv_Clk_lock, flags); if (Aud_ANA_Clk_cntr > 0) { PRINTK_AUD_CLK("AudDrv_Suspend_Clk_On Aud_AFE_Clk_cntr:%d ANA_Clk(%d) \n", Aud_AFE_Clk_cntr, Aud_ANA_Clk_cntr); } }
static int mtk_thermal_suspend(struct platform_device *dev, pm_message_t state) { kal_uint32 i; mtktscpu_dprintk("[mtk_thermal_suspend] \n"); if(talking_flag==false) { printk("[mtk_thermal_suspend] \n"); mt65xx_reg_sync_writel(0x00000000, TEMPMONCTL0); // disable periodoc temperature sensing point 0 disable_clock(MT_CG_THEM_SW_CG,"THM"); disable_clock(MT_VCG_AUX_THERM,"THM"); // disable auxadc module. mt65xx_reg_sync_writel(DRV_Reg32(TS_CON0) | 0x000000C0, TS_CON0); // turn off the sensor buffer to save power } #ifdef MTK_CRYSTAL_THERMAL if((cpu_env_first == 0) && (mtktscpu_reset_first ==false)){ if((cpu_curr_temp - cpu_min_temp) > CPU_NOTIFY_THRESHOLD) { mtkts_crystal_notify(15000); } } #endif for(i=0;i< THERMAL_MAX;i++) { if(thm_suspend_cbk[i] != NULL) thm_suspend_cbk[i](); } return 0; }
bool usb_enable_clock(bool enable) { static int count = 0; bool res1 = TRUE; bool res2 = TRUE; bool res3 = TRUE; unsigned long flags; spin_lock_irqsave(&musb_reg_clock_lock, flags); if (enable && count == 0) { enable_phy_clock(true); res1 = enable_clock(MT_CG_INFRA_USB, "INFRA_USB"); res2 = enable_clock(MT_CG_INFRA_USB_MCU, "INFRA_USB_MCU"); res3 = enable_clock(MT_CG_INFRA_ICUSB, "INFRA_ICUSB"); } else if (!enable && count == 1) { res2 = disable_clock(MT_CG_INFRA_USB_MCU, "INFRA_USB_MCU"); res1 = disable_clock(MT_CG_INFRA_USB, "INFRA_USB"); res3 = disable_clock(MT_CG_INFRA_ICUSB, "INFRA_ICUSB"); enable_phy_clock(false); } if (enable) count++; else count = (count==0) ? 0 : (count-1); spin_unlock_irqrestore(&musb_reg_clock_lock, flags); printk(KERN_DEBUG "enable(%d), count(%d) res1=%d, res2=%d\n", enable, count, res1, res2); return 1; }
void mali_platform_power_mode_change(mali_power_mode power_mode) { unsigned long flags; switch (power_mode) { case MALI_POWER_MODE_ON: MALI_DEBUG_PRINT(3, ("Mali platform: Got MALI_POWER_MODE_ON event, %s\n", atomic_read((atomic_t *)&bPoweroff) ? "powering on" : "already on")); if (atomic_read((atomic_t *)&bPoweroff) == 1) { MALI_DEBUG_PRINT(3,("[+]MFG enable_clock \n")); mfg_pwr_lock(flags); if (!clock_is_on(MT_CG_MFG_G3D)) { enable_clock(MT_CG_DISP0_SMI_COMMON, "MFG"); enable_clock(MT_CG_MFG_G3D, "MFG"); } mfg_pwr_unlock(flags); MALI_DEBUG_PRINT(3,("[-]MFG enable_clock \n")); #if defined(CONFIG_MALI400_PROFILING) _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE | MALI_PROFILING_EVENT_CHANNEL_GPU | MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, 500, 1200/1000, 0, 0, 0); #endif atomic_set((atomic_t *)&bPoweroff, 0); } break; case MALI_POWER_MODE_LIGHT_SLEEP: case MALI_POWER_MODE_DEEP_SLEEP: MALI_DEBUG_PRINT(3, ("Mali platform: Got %s event, %s\n", power_mode == MALI_POWER_MODE_LIGHT_SLEEP ? "MALI_POWER_MODE_LIGHT_SLEEP" : "MALI_POWER_MODE_DEEP_SLEEP", atomic_read((atomic_t *)&bPoweroff) ? "already off" : "powering off")); if (atomic_read((atomic_t *)&bPoweroff) == 0) { MALI_DEBUG_PRINT(3,("[+]MFG disable_clock \n")); mfg_pwr_lock(flags); if (clock_is_on(MT_CG_MFG_G3D)) { disable_clock(MT_CG_MFG_G3D, "MFG"); disable_clock(MT_CG_DISP0_SMI_COMMON, "MFG"); } mfg_pwr_unlock(flags); MALI_DEBUG_PRINT(3,("[-]MFG disable_clock \n")); #if defined(CONFIG_MALI400_PROFILING) _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE | MALI_PROFILING_EVENT_CHANNEL_GPU | MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, 0, 0, 0, 0, 0); #endif atomic_set((atomic_t *)&bPoweroff, 1); } break; } }
void AudDrv_APLL24M_Clk_Off(void) { mutex_lock(&auddrv_pmic_mutex); Aud_APLL24M_Clk_cntr--; if (Aud_APLL24M_Clk_cntr == 0) { PRINTK_AUDDRV("+%s disable_clock ADC clk(%x)\n", __func__, Aud_APLL24M_Clk_cntr); #ifdef PM_MANAGER_API if (disable_clock(MT_CG_AUDIO_24M, "AUDIO")) { PRINTK_AUD_CLK("%s fail", __func__); } if (disable_clock(MT_CG_AUDIO_APLL2_TUNER, "AUDIO")) { PRINTK_AUD_CLK("%s fail", __func__); } clkmux_sel(MT_MUX_AUD2, 0, "AUDIO"); //select 26M disable_mux(MT_MUX_AUD2, "AUDIO"); #endif } if (Aud_APLL24M_Clk_cntr < 0) { PRINTK_AUDDRV("%s <0 (%d) \n", __func__, Aud_APLL24M_Clk_cntr); Aud_APLL24M_Clk_cntr = 0; } mutex_unlock(&auddrv_pmic_mutex); }
int ddp_path_lp_top_clock_off(void) { #ifdef ENABLE_CLK_MGR disable_clock(MT_CG_DISP0_SMI_LARB0 , "DDP"); disable_clock(MT_CG_DISP0_SMI_COMMON , "DDP"); #endif return 0; }
static void mali_early_suspend_handler(struct early_suspend *h) { mali_pm_os_suspend(); MALI_DEBUG_PRINT(1, ("[%s] disable_clock\n", __FUNCTION__)); disable_clock(MT_CG_MFG_G3D, "MFG"); disable_clock(MT_CG_DISP0_SMI_COMMON, "MFG"); }
void jpeg_drv_enc_power_off(void) { disable_clock(MT_CG_IMAGE_JPGE_SMI,"JPEG"); disable_clock(MT_CG_IMAGE_JPGE_JPG,"JPEG"); #ifdef FOR_COMPILE BOOL ret; ret = disable_clock(MT65XX_PDN_MM_JPEG_ENC,"JPEG"); NOT_REFERENCED(ret); #endif }
static int rdma_clock_off(DISP_MODULE_ENUM module,void * handle) { unsigned int idx = rdma_index(module); if(idx == 0){ disable_clock(MT_CG_DISP0_DISP_RDMA0 , "rdma0"); }else if(idx == 1){ disable_clock(MT_CG_DISP0_DISP_RDMA1 , "rdma1"); } else if(idx == 2){ disable_clock(MT_CG_DISP0_DISP_RDMA2 , "rdma2"); } DDPMSG("rdma_%d_clock_off CG 0x%x \n",idx, DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0)); return 0; }
static int rdma_clock_off(DISP_MODULE_ENUM module,void * handle) { unsigned int idx = rdma_index(module); #ifdef ENABLE_CLK_MGR if (idx == 0) { disable_clock(MT_CG_DISP0_DISP_RDMA0, "RDMA0"); }else{ disable_clock(MT_CG_DISP0_DISP_RDMA1, "RDMA1"); } #endif DDPMSG("rdma_%d_clock_off CG 0x%x \n",idx, DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0)); return 0; }
int ovl_suspend(DISP_MODULE_ENUM module, void *handle) { int idx = ovl_index(module); DDPMSG("ovl%d_suspend\n", idx); ovl_store_regs(module); #ifdef ENABLE_CLK_MGR if(idx == 0){ disable_clock(MT_CG_DISP0_DISP_OVL0+idx, "OVL0"); }else{ disable_clock(MT_CG_DISP0_DISP_OVL0+idx, "OVL1"); } #endif return 0; }
int ddp_path_top_clock_off(void) { DDPMSG("ddp path top clock off\n"); if(clk_is_force_on(MT_CG_DISP0_SMI_LARB0) || clk_is_force_on(MT_CG_DISP0_SMI_COMMON)) { DDPMSG("clear SMI_LARB0 & SMI_COMMON forced on\n"); clk_clr_force_on(MT_CG_DISP0_SMI_LARB0); clk_clr_force_on(MT_CG_DISP0_SMI_COMMON); } disable_clock(MT_CG_DISP0_MUTEX_32K , "DDP"); disable_clock(MT_CG_DISP0_SMI_LARB0 , "DDP"); disable_clock(MT_CG_DISP0_SMI_COMMON , "DDP"); return 0; }
void jpeg_drv_enc_power_off(void) { #ifndef FPGA_VERSION disable_clock(MT_CG_IMAGE_LARB2_SMI,"JPEG"); disable_clock(MT_CG_IMAGE_VENC_JPENC,"JPEG"); disable_clock(MT_CG_DISP0_SMI_COMMON,"JPEG"); #endif #ifdef FOR_COMPILE BOOL ret; ret = disable_clock(MT65XX_PDN_MM_JPEG_ENC,"JPEG"); NOT_REFERENCED(ret); #endif }
static void enable_phy_clock(bool enable) { /* USB phy 48M clock , UNIVPLL_CON0[26] */ if (enable) { enable_clock(MT_CG_UNIV_48M, "PERI_USB"); enable_clock(MT_CG_USB_48M, "PERI_USB"); } else { disable_clock(MT_CG_UNIV_48M, "PERI_USB"); disable_clock(MT_CG_USB_48M, "PERI_USB"); } }
void spm_module_init(void) { int r; unsigned long flags; spm_fs_init(); spin_lock_irqsave(&spm_lock, flags); #if 1//def SPM_CLOCK_INIT /*Only set during bringup init. No need to be changed.*/ if(clock_is_on(MT_CG_SPM_52M_SW_CG)) disable_clock(MT_CG_SPM_52M_SW_CG, "SPM"); if(!clock_is_on(MT_CG_SC_26M_CK_SEL_EN)) enable_clock(MT_CG_SC_26M_CK_SEL_EN, "SPM");//Enable the feature that SPM can switch bus and audio clock to be 26Mhz if(clock_is_on(MT_CG_SC_MEM_CK_OFF_EN)) disable_clock(MT_CG_SC_MEM_CK_OFF_EN, "SPM"); /*Dynamic on/off before entering suspend/DPidle and after leaving suspend/DPidle*/ if(!clock_is_on(MT_CG_MEMSLP_DLYER_SW_CG)) enable_clock(MT_CG_MEMSLP_DLYER_SW_CG, "SPM"); if(!clock_is_on(MT_CG_SPM_SW_CG))//need check with mtcmos owner for spm clk init gating enable_clock(MT_CG_SPM_SW_CG, "SPM"); #endif spin_unlock_irqrestore(&spm_lock, flags); r = request_irq(MT_SPM0_IRQ_ID, spm0_irq_handler, IRQF_TRIGGER_LOW,"mt-spm", NULL); if (r) { spm_error("SPM IRQ[0] register failed (%d)\n", r); WARN_ON(1); } #ifdef CONFIG_KICK_SPM_WDT #ifndef CONFIG_FIQ_GLUE //printk("******** MTK WDT register irq ********\n" ); r = request_irq(MT_SPM1_IRQ_ID, spm1_irq_handler, IRQF_TRIGGER_LOW,"[SPM WDT]", NULL); #else //printk("******** MTK WDT register fiq ********\n" ); r = request_fiq(MT_SPM1_IRQ_ID, spm1_fiq_handler, IRQF_TRIGGER_LOW, NULL); #endif #else r = request_irq(MT_SPM1_IRQ_ID, spm1_irq_handler, IRQF_TRIGGER_LOW,"mt-spm", NULL); #endif if (r) { spm_error("SPM IRQ[1] register failed (%d)\n", r); WARN_ON(1);} }
bool usb_enable_clock(bool enable) { static int count = 0; bool res = TRUE; unsigned long flags; spin_lock_irqsave(&musb_reg_clock_lock, flags); if (enable && count == 0) { /* * USB CG may default on. * To prevent clk_mgr reference count error. MUST CHECK is clock on? */ if(!clock_is_on(MT_CG_USB_SW_CG)){ res = enable_clock(MT_CG_USB_SW_CG, "PERI_USB"); } } else if (!enable && count == 1) { res = disable_clock(MT_CG_USB_SW_CG, "PERI_USB"); } if (enable) count++; else count = (count==0) ? 0 : (count-1); spin_unlock_irqrestore(&musb_reg_clock_lock, flags); printk(KERN_DEBUG "enable(%d), count(%d) res=%d\n", enable, count, res); return 1; }
/*----------------------------------------------------------------------------*/ static VOID HifPdmaClockCtrl( IN UINT_32 FlgIsEnabled ) { #if !defined(CONFIG_MTK_LEGACY) int ret = 0; #endif #if defined(CONFIG_MTK_LEGACY) if (FlgIsEnabled == TRUE) enable_clock(MT_CG_PERI_APDMA, "WLAN"); else disable_clock(MT_CG_PERI_APDMA, "WLAN"); #else if(FlgIsEnabled == TRUE) { ret = clk_prepare_enable(g_clk_wifi_pdma); if(ret) printk("[CCF]clk_prepare_enable ret= %d\n", ret); } else { clk_disable_unprepare(g_clk_wifi_pdma); } #endif }
int ddp_pwm_power_off(DISP_MODULE_ENUM module, void *handle) { PWM_MSG("ddp_pwm_power_off: %d\n", module); if (module == DISP_MODULE_PWM0) { atomic_set(&g_pwm_backlight[0], 0); disable_clock(MT_CG_DISP1_DISP_PWM0_26M , "PWM"); disable_clock(MT_CG_DISP1_DISP_PWM0_MM , "PWM"); } else if(module == DISP_MODULE_PWM1) { atomic_set(&g_pwm_backlight[1], 0); disable_clock(MT_CG_DISP1_DISP_PWM1_26M , "PWM"); disable_clock(MT_CG_DISP1_DISP_PWM1_MM , "PWM"); } return 0; }
void AudDrv_Core_Clk_Off(void) { //PRINTK_AUD_CLK("+AudDrv_Core_Clk_On, Aud_Core_Clk_cntr:%d \n", Aud_Core_Clk_cntr); unsigned long flags; spin_lock_irqsave(&auddrv_Clk_lock, flags); if (Aud_Core_Clk_cntr == 0) { #ifdef PM_MANAGER_API #if defined(CONFIG_MTK_LEGACY) if (disable_clock(MT_CG_AUDIO_AFE, "AUDIO")) { PRINTK_AUD_ERROR("AudDrv_Core_Clk_On Aud disable_clock MT_CG_AUDIO_AFE fail !!!\n"); } #else if (paudclk->aud_afe_clk_status) { clk_disable_unprepare(paudclk->aud_afe_clk); } #endif #endif } Aud_Core_Clk_cntr++; spin_unlock_irqrestore(&auddrv_Clk_lock, flags); //PRINTK_AUD_CLK("-AudDrv_Core_Clk_On, Aud_Core_Clk_cntr:%d \n", Aud_Core_Clk_cntr); }
void AudDrv_ADC_Clk_Off(void) { //PRINTK_AUDDRV("+AudDrv_ADC_Clk_Off, Aud_ADC_Clk_cntr:%d \n", Aud_ADC_Clk_cntr); mutex_lock(&auddrv_pmic_mutex); Aud_ADC_Clk_cntr--; if (Aud_ADC_Clk_cntr == 0) { PRINTK_AUDDRV("+AudDrv_ADC_Clk_On disable_clock ADC clk(%x)\n", Aud_ADC_Clk_cntr); //Afe_Set_Reg(AUDIO_TOP_CON0, 1 << 24 , 1 << 24); #ifdef PM_MANAGER_API #if defined(CONFIG_MTK_LEGACY) if (disable_clock(MT_CG_AUDIO_ADC, "AUDIO")) { PRINTK_AUD_CLK("%s fail", __func__); } #else if (paudclk->aud_adc_clk_status) { clk_disable_unprepare(paudclk->aud_adc_clk); } #endif #else Afe_Set_Reg(AUDIO_TOP_CON0, 1 << 24 , 1 << 24); #endif } if (Aud_ADC_Clk_cntr < 0) { PRINTK_AUDDRV("!! AudDrv_ADC_Clk_Off, Aud_ADC_Clk_cntr<0 (%d) \n", Aud_ADC_Clk_cntr); Aud_ADC_Clk_cntr = 0; } mutex_unlock(&auddrv_pmic_mutex); //PRINTK_AUDDRV("-AudDrv_ADC_Clk_Off, Aud_ADC_Clk_cntr:%d \n", Aud_ADC_Clk_cntr); }
void spm_dpidle_after_wfi(void) { #ifdef CONFIG_SMP //if (gpt_check_irq(GPT4)) { if (gpt_check_and_ack_irq(GPT4)) { /* waked up by WAKEUP_GPT */ localtimer_set_next_event(1); } else { /* waked up by other wakeup source */ unsigned int cnt, cmp; gpt_get_cnt(GPT4, &cnt); gpt_get_cmp(GPT4, &cmp); if (unlikely(cmp < cnt)) { idle_err("[%s]GPT%d: counter = %10u, compare = %10u\n", __func__, GPT4 + 1, cnt, cmp); BUG(); } localtimer_set_next_event(cmp-cnt); stop_gpt(GPT4); //GPT_ClearCount(WAKEUP_GPT); free_gpt(GPT4); } #endif disable_clock(MT_CG_PMIC_SW_CG_AP, "DEEP_IDLE"); clkmux_sel(MT_CLKMUX_AUD_INTBUS_SEL,g_clk_aud_intbus_sel,"Deep_Idle"); dpidle_cnt[0]++; }
bool usb_enable_clock(bool enable) { static int count = 0; bool res = TRUE; unsigned long flags; spin_lock_irqsave(&musb_reg_clock_lock, flags); if (enable && count == 0) { enable_phy_clock(true); res = enable_clock(MT_CG_PERI_USB0, "PERI_USB"); } else if (!enable && count == 1) { res = disable_clock(MT_CG_PERI_USB0, "PERI_USB"); enable_phy_clock(false); } if (enable) count++; else count = (count==0) ? 0 : (count-1); spin_unlock_irqrestore(&musb_reg_clock_lock, flags); printk(KERN_DEBUG "enable(%d), count(%d) res=%d\n", enable, count, res); return 1; }
void cmdq_core_enable_common_clock_locked_impl(bool enable) { #ifdef CMDQ_PWR_AWARE if (enable) { CMDQ_VERBOSE("[CLOCK] Enable SMI & LARB0 Clock\n"); cmdq_dev_enable_clock_SMI_COMMON(enable); cmdq_dev_enable_clock_SMI_LARB0(enable); #if 0 /* MT_CG_DISP0_MUTEX_32K is removed in this platform */ CMDQ_LOG("[CLOCK] enable MT_CG_DISP0_MUTEX_32K\n"); enable_clock(MT_CG_DISP0_MUTEX_32K, "CMDQ_MDP"); #endif } else { CMDQ_VERBOSE("[CLOCK] Disable SMI & LARB0 Clock\n"); /* disable, reverse the sequence */ cmdq_dev_enable_clock_SMI_LARB0(enable); cmdq_dev_enable_clock_SMI_COMMON(enable); #if 0 /* MT_CG_DISP0_MUTEX_32K is removed in this platform */ CMDQ_LOG("[CLOCK] disable MT_CG_DISP0_MUTEX_32K\n"); disable_clock(MT_CG_DISP0_MUTEX_32K, "CMDQ_MDP"); #endif } #endif /* CMDQ_PWR_AWARE */ }
void AudDrv_I2S_Clk_Off(void) { unsigned long flags; //PRINTK_AUD_CLK("+AudDrv_I2S_Clk_Off, Aud_I2S_Clk_cntr:%d \n", Aud_I2S_Clk_cntr); spin_lock_irqsave(&auddrv_Clk_lock, flags); Aud_I2S_Clk_cntr--; if (Aud_I2S_Clk_cntr == 0) { #ifdef PM_MANAGER_API if (disable_clock(MT_CG_AUDIO_I2S, "AUDIO")) { PRINTK_AUD_ERROR("disable_clock MT_CG_AUDIO_I2S fail"); } #else Afe_Set_Reg(AUDIO_TOP_CON0, 0x00000000, 0x00000040); //power off I2S clock #endif } else if (Aud_I2S_Clk_cntr < 0) { PRINTK_AUD_ERROR("!! AudDrv_I2S_Clk_Off, Aud_I2S_Clk_cntr<0 (%d) \n", Aud_I2S_Clk_cntr); AUDIO_ASSERT(true); Aud_I2S_Clk_cntr = 0; } spin_unlock_irqrestore(&auddrv_Clk_lock, flags); //PRINTK_AUD_CLK("-AudDrv_I2S_Clk_Off, Aud_I2S_Clk_cntr:%d \n",Aud_I2S_Clk_cntr); }
void AudDrv_ADC2_Clk_Off(void) { //PRINTK_AUDDRV("+%s %d \n", __func__,Aud_ADC2_Clk_cntr); mutex_lock(&auddrv_pmic_mutex); Aud_ADC2_Clk_cntr--; if (Aud_ADC2_Clk_cntr == 0) { PRINTK_AUDDRV("+%s disable_clock ADC clk(%x)\n", __func__, Aud_ADC2_Clk_cntr); #if 0 //K2 removed #ifdef PM_MANAGER_API if (disable_clock(MT_CG_AUDIO_ADDA2, "AUDIO")) { PRINTK_AUD_CLK("%s fail", __func__); } #else Afe_Set_Reg(AUDIO_TOP_CON0, 1 << 23 , 1 << 23); //temp hard code setting, after confirm with enable clock usage, this could be removed. #endif #endif } if (Aud_ADC2_Clk_cntr < 0) { PRINTK_AUDDRV("%s <0 (%d) \n", __func__, Aud_ADC2_Clk_cntr); Aud_ADC2_Clk_cntr = 0; } mutex_unlock(&auddrv_pmic_mutex); //PRINTK_AUDDRV("-AudDrv_ADC_Clk_Off, Aud_ADC_Clk_cntr:%d \n", Aud_ADC_Clk_cntr); }
void AudDrv_Clk_Off(void) { unsigned long flags; //PRINTK_AUD_CLK("+!! AudDrv_Clk_Off, Aud_AFE_Clk_cntr:%d \n",Aud_AFE_Clk_cntr); spin_lock_irqsave(&auddrv_Clk_lock, flags); Aud_AFE_Clk_cntr--; if (Aud_AFE_Clk_cntr == 0) { PRINTK_AUD_CLK("+ AudDrv_Clk_Off, Aud_AFE_Clk_cntr:%d \n", Aud_AFE_Clk_cntr); { // Disable AFE clock #ifdef PM_MANAGER_API if (disable_clock(MT_CG_AUDIO_AFE, "AUDIO")) { xlog_printk(ANDROID_LOG_ERROR, "Sound", "disable_clock MT_CG_AUDIO_AFE fail"); } #else //Afe_Set_Reg(AUDIO_TOP_CON0, 0x00000000, 0x00000004); // bit2: afe power on #endif } } else if (Aud_AFE_Clk_cntr < 0) { PRINTK_AUD_ERROR("!! AudDrv_Clk_Off, Aud_AFE_Clk_cntr<0 (%d) \n", Aud_AFE_Clk_cntr); AUDIO_ASSERT(true); Aud_AFE_Clk_cntr = 0; } spin_unlock_irqrestore(&auddrv_Clk_lock, flags); }
void AudDrv_ADC3_Clk_Off(void) { //PRINTK_AUDDRV("+%s %d \n", __func__,Aud_ADC2_Clk_cntr); mutex_lock(&auddrv_pmic_mutex); Aud_ADC3_Clk_cntr--; if (Aud_ADC3_Clk_cntr == 0) { PRINTK_AUDDRV("+%s disable_clock ADC clk(%x)\n", __func__, Aud_ADC3_Clk_cntr); #if 0 //K2 removed #ifdef PM_MANAGER_API if (disable_clock(MT_CG_AUDIO_ADDA3, "AUDIO")) { PRINTK_AUD_CLK("%s fail", __func__); } #endif #endif } if (Aud_ADC3_Clk_cntr < 0) { PRINTK_AUDDRV("%s <0 (%d) \n", __func__, Aud_ADC3_Clk_cntr); Aud_ADC3_Clk_cntr = 0; } mutex_unlock(&auddrv_pmic_mutex); //PRINTK_AUDDRV("-AudDrv_ADC_Clk_Off, Aud_ADC_Clk_cntr:%d \n", Aud_ADC_Clk_cntr); }
bool usb_enable_clock(bool enable) { #ifndef CONFIG_MT6575T_FPGA static int count = 0; bool res = TRUE; unsigned long flags; spin_lock_irqsave(&musb_reg_clock_lock, flags); if (enable && count == 0) { res = enable_clock(MT65XX_PDN_PERI_USB1, "PERI_USB"); } else if (!enable && count == 1) { res = disable_clock(MT65XX_PDN_PERI_USB1, "PERI_USB"); } if (enable) count++; else count = (count==0) ? 0 : (count-1); spin_unlock_irqrestore(&musb_reg_clock_lock, flags); printk(KERN_DEBUG "enable(%d), count(%d) res=%d\n", enable, count, res); #endif //End of CONFIG_MT6589_FPGA return 1; }
static int mt_eis_clk_onoff(__user unsigned long arg) { spin_lock_irq(&eis_lock); if (arg == 1) { if (bClockState == FALSE) { enable_clock(MT65XX_PDN_MM_EIS , "EIS"); bClockState = TRUE; } } else { if (bClockState == TRUE) { disable_clock(MT65XX_PDN_MM_EIS , "EIS"); bClockState = FALSE; } } spin_unlock_irq(&eis_lock); return 0; }
int ddp_path_top_clock_off(void) { #ifdef ENABLE_CLK_MGR DDPMSG("ddp path top clock off\n"); if(clk_is_force_on(MT_CG_DISP0_SMI_LARB0) || clk_is_force_on(MT_CG_DISP0_SMI_COMMON)) { printk("[ddp] clear SMI_LARB0 & SMI_COMMON forced on\n"); clk_clr_force_on(MT_CG_DISP0_SMI_LARB0); clk_clr_force_on(MT_CG_DISP0_SMI_COMMON); } // disable_clock(MT_CG_DISP0_MUTEX_32K , "DDP"); disable_clock(MT_CG_DISP0_SMI_LARB0 , "DDP"); disable_clock(MT_CG_DISP0_SMI_COMMON , "DDP"); #endif return 0; }