static void __init gapspci_fixup_resources(struct pci_dev *dev) { struct pci_channel *p = board_pci_channels; printk(KERN_NOTICE "PCI: Fixing up device %s\n", pci_name(dev)); switch (dev->device) { case PCI_DEVICE_ID_SEGA_BBA: /* * We also assume that dev->devfn == 0 */ dev->resource[1].start = p->io_resource->start + 0x100; dev->resource[1].end = dev->resource[1].start + 0x200 - 1; /* * Redirect dma memory allocations to special memory window. */ BUG_ON(!dma_declare_coherent_memory(&dev->dev, GAPSPCI_DMA_BASE, GAPSPCI_DMA_BASE, GAPSPCI_DMA_SIZE, DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE)); break; default: printk("PCI: Failed resource fixup\n"); } }
static int __init mx31_3ds_init_camera(void) { int dma, ret = -ENOMEM; struct platform_device *pdev = imx31_alloc_mx3_camera(&mx31_3ds_camera_pdata); if (IS_ERR(pdev)) return PTR_ERR(pdev); if (!mx3_camera_base) goto err; dma = dma_declare_coherent_memory(&pdev->dev, mx3_camera_base, mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE, DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); if (!(dma & DMA_MEMORY_MAP)) goto err; ret = platform_device_add(pdev); if (ret) err: platform_device_put(pdev); return ret; }
static void __init gapspci_fixup_resources(struct pci_dev *dev) { struct pci_channel *p = dev->sysdata; printk(KERN_NOTICE "PCI: Fixing up device %s\n", pci_name(dev)); switch (dev->device) { case PCI_DEVICE_ID_SEGA_BBA: /* * We also assume that dev->devfn == 0 */ dev->resource[1].start = p->resources[0].start + 0x100; dev->resource[1].end = dev->resource[1].start + 0x200 - 1; /* * This is not a normal BAR, prevent any attempts to move * the BAR, as this will result in a bus lock. */ dev->resource[1].flags |= IORESOURCE_PCI_FIXED; /* * Redirect dma memory allocations to special memory window. */ BUG_ON(!dma_declare_coherent_memory(&dev->dev, GAPSPCI_DMA_BASE, GAPSPCI_DMA_BASE, GAPSPCI_DMA_SIZE, DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE)); break; default: printk("PCI: Failed resource fixup\n"); } }
static int __init mx31_3ds_camera_alloc_dma(void) { int dma; if (!mx3_camera_base) return -ENOMEM; dma = dma_declare_coherent_memory(&mx3_camera.dev, mx3_camera_base, mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE, DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); if (!(dma & DMA_MEMORY_MAP)) return -ENOMEM; return 0; }
static void gapspci_fixup_resources(struct pci_dev *dev) { struct pci_channel *p = dev->sysdata; struct resource res; struct pci_bus_region region; printk(KERN_NOTICE "PCI: Fixing up device %s\n", pci_name(dev)); switch (dev->device) { case PCI_DEVICE_ID_SEGA_BBA: /* * We also assume that dev->devfn == 0 */ dev->resource[1].start = p->resources[0].start + 0x100; dev->resource[1].end = dev->resource[1].start + 0x200 - 1; /* * This is not a normal BAR, prevent any attempts to move * the BAR, as this will result in a bus lock. */ dev->resource[1].flags |= IORESOURCE_PCI_FIXED; /* * Redirect dma memory allocations to special memory window. * * If this GAPSPCI region were mapped by a BAR, the CPU * phys_addr_t would be pci_resource_start(), and the bus * address would be pci_bus_address(pci_resource_start()). * But apparently there's no BAR mapping it, so we just * "know" its CPU address is GAPSPCI_DMA_BASE. */ res.start = GAPSPCI_DMA_BASE; res.end = GAPSPCI_DMA_BASE + GAPSPCI_DMA_SIZE - 1; res.flags = IORESOURCE_MEM; pcibios_resource_to_bus(dev->bus, ®ion, &res); BUG_ON(dma_declare_coherent_memory(&dev->dev, res.start, region.start, resource_size(&res))); break; default: printk("PCI: Failed resource fixup\n"); } }
/* enable SRAM if sram detected */ static void sram_init(struct usb_hcd *hcd) { struct ehci_hcd *ehci = hcd_to_ehci(hcd); struct pci_dev *pdev = to_pci_dev(hcd->self.controller); void __iomem *base = NULL; void __iomem *addr = NULL; if (!hcd->has_sram) return; ehci->sram_addr = pci_resource_start(pdev, 1); ehci->sram_size = pci_resource_len(pdev, 1); ehci_info(ehci, "Found HCD SRAM at %x size:%x\n", ehci->sram_addr, ehci->sram_size); if (pci_request_region(pdev, 1, kobject_name(&pdev->dev.kobj))) { ehci_warn(ehci, "SRAM request failed\n"); hcd->has_sram = 0; return; } else if (!dma_declare_coherent_memory(&pdev->dev, ehci->sram_addr, ehci->sram_addr, ehci->sram_size, DMA_MEMORY_MAP)) { ehci_warn(ehci, "SRAM DMA declare failed\n"); pci_release_region(pdev, 1); hcd->has_sram = 0; return; } /* initialize SRAM to 0 to avoid ECC errors during entry into D0 */ base = ioremap_nocache(ehci->sram_addr, ehci->sram_size); if (base == NULL) { ehci_warn(ehci, "SRAM init: ioremap failed\n"); return; } addr = base; while (addr < base + ehci->sram_size) { writel(0x0, addr); addr = addr + 4; } iounmap(base); }
static int __init pcm037_camera_alloc_dma(const size_t buf_size) { dma_addr_t dma_handle; void *buf; int dma; if (buf_size < 2 * 1024 * 1024) return -EINVAL; buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL); if (!buf) { pr_err("%s: cannot allocate camera buffer-memory\n", __func__); return -ENOMEM; } memset(buf, 0, buf_size); dma = dma_declare_coherent_memory(&mx3_camera.dev, dma_handle, dma_handle, buf_size, DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); /* The way we call dma_declare_coherent_memory only a malloc can fail */ return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM; }
static int __devinit ohci_hcd_tmio_drv_probe(struct platform_device *dev) { const struct mfd_cell *cell = mfd_get_cell(dev); struct resource *regs = platform_get_resource(dev, IORESOURCE_MEM, 0); struct resource *config = platform_get_resource(dev, IORESOURCE_MEM, 1); struct resource *sram = platform_get_resource(dev, IORESOURCE_MEM, 2); int irq = platform_get_irq(dev, 0); struct tmio_hcd *tmio; struct ohci_hcd *ohci; struct usb_hcd *hcd; int ret; if (usb_disabled()) return -ENODEV; if (!cell) return -EINVAL; hcd = usb_create_hcd(&ohci_tmio_hc_driver, &dev->dev, dev_name(&dev->dev)); if (!hcd) { ret = -ENOMEM; goto err_usb_create_hcd; } hcd->rsrc_start = regs->start; hcd->rsrc_len = resource_size(regs); tmio = hcd_to_tmio(hcd); spin_lock_init(&tmio->lock); tmio->ccr = ioremap(config->start, resource_size(config)); if (!tmio->ccr) { ret = -ENOMEM; goto err_ioremap_ccr; } hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); if (!hcd->regs) { ret = -ENOMEM; goto err_ioremap_regs; } if (!dma_declare_coherent_memory(&dev->dev, sram->start, sram->start, resource_size(sram), DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE)) { ret = -EBUSY; goto err_dma_declare; } if (cell->enable) { ret = cell->enable(dev); if (ret) goto err_enable; } tmio_start_hc(dev); ohci = hcd_to_ohci(hcd); ohci_hcd_init(ohci); ret = usb_add_hcd(hcd, irq, 0); if (ret) goto err_add_hcd; if (ret == 0) return ret; usb_remove_hcd(hcd); err_add_hcd: tmio_stop_hc(dev); if (cell->disable) cell->disable(dev); err_enable: dma_release_declared_memory(&dev->dev); err_dma_declare: iounmap(hcd->regs); err_ioremap_regs: iounmap(tmio->ccr); err_ioremap_ccr: usb_put_hcd(hcd); err_usb_create_hcd: return ret; }
static int ohci_hcd_sm501_drv_probe(struct platform_device *pdev) { const struct hc_driver *driver = &ohci_sm501_hc_driver; struct device *dev = &pdev->dev; struct resource *res, *mem; int retval, irq; struct usb_hcd *hcd = NULL; irq = retval = platform_get_irq(pdev, 0); if (retval < 0) goto err0; mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); if (mem == NULL) { dev_err(dev, "no resource definition for memory\n"); retval = -ENOENT; goto err0; } if (!request_mem_region(mem->start, resource_size(mem), pdev->name)) { dev_err(dev, "request_mem_region failed\n"); retval = -EBUSY; goto err0; } /* The sm501 chip is equipped with local memory that may be used * by on-chip devices such as the video controller and the usb host. * This driver uses dma_declare_coherent_memory() to make sure * usb allocations with dma_alloc_coherent() allocate from * this local memory. The dma_handle returned by dma_alloc_coherent() * will be an offset starting from 0 for the first local memory byte. * * So as long as data is allocated using dma_alloc_coherent() all is * fine. This is however not always the case - buffers may be allocated * using kmalloc() - so the usb core needs to be told that it must copy * data into our local memory if the buffers happen to be placed in * regular memory. The HCD_LOCAL_MEM flag does just that. */ if (!dma_declare_coherent_memory(dev, mem->start, mem->start - mem->parent->start, resource_size(mem), DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE)) { dev_err(dev, "cannot declare coherent memory\n"); retval = -ENXIO; goto err1; } /* allocate, reserve and remap resources for registers */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res == NULL) { dev_err(dev, "no resource definition for registers\n"); retval = -ENOENT; goto err2; } hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); if (!hcd) { retval = -ENOMEM; goto err2; } hcd->rsrc_start = res->start; hcd->rsrc_len = resource_size(res); if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, pdev->name)) { dev_err(dev, "request_mem_region failed\n"); retval = -EBUSY; goto err3; } hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); if (hcd->regs == NULL) { dev_err(dev, "cannot remap registers\n"); retval = -ENXIO; goto err4; } ohci_hcd_init(hcd_to_ohci(hcd)); retval = usb_add_hcd(hcd, irq, IRQF_SHARED); if (retval) goto err5; /* enable power and unmask interrupts */ sm501_unit_power(dev->parent, SM501_GATE_USB_HOST, 1); sm501_modify_reg(dev->parent, SM501_IRQ_MASK, 1 << 6, 0); return 0; err5: iounmap(hcd->regs); err4: release_mem_region(hcd->rsrc_start, hcd->rsrc_len); err3: usb_put_hcd(hcd); err2: dma_release_declared_memory(dev); err1: release_mem_region(mem->start, resource_size(mem)); err0: return retval; }
static int __init migor_devices_setup(void) { struct clk *video_clk; /* register board specific self-refresh code */ sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF, &migor_sdram_enter_start, &migor_sdram_enter_end, &migor_sdram_leave_start, &migor_sdram_leave_end); regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, ARRAY_SIZE(fixed3v3_power_consumers), 3300000); /* Let D11 LED show STATUS0 */ gpio_request(GPIO_FN_STATUS0, NULL); /* Lit D12 LED show PDSTATUS */ gpio_request(GPIO_FN_PDSTATUS, NULL); /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */ gpio_request(GPIO_FN_IRQ0, NULL); __raw_writel(0x00003400, BSC_CS4BCR); __raw_writel(0x00110080, BSC_CS4WCR); /* KEYSC */ gpio_request(GPIO_FN_KEYOUT0, NULL); gpio_request(GPIO_FN_KEYOUT1, NULL); gpio_request(GPIO_FN_KEYOUT2, NULL); gpio_request(GPIO_FN_KEYOUT3, NULL); gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); gpio_request(GPIO_FN_KEYIN1, NULL); gpio_request(GPIO_FN_KEYIN2, NULL); gpio_request(GPIO_FN_KEYIN3, NULL); gpio_request(GPIO_FN_KEYIN4, NULL); gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); /* NAND Flash */ gpio_request(GPIO_FN_CS6A_CE2B, NULL); __raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR); gpio_request(GPIO_PTA1, NULL); gpio_direction_input(GPIO_PTA1); /* SDHI */ gpio_request(GPIO_FN_SDHICD, NULL); gpio_request(GPIO_FN_SDHIWP, NULL); gpio_request(GPIO_FN_SDHID3, NULL); gpio_request(GPIO_FN_SDHID2, NULL); gpio_request(GPIO_FN_SDHID1, NULL); gpio_request(GPIO_FN_SDHID0, NULL); gpio_request(GPIO_FN_SDHICMD, NULL); gpio_request(GPIO_FN_SDHICLK, NULL); /* Touch Panel */ gpio_request(GPIO_FN_IRQ6, NULL); /* LCD Panel */ #ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */ gpio_request(GPIO_FN_LCDD17, NULL); gpio_request(GPIO_FN_LCDD16, NULL); gpio_request(GPIO_FN_LCDD15, NULL); gpio_request(GPIO_FN_LCDD14, NULL); gpio_request(GPIO_FN_LCDD13, NULL); gpio_request(GPIO_FN_LCDD12, NULL); gpio_request(GPIO_FN_LCDD11, NULL); gpio_request(GPIO_FN_LCDD10, NULL); gpio_request(GPIO_FN_LCDD8, NULL); gpio_request(GPIO_FN_LCDD7, NULL); gpio_request(GPIO_FN_LCDD6, NULL); gpio_request(GPIO_FN_LCDD5, NULL); gpio_request(GPIO_FN_LCDD4, NULL); gpio_request(GPIO_FN_LCDD3, NULL); gpio_request(GPIO_FN_LCDD2, NULL); gpio_request(GPIO_FN_LCDD1, NULL); gpio_request(GPIO_FN_LCDRS, NULL); gpio_request(GPIO_FN_LCDCS, NULL); gpio_request(GPIO_FN_LCDRD, NULL); gpio_request(GPIO_FN_LCDWR, NULL); gpio_request(GPIO_PTH2, NULL); /* LCD_DON */ gpio_direction_output(GPIO_PTH2, 1); #endif #ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */ gpio_request(GPIO_FN_LCDD15, NULL); gpio_request(GPIO_FN_LCDD14, NULL); gpio_request(GPIO_FN_LCDD13, NULL); gpio_request(GPIO_FN_LCDD12, NULL); gpio_request(GPIO_FN_LCDD11, NULL); gpio_request(GPIO_FN_LCDD10, NULL); gpio_request(GPIO_FN_LCDD9, NULL); gpio_request(GPIO_FN_LCDD8, NULL); gpio_request(GPIO_FN_LCDD7, NULL); gpio_request(GPIO_FN_LCDD6, NULL); gpio_request(GPIO_FN_LCDD5, NULL); gpio_request(GPIO_FN_LCDD4, NULL); gpio_request(GPIO_FN_LCDD3, NULL); gpio_request(GPIO_FN_LCDD2, NULL); gpio_request(GPIO_FN_LCDD1, NULL); gpio_request(GPIO_FN_LCDD0, NULL); gpio_request(GPIO_FN_LCDLCLK, NULL); gpio_request(GPIO_FN_LCDDCK, NULL); gpio_request(GPIO_FN_LCDVEPWC, NULL); gpio_request(GPIO_FN_LCDVCPWC, NULL); gpio_request(GPIO_FN_LCDVSYN, NULL); gpio_request(GPIO_FN_LCDHSYN, NULL); gpio_request(GPIO_FN_LCDDISP, NULL); gpio_request(GPIO_FN_LCDDON, NULL); #endif /* CEU */ gpio_request(GPIO_FN_VIO_CLK2, NULL); gpio_request(GPIO_FN_VIO_VD2, NULL); gpio_request(GPIO_FN_VIO_HD2, NULL); gpio_request(GPIO_FN_VIO_FLD, NULL); gpio_request(GPIO_FN_VIO_CKO, NULL); gpio_request(GPIO_FN_VIO_D15, NULL); gpio_request(GPIO_FN_VIO_D14, NULL); gpio_request(GPIO_FN_VIO_D13, NULL); gpio_request(GPIO_FN_VIO_D12, NULL); gpio_request(GPIO_FN_VIO_D11, NULL); gpio_request(GPIO_FN_VIO_D10, NULL); gpio_request(GPIO_FN_VIO_D9, NULL); gpio_request(GPIO_FN_VIO_D8, NULL); __raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */ /* SIU: Port B */ gpio_request(GPIO_FN_SIUBOLR, NULL); gpio_request(GPIO_FN_SIUBOBT, NULL); gpio_request(GPIO_FN_SIUBISLD, NULL); gpio_request(GPIO_FN_SIUBOSLD, NULL); gpio_request(GPIO_FN_SIUMCKB, NULL); /* * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to * output. Need only SIUB, set to output for master mode (table 34.2) */ __raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA); /* * Use 10 MHz VIO_CKO instead of 24 MHz to work around signal quality * issues on Panel Board V2.1. */ video_clk = clk_get(NULL, "video_clk"); if (!IS_ERR(video_clk)) { clk_set_rate(video_clk, clk_round_rate(video_clk, 10000000)); clk_put(video_clk); } /* Add a clock alias for ov7725 xclk source. */ clk_add_alias(NULL, "0-0021", "video_clk", NULL); /* Register GPIOs for video sources. */ gpiod_add_lookup_table(&ov7725_gpios); gpiod_add_lookup_table(&tw9910_gpios); i2c_register_board_info(0, migor_i2c_devices, ARRAY_SIZE(migor_i2c_devices)); /* Initialize CEU platform device separately to map memory first */ device_initialize(&migor_ceu_device.dev); arch_setup_pdev_archdata(&migor_ceu_device); dma_declare_coherent_memory(&migor_ceu_device.dev, ceu_dma_membase, ceu_dma_membase, ceu_dma_membase + CEU_BUFFER_MEMORY_SIZE - 1, DMA_MEMORY_EXCLUSIVE); platform_device_add(&migor_ceu_device); return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices)); }
static int zynq_rpmsg_initialize(struct platform_device *pdev) { int ret = 0; int index; struct virtio_device *virtio_dev; /* Register ipi handler. */ ret = set_ipi_handler(zynq_rpmsg_p->vring0, ipi_handler, "Firmware kick"); if (ret) { dev_err(&pdev->dev, "IPI handler already registered\n"); return -ENODEV; } /* Initialize work. */ INIT_WORK(&zynq_rpmsg_work, handle_event); /* Memory allocations for vrings. */ ret = dma_declare_coherent_memory(&pdev->dev, zynq_rpmsg_p->mem_start, zynq_rpmsg_p->mem_start, zynq_rpmsg_p->mem_end - zynq_rpmsg_p->mem_start + 1, DMA_MEMORY_IO); if (!ret) { dev_err(&pdev->dev, "dma_declare_coherent_memory failed\n"); return -ENODEV; } ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); if (ret) { dev_err(&pdev->dev, "dma_set_coherent_mask: %d\n", ret); return -ENODEV; } /* Initialize a mid-level device. Needed because of bad data structure * handling and assumptions within the virtio rpmsg bus. We are doing it * to just make sure that the virtio device has a parent device which * then itself has a parent in the form of the platform device. */ device_initialize(&(zynq_rpmsg_p->mid_dev)); zynq_rpmsg_p->mid_dev.parent = &(pdev->dev); zynq_rpmsg_p->mid_dev.type = &mid_level_type; index = ida_simple_get(&rpmsg_zynq_dev_index, 0, 0, GFP_KERNEL); if (index < 0) { put_device(&(zynq_rpmsg_p->mid_dev)); return -ENODEV; } dev_set_name(&(zynq_rpmsg_p->mid_dev), "rpmsg_mid%d", index); device_add(&(zynq_rpmsg_p->mid_dev)); /* Setup the virtio device structure. */ virtio_dev = &(zynq_rpmsg_p->virtio_dev); virtio_dev->id.device = zynq_rpmsg_p->virtioid; virtio_dev->config = &zynq_rpmsg_virtio_config_ops; virtio_dev->dev.parent = &(zynq_rpmsg_p->mid_dev); virtio_dev->dev.release = zynq_rpmsg_vdev_release; /* Register the virtio device. */ ret = register_virtio_device(virtio_dev); dev_info(&(zynq_rpmsg_platform->dev), "virtio device registered \r\n"); return ret; }
static int ohci_hcd_sm501_drv_probe(struct platform_device *pdev) { const struct hc_driver *driver = &ohci_sm501_hc_driver; struct device *dev = &pdev->dev; struct resource *res, *mem; int retval, irq; struct usb_hcd *hcd = NULL; irq = retval = platform_get_irq(pdev, 0); if (retval < 0) goto err0; mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); if (mem == NULL) { dev_err(dev, "no resource definition for memory\n"); retval = -ENOENT; goto err0; } if (!request_mem_region(mem->start, mem->end - mem->start + 1, pdev->name)) { dev_err(dev, "request_mem_region failed\n"); retval = -EBUSY; goto err0; } if (!dma_declare_coherent_memory(dev, mem->start, mem->start - mem->parent->start, (mem->end - mem->start) + 1, DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE)) { dev_err(dev, "cannot declare coherent memory\n"); retval = -ENXIO; goto err1; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res == NULL) { dev_err(dev, "no resource definition for registers\n"); retval = -ENOENT; goto err2; } hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); if (!hcd) { retval = -ENOMEM; goto err2; } hcd->rsrc_start = res->start; hcd->rsrc_len = res->end - res->start + 1; if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, pdev->name)) { dev_err(dev, "request_mem_region failed\n"); retval = -EBUSY; goto err3; } hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); if (hcd->regs == NULL) { dev_err(dev, "cannot remap registers\n"); retval = -ENXIO; goto err4; } ohci_hcd_init(hcd_to_ohci(hcd)); retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); if (retval) goto err4; sm501_unit_power(dev->parent, SM501_GATE_USB_HOST, 1); sm501_modify_reg(dev->parent, SM501_IRQ_MASK, 1 << 6, 0); return 0; err4: release_mem_region(hcd->rsrc_start, hcd->rsrc_len); err3: usb_put_hcd(hcd); err2: dma_release_declared_memory(dev); err1: release_mem_region(mem->start, mem->end - mem->start + 1); err0: return retval; }
static int __devinit ehci_hcd_hlwd_probe(struct of_device *op, const struct of_device_id *match) { struct device_node *dn = op->node; struct usb_hcd *hcd; struct ehci_hcd *ehci = NULL; struct resource res; dma_addr_t coherent_mem_addr; size_t coherent_mem_size; int irq; int error = -ENODEV; if (usb_disabled()) goto out; if (starlet_get_ipc_flavour() != STARLET_IPC_MINI) goto out; dev_dbg(&op->dev, "initializing " DRV_MODULE_NAME " USB Controller\n"); error = of_address_to_resource(dn, 0, &res); if (error) goto out; hcd = usb_create_hcd(&ehci_hlwd_hc_driver, &op->dev, DRV_MODULE_NAME); if (!hcd) { error = -ENOMEM; goto out; } hcd->rsrc_start = res.start; hcd->rsrc_len = resource_size(&res); error = of_address_to_resource(dn, 1, &res); if (error) { /* satisfy coherent memory allocations from mem1 or mem2 */ dev_warn(&op->dev, "using normal memory\n"); } else { coherent_mem_addr = res.start; coherent_mem_size = res.end - res.start + 1; if (!dma_declare_coherent_memory(&op->dev, coherent_mem_addr, coherent_mem_addr, coherent_mem_size, DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE)) { dev_err(&op->dev, "error declaring %u bytes of" " coherent memory at 0x%p\n", coherent_mem_size, (void *)coherent_mem_addr); error = -EBUSY; goto err_decl_coherent; } } irq = irq_of_parse_and_map(dn, 0); if (irq == NO_IRQ) { printk(KERN_ERR __FILE__ ": irq_of_parse_and_map failed\n"); error = -EBUSY; goto err_irq; } hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); if (!hcd->regs) { printk(KERN_ERR __FILE__ ": ioremap failed\n"); error = -EBUSY; goto err_ioremap; } ehci = hcd_to_ehci(hcd); ehci->caps = hcd->regs; ehci->regs = hcd->regs + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); /* cache this readonly data; minimize chip reads */ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); error = usb_add_hcd(hcd, irq, 0); if (error == 0) return 0; iounmap(hcd->regs); err_ioremap: irq_dispose_mapping(irq); err_irq: dma_release_declared_memory(&op->dev); err_decl_coherent: usb_put_hcd(hcd); out: return error; }
static int __init arch_setup(void) { struct clk *clk; bool cn12_enabled = false; /* register board specific self-refresh code */ sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF | SUSP_SH_RSTANDBY, &ecovec24_sdram_enter_start, &ecovec24_sdram_enter_end, &ecovec24_sdram_leave_start, &ecovec24_sdram_leave_end); /* enable STATUS0, STATUS2 and PDSTATUS */ gpio_request(GPIO_FN_STATUS0, NULL); gpio_request(GPIO_FN_STATUS2, NULL); gpio_request(GPIO_FN_PDSTATUS, NULL); /* enable SCIFA0 */ gpio_request(GPIO_FN_SCIF0_TXD, NULL); gpio_request(GPIO_FN_SCIF0_RXD, NULL); /* enable debug LED */ gpio_request(GPIO_PTG0, NULL); gpio_request(GPIO_PTG1, NULL); gpio_request(GPIO_PTG2, NULL); gpio_request(GPIO_PTG3, NULL); gpio_direction_output(GPIO_PTG0, 0); gpio_direction_output(GPIO_PTG1, 0); gpio_direction_output(GPIO_PTG2, 0); gpio_direction_output(GPIO_PTG3, 0); __raw_writew((__raw_readw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA); /* enable SH-Eth */ gpio_request(GPIO_PTA1, NULL); gpio_direction_output(GPIO_PTA1, 1); mdelay(20); gpio_request(GPIO_FN_RMII_RXD0, NULL); gpio_request(GPIO_FN_RMII_RXD1, NULL); gpio_request(GPIO_FN_RMII_TXD0, NULL); gpio_request(GPIO_FN_RMII_TXD1, NULL); gpio_request(GPIO_FN_RMII_REF_CLK, NULL); gpio_request(GPIO_FN_RMII_TX_EN, NULL); gpio_request(GPIO_FN_RMII_RX_ER, NULL); gpio_request(GPIO_FN_RMII_CRS_DV, NULL); gpio_request(GPIO_FN_MDIO, NULL); gpio_request(GPIO_FN_MDC, NULL); gpio_request(GPIO_FN_LNKSTA, NULL); /* enable USB */ __raw_writew(0x0000, 0xA4D80000); __raw_writew(0x0000, 0xA4D90000); gpio_request(GPIO_PTB3, NULL); gpio_request(GPIO_PTB4, NULL); gpio_request(GPIO_PTB5, NULL); gpio_direction_input(GPIO_PTB3); gpio_direction_output(GPIO_PTB4, 0); gpio_direction_output(GPIO_PTB5, 0); __raw_writew(0x0600, 0xa40501d4); __raw_writew(0x0600, 0xa4050192); if (gpio_get_value(GPIO_PTB3)) { printk(KERN_INFO "USB1 function is selected\n"); usb1_common_device.name = "r8a66597_udc"; } else { printk(KERN_INFO "USB1 host is selected\n"); usb1_common_device.name = "r8a66597_hcd"; } /* enable LCDC */ gpio_request(GPIO_FN_LCDD23, NULL); gpio_request(GPIO_FN_LCDD22, NULL); gpio_request(GPIO_FN_LCDD21, NULL); gpio_request(GPIO_FN_LCDD20, NULL); gpio_request(GPIO_FN_LCDD19, NULL); gpio_request(GPIO_FN_LCDD18, NULL); gpio_request(GPIO_FN_LCDD17, NULL); gpio_request(GPIO_FN_LCDD16, NULL); gpio_request(GPIO_FN_LCDD15, NULL); gpio_request(GPIO_FN_LCDD14, NULL); gpio_request(GPIO_FN_LCDD13, NULL); gpio_request(GPIO_FN_LCDD12, NULL); gpio_request(GPIO_FN_LCDD11, NULL); gpio_request(GPIO_FN_LCDD10, NULL); gpio_request(GPIO_FN_LCDD9, NULL); gpio_request(GPIO_FN_LCDD8, NULL); gpio_request(GPIO_FN_LCDD7, NULL); gpio_request(GPIO_FN_LCDD6, NULL); gpio_request(GPIO_FN_LCDD5, NULL); gpio_request(GPIO_FN_LCDD4, NULL); gpio_request(GPIO_FN_LCDD3, NULL); gpio_request(GPIO_FN_LCDD2, NULL); gpio_request(GPIO_FN_LCDD1, NULL); gpio_request(GPIO_FN_LCDD0, NULL); gpio_request(GPIO_FN_LCDDISP, NULL); gpio_request(GPIO_FN_LCDHSYN, NULL); gpio_request(GPIO_FN_LCDDCK, NULL); gpio_request(GPIO_FN_LCDVSYN, NULL); gpio_request(GPIO_FN_LCDDON, NULL); gpio_request(GPIO_FN_LCDLCLK, NULL); __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA); gpio_request(GPIO_PTE6, NULL); gpio_request(GPIO_PTU1, NULL); gpio_request(GPIO_PTA2, NULL); gpio_direction_input(GPIO_PTE6); gpio_direction_output(GPIO_PTU1, 0); gpio_direction_output(GPIO_PTA2, 0); /* I/O buffer drive ability is high */ __raw_writew((__raw_readw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA); if (gpio_get_value(GPIO_PTE6)) { /* DVI */ lcdc_info.clock_source = LCDC_CLK_EXTERNAL; lcdc_info.ch[0].clock_divider = 1; lcdc_info.ch[0].lcd_modes = ecovec_dvi_modes; lcdc_info.ch[0].num_modes = ARRAY_SIZE(ecovec_dvi_modes); /* No backlight */ gpio_backlight_data.fbdev = NULL; gpio_set_value(GPIO_PTA2, 1); gpio_set_value(GPIO_PTU1, 1); } else { /* Panel */ lcdc_info.clock_source = LCDC_CLK_PERIPHERAL; lcdc_info.ch[0].clock_divider = 2; lcdc_info.ch[0].lcd_modes = ecovec_lcd_modes; lcdc_info.ch[0].num_modes = ARRAY_SIZE(ecovec_lcd_modes); /* FIXME * * LCDDON control is needed for Panel, * but current sh_mobile_lcdc driver doesn't control it. * It is temporary correspondence */ gpio_request(GPIO_PTF4, NULL); gpio_direction_output(GPIO_PTF4, 1); /* enable TouchScreen */ i2c_register_board_info(0, &ts_i2c_clients, 1); irq_set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW); } /* enable CEU0 */ gpio_request(GPIO_FN_VIO0_D15, NULL); gpio_request(GPIO_FN_VIO0_D14, NULL); gpio_request(GPIO_FN_VIO0_D13, NULL); gpio_request(GPIO_FN_VIO0_D12, NULL); gpio_request(GPIO_FN_VIO0_D11, NULL); gpio_request(GPIO_FN_VIO0_D10, NULL); gpio_request(GPIO_FN_VIO0_D9, NULL); gpio_request(GPIO_FN_VIO0_D8, NULL); gpio_request(GPIO_FN_VIO0_D7, NULL); gpio_request(GPIO_FN_VIO0_D6, NULL); gpio_request(GPIO_FN_VIO0_D5, NULL); gpio_request(GPIO_FN_VIO0_D4, NULL); gpio_request(GPIO_FN_VIO0_D3, NULL); gpio_request(GPIO_FN_VIO0_D2, NULL); gpio_request(GPIO_FN_VIO0_D1, NULL); gpio_request(GPIO_FN_VIO0_D0, NULL); gpio_request(GPIO_FN_VIO0_VD, NULL); gpio_request(GPIO_FN_VIO0_CLK, NULL); gpio_request(GPIO_FN_VIO0_FLD, NULL); gpio_request(GPIO_FN_VIO0_HD, NULL); /* enable CEU1 */ gpio_request(GPIO_FN_VIO1_D7, NULL); gpio_request(GPIO_FN_VIO1_D6, NULL); gpio_request(GPIO_FN_VIO1_D5, NULL); gpio_request(GPIO_FN_VIO1_D4, NULL); gpio_request(GPIO_FN_VIO1_D3, NULL); gpio_request(GPIO_FN_VIO1_D2, NULL); gpio_request(GPIO_FN_VIO1_D1, NULL); gpio_request(GPIO_FN_VIO1_D0, NULL); gpio_request(GPIO_FN_VIO1_FLD, NULL); gpio_request(GPIO_FN_VIO1_HD, NULL); gpio_request(GPIO_FN_VIO1_VD, NULL); gpio_request(GPIO_FN_VIO1_CLK, NULL); /* enable KEYSC */ gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); gpio_request(GPIO_FN_KEYOUT3, NULL); gpio_request(GPIO_FN_KEYOUT2, NULL); gpio_request(GPIO_FN_KEYOUT1, NULL); gpio_request(GPIO_FN_KEYOUT0, NULL); gpio_request(GPIO_FN_KEYIN0, NULL); /* enable user debug switch */ gpio_request(GPIO_PTR0, NULL); gpio_request(GPIO_PTR4, NULL); gpio_request(GPIO_PTR5, NULL); gpio_request(GPIO_PTR6, NULL); gpio_direction_input(GPIO_PTR0); gpio_direction_input(GPIO_PTR4); gpio_direction_input(GPIO_PTR5); gpio_direction_input(GPIO_PTR6); /* SD-card slot CN11 */ #if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE) /* enable SDHI0 on CN11 (needs DS2.4 set to ON) */ gpio_request(GPIO_FN_SDHI0WP, NULL); gpio_request(GPIO_FN_SDHI0CMD, NULL); gpio_request(GPIO_FN_SDHI0CLK, NULL); gpio_request(GPIO_FN_SDHI0D3, NULL); gpio_request(GPIO_FN_SDHI0D2, NULL); gpio_request(GPIO_FN_SDHI0D1, NULL); gpio_request(GPIO_FN_SDHI0D0, NULL); #else /* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */ gpio_request(GPIO_FN_MSIOF0_TXD, NULL); gpio_request(GPIO_FN_MSIOF0_RXD, NULL); gpio_request(GPIO_FN_MSIOF0_TSCK, NULL); gpio_request(GPIO_PTM4, NULL); /* software CS control of TSYNC pin */ gpio_direction_output(GPIO_PTM4, 1); /* active low CS */ gpio_request(GPIO_PTB6, NULL); /* 3.3V power control */ gpio_direction_output(GPIO_PTB6, 0); /* disable power by default */ spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus)); #endif /* MMC/SD-card slot CN12 */ #if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE) /* enable MMCIF (needs DS2.6,7 set to OFF,ON) */ gpio_request(GPIO_FN_MMC_D7, NULL); gpio_request(GPIO_FN_MMC_D6, NULL); gpio_request(GPIO_FN_MMC_D5, NULL); gpio_request(GPIO_FN_MMC_D4, NULL); gpio_request(GPIO_FN_MMC_D3, NULL); gpio_request(GPIO_FN_MMC_D2, NULL); gpio_request(GPIO_FN_MMC_D1, NULL); gpio_request(GPIO_FN_MMC_D0, NULL); gpio_request(GPIO_FN_MMC_CLK, NULL); gpio_request(GPIO_FN_MMC_CMD, NULL); cn12_enabled = true; #elif defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE) /* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */ gpio_request(GPIO_FN_SDHI1WP, NULL); gpio_request(GPIO_FN_SDHI1CMD, NULL); gpio_request(GPIO_FN_SDHI1CLK, NULL); gpio_request(GPIO_FN_SDHI1D3, NULL); gpio_request(GPIO_FN_SDHI1D2, NULL); gpio_request(GPIO_FN_SDHI1D1, NULL); gpio_request(GPIO_FN_SDHI1D0, NULL); cn12_enabled = true; #endif if (cn12_enabled) /* I/O buffer drive ability is high for CN12 */ __raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000, IODRIVEA); /* enable FSI */ gpio_request(GPIO_FN_FSIMCKB, NULL); gpio_request(GPIO_FN_FSIIBSD, NULL); gpio_request(GPIO_FN_FSIOBSD, NULL); gpio_request(GPIO_FN_FSIIBBCK, NULL); gpio_request(GPIO_FN_FSIIBLRCK, NULL); gpio_request(GPIO_FN_FSIOBBCK, NULL); gpio_request(GPIO_FN_FSIOBLRCK, NULL); gpio_request(GPIO_FN_CLKAUDIOBO, NULL); /* set SPU2 clock to 83.4 MHz */ clk = clk_get(NULL, "spu_clk"); if (!IS_ERR(clk)) { clk_set_rate(clk, clk_round_rate(clk, 83333333)); clk_put(clk); } /* change parent of FSI B */ clk = clk_get(NULL, "fsib_clk"); if (!IS_ERR(clk)) { /* 48kHz dummy clock was used to make sure 1/1 divide */ clk_set_rate(&sh7724_fsimckb_clk, 48000); clk_set_parent(clk, &sh7724_fsimckb_clk); clk_set_rate(clk, 48000); clk_put(clk); } gpio_request(GPIO_PTU0, NULL); gpio_direction_output(GPIO_PTU0, 0); mdelay(20); /* enable motion sensor */ gpio_request(GPIO_FN_INTC_IRQ1, NULL); gpio_direction_input(GPIO_FN_INTC_IRQ1); /* set VPU clock to 166 MHz */ clk = clk_get(NULL, "vpu_clk"); if (!IS_ERR(clk)) { clk_set_rate(clk, clk_round_rate(clk, 166000000)); clk_put(clk); } /* enable IrDA */ gpio_request(GPIO_FN_IRDA_OUT, NULL); gpio_request(GPIO_FN_IRDA_IN, NULL); gpio_request(GPIO_PTU5, NULL); gpio_direction_output(GPIO_PTU5, 0); /* Register gpio lookup tables for cameras and video decoder */ gpiod_add_lookup_table(&tw9910_gpios); gpiod_add_lookup_table(&mt9t112_0_gpios); gpiod_add_lookup_table(&mt9t112_1_gpios); /* enable I2C device */ i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices)); i2c_register_board_info(1, i2c1_devices, ARRAY_SIZE(i2c1_devices)); #if defined(CONFIG_VIDEO_SH_VOU) || defined(CONFIG_VIDEO_SH_VOU_MODULE) /* VOU */ gpio_request(GPIO_FN_DV_D15, NULL); gpio_request(GPIO_FN_DV_D14, NULL); gpio_request(GPIO_FN_DV_D13, NULL); gpio_request(GPIO_FN_DV_D12, NULL); gpio_request(GPIO_FN_DV_D11, NULL); gpio_request(GPIO_FN_DV_D10, NULL); gpio_request(GPIO_FN_DV_D9, NULL); gpio_request(GPIO_FN_DV_D8, NULL); gpio_request(GPIO_FN_DV_CLKI, NULL); gpio_request(GPIO_FN_DV_CLK, NULL); gpio_request(GPIO_FN_DV_VSYNC, NULL); gpio_request(GPIO_FN_DV_HSYNC, NULL); /* AK8813 power / reset sequence */ gpio_request(GPIO_PTG4, NULL); gpio_request(GPIO_PTU3, NULL); /* Reset */ gpio_direction_output(GPIO_PTG4, 0); /* Power down */ gpio_direction_output(GPIO_PTU3, 1); udelay(10); /* Power up, reset */ gpio_set_value(GPIO_PTU3, 0); udelay(10); /* Remove reset */ gpio_set_value(GPIO_PTG4, 1); #endif /* Initialize CEU platform devices separately to map memory first */ device_initialize(&ecovec_ceu_devices[0]->dev); arch_setup_pdev_archdata(ecovec_ceu_devices[0]); dma_declare_coherent_memory(&ecovec_ceu_devices[0]->dev, ceu0_dma_membase, ceu0_dma_membase, ceu0_dma_membase + CEU_BUFFER_MEMORY_SIZE - 1, DMA_MEMORY_EXCLUSIVE); platform_device_add(ecovec_ceu_devices[0]); device_initialize(&ecovec_ceu_devices[1]->dev); arch_setup_pdev_archdata(ecovec_ceu_devices[1]); dma_declare_coherent_memory(&ecovec_ceu_devices[1]->dev, ceu1_dma_membase, ceu1_dma_membase, ceu1_dma_membase + CEU_BUFFER_MEMORY_SIZE - 1, DMA_MEMORY_EXCLUSIVE); platform_device_add(ecovec_ceu_devices[1]); gpiod_add_lookup_table(&cn12_power_gpiod_table); #if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE) gpiod_add_lookup_table(&sdhi0_power_gpiod_table); #endif return platform_add_devices(ecovec_devices, ARRAY_SIZE(ecovec_devices)); }
/** * vpfe_probe : vpfe probe function * @pdev: platform device pointer * * This function creates device entries by register itself to the V4L2 driver * and initializes fields of each device objects */ static __devinit int vpfe_probe(struct platform_device *pdev) { struct vpfe_config *vpfe_cfg; struct resource *res1; struct vpfe_device *vpfe_dev; int ret = -ENOMEM, err; unsigned long phys_end_kernel; size_t size; /* Get the pointer to the device object */ vpfe_dev = vpfe_initialize(); if (!vpfe_dev) { v4l2_err(pdev->dev.driver, "Failed to allocate memory for vpfe_dev\n"); return ret; } vpfe_dev->pdev = &pdev->dev; if (cont_bufsize) { /* attempt to determine the end of Linux kernel memory */ phys_end_kernel = virt_to_phys((void *)PAGE_OFFSET) + (num_physpages << PAGE_SHIFT); size = cont_bufsize; phys_end_kernel += cont_bufoffset; err = dma_declare_coherent_memory(&pdev->dev, phys_end_kernel, phys_end_kernel, size, DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); if (!err) { dev_err(&pdev->dev, "Unable to declare MMAP memory.\n"); ret = -ENOENT; goto probe_free_dev_mem; } vpfe_dev->config_params.video_limit = size; } if (NULL == pdev->dev.platform_data) { v4l2_err(pdev->dev.driver, "Unable to get vpfe config\n"); ret = -ENOENT; goto probe_free_dev_mem; } vpfe_cfg = pdev->dev.platform_data; vpfe_dev->cfg = vpfe_cfg; if (NULL == vpfe_cfg->card_name || NULL == vpfe_cfg->sub_devs) { v4l2_err(pdev->dev.driver, "null ptr in vpfe_cfg\n"); ret = -ENOENT; goto probe_free_dev_mem; } /* enable vpss clocks */ ret = vpfe_enable_clock(vpfe_dev); if (ret) goto probe_free_dev_mem; mutex_lock(&ccdc_lock); if (vpfe_initialize_modules(vpfe_dev, pdev)) goto probe_disable_clock; /* Get VINT0 irq resource */ res1 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (!res1) { v4l2_err(pdev->dev.driver, "Unable to get interrupt for VINT0\n"); ret = -ENOENT; goto probe_out_ccdc_cleanup; } vpfe_dev->ccdc_irq0 = res1->start; /* Get VINT1 irq resource */ res1 = platform_get_resource(pdev, IORESOURCE_IRQ, 1); if (!res1) { v4l2_err(pdev->dev.driver, "Unable to get interrupt for VINT1\n"); ret = -ENOENT; goto probe_out_ccdc_cleanup; } vpfe_dev->ccdc_irq1 = res1->start; /* Get PRVUINT irq resource */ res1 = platform_get_resource(pdev, IORESOURCE_IRQ, 2); if (!res1) { v4l2_err(pdev->dev.driver, "Unable to get interrupt for PRVUINT\n"); ret = -ENOENT; goto probe_out_ccdc_cleanup; } vpfe_dev->imp_dma_irq = res1->start; vpfe_dev->media_dev.dev = vpfe_dev->pdev; strcpy((char *)&vpfe_dev->media_dev.model, "davinci-media"); ret = media_device_register(&vpfe_dev->media_dev); if (ret) goto probe_out_ccdc_cleanup; vpfe_dev->v4l2_dev.mdev = &vpfe_dev->media_dev; ret = v4l2_device_register(&pdev->dev, &vpfe_dev->v4l2_dev); if (ret) { v4l2_err(pdev->dev.driver, "Unable to register v4l2 device.\n"); goto probe_out_video_release; } v4l2_info(&vpfe_dev->v4l2_dev, "v4l2 device registered\n"); /* register video device */ v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "trying to register vpfe device.\n"); /* set the driver data in platform device */ platform_set_drvdata(pdev, vpfe_dev); /* register subdevs/entities */ if (vpfe_register_entities(vpfe_dev)) goto probe_out_video_unregister; ret = vpfe_attach_irq(vpfe_dev); if (ret) goto probe_out_register_entities; mutex_unlock(&ccdc_lock); return 0; probe_out_register_entities: vpfe_register_entities(vpfe_dev); probe_out_video_unregister: /*TODO we need this?*/ probe_out_video_release: /*TODO we need this?*/ probe_out_ccdc_cleanup: vpfe_cleanup_modules(vpfe_dev, pdev); probe_disable_clock: vpfe_disable_clock(vpfe_dev); mutex_unlock(&ccdc_lock); probe_free_dev_mem: kzfree(vpfe_dev); return ret; }
static int mb_remoteproc_probe(struct platform_device *pdev) { const unsigned char *prop; struct platform_device *bram_pdev; struct device_node *bram_dev; struct resource *res; /* IO mem resources */ int ret = 0; int count = 0; struct mb_rproc_pdata *local; local = devm_kzalloc(&pdev->dev, sizeof(*local), GFP_KERNEL); if (!local) return -ENOMEM; platform_set_drvdata(pdev, local); /* Declare memory for firmware */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(&pdev->dev, "invalid address\n"); return -ENODEV; } local->mem_start = res->start; local->mem_end = res->end; /* Alloc phys addr from 0 to max_addr for firmware */ ret = dma_declare_coherent_memory(&pdev->dev, local->mem_start, local->mem_start, local->mem_end - local->mem_start + 1, DMA_MEMORY_IO); if (!ret) { dev_err(&pdev->dev, "dma_declare_coherent_memory failed\n"); return -ENOMEM; } ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); if (ret) { dev_err(&pdev->dev, "dma_set_coherent_mask: %d\n", ret); goto dma_mask_fault; } /* Alloc IRQ based on DTS to be sure that no other driver will use it */ while (1) { int irq; /* Allocating shared IRQs will ensure that any module will * use these IRQs */ irq = platform_get_irq(pdev, count++); if (irq == -ENXIO || irq == -EINVAL) break; ret = devm_request_irq(&pdev->dev, irq, mb_remoteproc_interrupt, 0, dev_name(&pdev->dev), &pdev->dev); if (ret) { dev_err(&pdev->dev, "IRQ %d already allocated\n", irq); goto dma_mask_fault; } dev_info(&pdev->dev, "%d: Alloc irq: %d\n", count, irq); } /* Find out reset gpio and keep microblaze in reset */ local->reset_gpio = of_get_named_gpio(pdev->dev.of_node, "reset", 0); if (local->reset_gpio < 0) { dev_err(&pdev->dev, "reset-gpio property not found\n"); ret = local->reset_gpio; goto dma_mask_fault; } ret = devm_gpio_request_one(&pdev->dev, local->reset_gpio, GPIOF_OUT_INIT_HIGH, "mb_reset"); if (ret) { dev_err(&pdev->dev, "Please specify gpio reset addr\n"); goto dma_mask_fault; } /* Find out reset gpio and keep microblaze in reset */ local->mb_debug_gpio = of_get_named_gpio(pdev->dev.of_node, "debug", 0); if (local->mb_debug_gpio < 0) { dev_err(&pdev->dev, "mb-debug-gpio property not found\n"); ret = local->mb_debug_gpio; goto dma_mask_fault; } ret = devm_gpio_request_one(&pdev->dev, local->mb_debug_gpio, GPIOF_OUT_INIT_LOW, "mb_debug"); if (ret) { dev_err(&pdev->dev, "Please specify gpio debug pin\n"); goto dma_mask_fault; } /* IPI number for getting irq from firmware */ local->ipi = of_get_named_gpio(pdev->dev.of_node, "ipino", 0); if (local->ipi < 0) { dev_err(&pdev->dev, "ipi-gpio property not found\n"); ret = local->ipi; goto dma_mask_fault; } ret = devm_gpio_request_one(&pdev->dev, local->ipi, GPIOF_IN, "mb_ipi"); if (ret) { dev_err(&pdev->dev, "Please specify gpio reset addr\n"); goto dma_mask_fault; } ret = devm_request_irq(&pdev->dev, gpio_to_irq(local->ipi), ipi_kick, IRQF_SHARED|IRQF_TRIGGER_RISING, dev_name(&pdev->dev), local); if (ret) { dev_err(&pdev->dev, "IRQ %d already allocated\n", local->ipi); goto dma_mask_fault; } /* Find out vring0 pin */ local->vring0 = of_get_named_gpio(pdev->dev.of_node, "vring0", 0); if (local->vring0 < 0) { dev_err(&pdev->dev, "reset-gpio property not found\n"); ret = local->vring0; goto dma_mask_fault; } ret = devm_gpio_request_one(&pdev->dev, local->vring0, GPIOF_DIR_OUT, "mb_vring0"); if (ret) { dev_err(&pdev->dev, "Please specify gpio reset addr\n"); goto dma_mask_fault; } /* Find out vring1 pin */ local->vring1 = of_get_named_gpio(pdev->dev.of_node, "vring1", 0); if (local->vring1 < 0) { dev_err(&pdev->dev, "reset-gpio property not found\n"); ret = local->vring1; goto dma_mask_fault; } ret = devm_gpio_request_one(&pdev->dev, local->vring1, GPIOF_DIR_OUT, "mb_vring1"); if (ret) { dev_err(&pdev->dev, "Please specify gpio reset addr\n"); goto dma_mask_fault; } /* Allocate bram device */ bram_dev = of_parse_phandle(pdev->dev.of_node, "bram", 0); if (!bram_dev) { dev_err(&pdev->dev, "Please specify bram connection\n"); ret = -ENODEV; goto dma_mask_fault; } bram_pdev = of_find_device_by_node(bram_dev); if (!bram_pdev) { dev_err(&pdev->dev, "BRAM device hasn't found\n"); ret = -ENODEV; goto dma_mask_fault; } res = platform_get_resource(bram_pdev, IORESOURCE_MEM, 0); local->vbase = devm_ioremap_resource(&pdev->dev, res); if (!local->vbase) { ret = -ENODEV; goto dma_mask_fault; } /* Load simple bootloader to bram */ local->bootloader = of_get_property(pdev->dev.of_node, "bram-firmware", NULL); if (!local->bootloader) { dev_err(&pdev->dev, "Please specify BRAM firmware\n"); ret = -ENODEV; goto dma_mask_fault; } dev_info(&pdev->dev, "Using microblaze BRAM bootloader: %s\n", local->bootloader); /* Module param firmware first */ if (firmware) prop = firmware; else prop = of_get_property(pdev->dev.of_node, "firmware", NULL); if (prop) { dev_info(&pdev->dev, "Using firmware: %s\n", prop); local->rproc = rproc_alloc(&pdev->dev, dev_name(&pdev->dev), &mb_rproc_ops, prop, sizeof(struct rproc)); if (!local->rproc) { dev_err(&pdev->dev, "rproc allocation failed\n"); ret = -ENODEV; goto dma_mask_fault; } ret = rproc_add(local->rproc); if (ret) { dev_err(&pdev->dev, "rproc registration failed\n"); rproc_put(local->rproc); goto dma_mask_fault; } return 0; } else { ret = -ENODEV; } dma_mask_fault: dma_release_declared_memory(&pdev->dev); return ret; }
static int __devinit sh_mobile_ceu_probe(struct platform_device *pdev) { struct sh_mobile_ceu_dev *pcdev; struct resource *res; void __iomem *base; unsigned int irq; int err = 0; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); irq = platform_get_irq(pdev, 0); if (!res || !irq) { dev_err(&pdev->dev, "Not enough CEU platform resources.\n"); err = -ENODEV; goto exit; } pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); if (!pcdev) { dev_err(&pdev->dev, "Could not allocate pcdev\n"); err = -ENOMEM; goto exit; } INIT_LIST_HEAD(&pcdev->capture); spin_lock_init(&pcdev->lock); pcdev->pdata = pdev->dev.platform_data; if (!pcdev->pdata) { err = -EINVAL; dev_err(&pdev->dev, "CEU platform data not set.\n"); goto exit_kfree; } base = ioremap_nocache(res->start, resource_size(res)); if (!base) { err = -ENXIO; dev_err(&pdev->dev, "Unable to ioremap CEU registers.\n"); goto exit_kfree; } pcdev->irq = irq; pcdev->base = base; pcdev->video_limit = 0; res = platform_get_resource(pdev, IORESOURCE_MEM, 1); if (res) { err = dma_declare_coherent_memory(&pdev->dev, res->start, res->start, resource_size(res), DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); if (!err) { dev_err(&pdev->dev, "Unable to declare CEU memory.\n"); err = -ENXIO; goto exit_iounmap; } pcdev->video_limit = resource_size(res); } err = request_irq(pcdev->irq, sh_mobile_ceu_irq, IRQF_DISABLED, dev_name(&pdev->dev), pcdev); if (err) { dev_err(&pdev->dev, "Unable to register CEU interrupt.\n"); goto exit_release_mem; } pm_suspend_ignore_children(&pdev->dev, true); pm_runtime_enable(&pdev->dev); pm_runtime_resume(&pdev->dev); pcdev->ici.priv = pcdev; pcdev->ici.v4l2_dev.dev = &pdev->dev; pcdev->ici.nr = pdev->id; pcdev->ici.drv_name = dev_name(&pdev->dev); pcdev->ici.ops = &sh_mobile_ceu_host_ops; err = soc_camera_host_register(&pcdev->ici); if (err) goto exit_free_clk; return 0; exit_free_clk: pm_runtime_disable(&pdev->dev); free_irq(pcdev->irq, pcdev); exit_release_mem: if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) dma_release_declared_memory(&pdev->dev); exit_iounmap: iounmap(base); exit_kfree: kfree(pcdev); exit: return err; }
int __init p7_init_dma(void) { int err; int const rev = p7_chiprev(); pr_debug("p7: registering %s...\n", p7_dma_dev.dev.init_name); if (rev == P7_CHIPREV_R1) { /* P7 first revision initializes DMA controller in non secure mode * when coming out of reset but it is not possible to switch back to * secure mode. Since Linux / cores / L2 cache controller run in * secure mode, and all DMA controller transactions going through ACP * port are flagged as non secure, CPU and DMA accesses to the same * address won't point to same L2 cache internal location. * Therefore, we must disable DMA RAM to RAM ACP accesses (and * bypass L2 cache) to perform transactions directly onto main AXI * system bus (the one behind L2 cache). */ #define P7_NIC_REMAP P7_NIC #define NIC_NOACP (1U << 7) __raw_writel(NIC_NOACP, MMIO_P2V(P7_NIC_REMAP)); /* On R1, DMA interrupts are not shared */ p7_dma_dev.irq[0] = P7_R1_DMA_ABORT_IRQ; p7_dma_dev.irq[1] = P7_R1_DMA5_IRQ; p7_dma_pdata.flushp = true; } else if (rev == P7_CHIPREV_R2 || rev == P7_CHIPREV_R3) { /* * P7_NIC_REMAP is write-only, we can't check the REMAP_DRAM bit * value. The assumption is made that it is already set at this point, * so we add it to our bitmask. */ #define NIC_REMAP_DRAM (1U) __raw_writel(NIC_REMAP_DRAM | NIC_NOACP, MMIO_P2V(P7_NIC_REMAP)); p7_dma_pdata.flushp = true; } dma_cap_set(DMA_MEMCPY, p7_dma_pdata.cap_mask); dma_cap_set(DMA_SLAVE, p7_dma_pdata.cap_mask); dma_cap_set(DMA_CYCLIC, p7_dma_pdata.cap_mask); err = amba_device_register(&p7_dma_dev, &iomem_resource); if (err) panic("p7: failed to register %s (%d)\n", p7_dma_dev.dev.init_name, err); /* * We want to store controller microcode into internal RAM for performance * reasons. * As amba_device holds a single resource and pl330 driver does not handle * multiple memory resources, we have to reserve microcode memory region here. * Related device must have been initialized (amba_device_register) before * using dma_declare_coherent_memory. * Moreover, dma_declare_coherent_memory must be performed before pl330 * driver loaded since it allocates microcode region at probing time. */ if (! (dma_declare_coherent_memory(&p7_dma_dev.dev, p7_dma_ucode_addr(), p7_dma_ucode_addr(), p7_dma_ucode_sz(), DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) & DMA_MEMORY_MAP)) /* Failure: will use DMA zone located in system RAM. */ panic("p7: failed to map DMA controller microcode memory region [%08x:%08x]\n", p7_dma_ucode_addr(), p7_dma_ucode_addr() + p7_dma_ucode_sz() - 1); dev_info(&p7_dma_dev.dev, "mapped microcode memory region [%08x:%08x]\n", p7_dma_ucode_addr(), p7_dma_ucode_addr() + p7_dma_ucode_sz() - 1); return 0; }
static int __init devices_setup(void) { u16 sw = __raw_readw(SW4140); /* select camera, monitor */ struct clk *clk; u16 fpga_out; /* register board specific self-refresh code */ sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF | SUSP_SH_RSTANDBY, &ms7724se_sdram_enter_start, &ms7724se_sdram_enter_end, &ms7724se_sdram_leave_start, &ms7724se_sdram_leave_end); regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, ARRAY_SIZE(fixed3v3_power_consumers), 3300000); /* Reset Release */ fpga_out = __raw_readw(FPGA_OUT); /* bit4: NTSC_PDN, bit5: NTSC_RESET */ fpga_out &= ~((1 << 1) | /* LAN */ (1 << 4) | /* AK8813 PDN */ (1 << 5) | /* AK8813 RESET */ (1 << 6) | /* VIDEO DAC */ (1 << 7) | /* AK4643 */ (1 << 8) | /* IrDA */ (1 << 12) | /* USB0 */ (1 << 14)); /* RMII */ __raw_writew(fpga_out | (1 << 4), FPGA_OUT); udelay(10); /* AK8813 RESET */ __raw_writew(fpga_out | (1 << 5), FPGA_OUT); udelay(10); __raw_writew(fpga_out, FPGA_OUT); /* turn on USB clocks, use external clock */ __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB); /* Let LED9 show STATUS2 */ gpio_request(GPIO_FN_STATUS2, NULL); /* Lit LED10 show STATUS0 */ gpio_request(GPIO_FN_STATUS0, NULL); /* Lit LED11 show PDSTATUS */ gpio_request(GPIO_FN_PDSTATUS, NULL); /* enable USB0 port */ __raw_writew(0x0600, 0xa40501d4); /* enable USB1 port */ __raw_writew(0x0600, 0xa4050192); /* enable IRQ 0,1,2 */ gpio_request(GPIO_FN_INTC_IRQ0, NULL); gpio_request(GPIO_FN_INTC_IRQ1, NULL); gpio_request(GPIO_FN_INTC_IRQ2, NULL); /* enable SCIFA3 */ gpio_request(GPIO_FN_SCIF3_I_SCK, NULL); gpio_request(GPIO_FN_SCIF3_I_RXD, NULL); gpio_request(GPIO_FN_SCIF3_I_TXD, NULL); gpio_request(GPIO_FN_SCIF3_I_CTS, NULL); gpio_request(GPIO_FN_SCIF3_I_RTS, NULL); /* enable LCDC */ gpio_request(GPIO_FN_LCDD23, NULL); gpio_request(GPIO_FN_LCDD22, NULL); gpio_request(GPIO_FN_LCDD21, NULL); gpio_request(GPIO_FN_LCDD20, NULL); gpio_request(GPIO_FN_LCDD19, NULL); gpio_request(GPIO_FN_LCDD18, NULL); gpio_request(GPIO_FN_LCDD17, NULL); gpio_request(GPIO_FN_LCDD16, NULL); gpio_request(GPIO_FN_LCDD15, NULL); gpio_request(GPIO_FN_LCDD14, NULL); gpio_request(GPIO_FN_LCDD13, NULL); gpio_request(GPIO_FN_LCDD12, NULL); gpio_request(GPIO_FN_LCDD11, NULL); gpio_request(GPIO_FN_LCDD10, NULL); gpio_request(GPIO_FN_LCDD9, NULL); gpio_request(GPIO_FN_LCDD8, NULL); gpio_request(GPIO_FN_LCDD7, NULL); gpio_request(GPIO_FN_LCDD6, NULL); gpio_request(GPIO_FN_LCDD5, NULL); gpio_request(GPIO_FN_LCDD4, NULL); gpio_request(GPIO_FN_LCDD3, NULL); gpio_request(GPIO_FN_LCDD2, NULL); gpio_request(GPIO_FN_LCDD1, NULL); gpio_request(GPIO_FN_LCDD0, NULL); gpio_request(GPIO_FN_LCDDISP, NULL); gpio_request(GPIO_FN_LCDHSYN, NULL); gpio_request(GPIO_FN_LCDDCK, NULL); gpio_request(GPIO_FN_LCDVSYN, NULL); gpio_request(GPIO_FN_LCDDON, NULL); gpio_request(GPIO_FN_LCDVEPWC, NULL); gpio_request(GPIO_FN_LCDVCPWC, NULL); gpio_request(GPIO_FN_LCDRD, NULL); gpio_request(GPIO_FN_LCDLCLK, NULL); __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA); /* enable CEU0 */ gpio_request(GPIO_FN_VIO0_D15, NULL); gpio_request(GPIO_FN_VIO0_D14, NULL); gpio_request(GPIO_FN_VIO0_D13, NULL); gpio_request(GPIO_FN_VIO0_D12, NULL); gpio_request(GPIO_FN_VIO0_D11, NULL); gpio_request(GPIO_FN_VIO0_D10, NULL); gpio_request(GPIO_FN_VIO0_D9, NULL); gpio_request(GPIO_FN_VIO0_D8, NULL); gpio_request(GPIO_FN_VIO0_D7, NULL); gpio_request(GPIO_FN_VIO0_D6, NULL); gpio_request(GPIO_FN_VIO0_D5, NULL); gpio_request(GPIO_FN_VIO0_D4, NULL); gpio_request(GPIO_FN_VIO0_D3, NULL); gpio_request(GPIO_FN_VIO0_D2, NULL); gpio_request(GPIO_FN_VIO0_D1, NULL); gpio_request(GPIO_FN_VIO0_D0, NULL); gpio_request(GPIO_FN_VIO0_VD, NULL); gpio_request(GPIO_FN_VIO0_CLK, NULL); gpio_request(GPIO_FN_VIO0_FLD, NULL); gpio_request(GPIO_FN_VIO0_HD, NULL); /* enable CEU1 */ gpio_request(GPIO_FN_VIO1_D7, NULL); gpio_request(GPIO_FN_VIO1_D6, NULL); gpio_request(GPIO_FN_VIO1_D5, NULL); gpio_request(GPIO_FN_VIO1_D4, NULL); gpio_request(GPIO_FN_VIO1_D3, NULL); gpio_request(GPIO_FN_VIO1_D2, NULL); gpio_request(GPIO_FN_VIO1_D1, NULL); gpio_request(GPIO_FN_VIO1_D0, NULL); gpio_request(GPIO_FN_VIO1_FLD, NULL); gpio_request(GPIO_FN_VIO1_HD, NULL); gpio_request(GPIO_FN_VIO1_VD, NULL); gpio_request(GPIO_FN_VIO1_CLK, NULL); /* KEYSC */ gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); gpio_request(GPIO_FN_KEYIN4, NULL); gpio_request(GPIO_FN_KEYIN3, NULL); gpio_request(GPIO_FN_KEYIN2, NULL); gpio_request(GPIO_FN_KEYIN1, NULL); gpio_request(GPIO_FN_KEYIN0, NULL); gpio_request(GPIO_FN_KEYOUT3, NULL); gpio_request(GPIO_FN_KEYOUT2, NULL); gpio_request(GPIO_FN_KEYOUT1, NULL); gpio_request(GPIO_FN_KEYOUT0, NULL); /* enable FSI */ gpio_request(GPIO_FN_FSIMCKA, NULL); gpio_request(GPIO_FN_FSIIASD, NULL); gpio_request(GPIO_FN_FSIOASD, NULL); gpio_request(GPIO_FN_FSIIABCK, NULL); gpio_request(GPIO_FN_FSIIALRCK, NULL); gpio_request(GPIO_FN_FSIOABCK, NULL); gpio_request(GPIO_FN_FSIOALRCK, NULL); gpio_request(GPIO_FN_CLKAUDIOAO, NULL); /* set SPU2 clock to 83.4 MHz */ clk = clk_get(NULL, "spu_clk"); if (!IS_ERR(clk)) { clk_set_rate(clk, clk_round_rate(clk, 83333333)); clk_put(clk); } /* change parent of FSI A */ clk = clk_get(NULL, "fsia_clk"); if (!IS_ERR(clk)) { /* 48kHz dummy clock was used to make sure 1/1 divide */ clk_set_rate(&sh7724_fsimcka_clk, 48000); clk_set_parent(clk, &sh7724_fsimcka_clk); clk_set_rate(clk, 48000); clk_put(clk); } /* SDHI0 connected to cn7 */ gpio_request(GPIO_FN_SDHI0CD, NULL); gpio_request(GPIO_FN_SDHI0WP, NULL); gpio_request(GPIO_FN_SDHI0D3, NULL); gpio_request(GPIO_FN_SDHI0D2, NULL); gpio_request(GPIO_FN_SDHI0D1, NULL); gpio_request(GPIO_FN_SDHI0D0, NULL); gpio_request(GPIO_FN_SDHI0CMD, NULL); gpio_request(GPIO_FN_SDHI0CLK, NULL); /* SDHI1 connected to cn8 */ gpio_request(GPIO_FN_SDHI1CD, NULL); gpio_request(GPIO_FN_SDHI1WP, NULL); gpio_request(GPIO_FN_SDHI1D3, NULL); gpio_request(GPIO_FN_SDHI1D2, NULL); gpio_request(GPIO_FN_SDHI1D1, NULL); gpio_request(GPIO_FN_SDHI1D0, NULL); gpio_request(GPIO_FN_SDHI1CMD, NULL); gpio_request(GPIO_FN_SDHI1CLK, NULL); /* enable IrDA */ gpio_request(GPIO_FN_IRDA_OUT, NULL); gpio_request(GPIO_FN_IRDA_IN, NULL); /* * enable SH-Eth * * please remove J33 pin from your board !! * * ms7724 board should not use GPIO_FN_LNKSTA pin * So, This time PTX5 is set to input pin */ gpio_request(GPIO_FN_RMII_RXD0, NULL); gpio_request(GPIO_FN_RMII_RXD1, NULL); gpio_request(GPIO_FN_RMII_TXD0, NULL); gpio_request(GPIO_FN_RMII_TXD1, NULL); gpio_request(GPIO_FN_RMII_REF_CLK, NULL); gpio_request(GPIO_FN_RMII_TX_EN, NULL); gpio_request(GPIO_FN_RMII_RX_ER, NULL); gpio_request(GPIO_FN_RMII_CRS_DV, NULL); gpio_request(GPIO_FN_MDIO, NULL); gpio_request(GPIO_FN_MDC, NULL); gpio_request(GPIO_PTX5, NULL); gpio_direction_input(GPIO_PTX5); sh_eth_init(); if (sw & SW41_B) { /* 720p */ lcdc_info.ch[0].lcd_modes = lcdc_720p_modes; lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_720p_modes); } else { /* VGA */ lcdc_info.ch[0].lcd_modes = lcdc_vga_modes; lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_vga_modes); } if (sw & SW41_A) { /* Digital monitor */ lcdc_info.ch[0].interface_type = RGB18; lcdc_info.ch[0].flags = 0; } else { /* Analog monitor */ lcdc_info.ch[0].interface_type = RGB24; lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL; } /* VOU */ gpio_request(GPIO_FN_DV_D15, NULL); gpio_request(GPIO_FN_DV_D14, NULL); gpio_request(GPIO_FN_DV_D13, NULL); gpio_request(GPIO_FN_DV_D12, NULL); gpio_request(GPIO_FN_DV_D11, NULL); gpio_request(GPIO_FN_DV_D10, NULL); gpio_request(GPIO_FN_DV_D9, NULL); gpio_request(GPIO_FN_DV_D8, NULL); gpio_request(GPIO_FN_DV_CLKI, NULL); gpio_request(GPIO_FN_DV_CLK, NULL); gpio_request(GPIO_FN_DV_VSYNC, NULL); gpio_request(GPIO_FN_DV_HSYNC, NULL); /* Initialize CEU platform devices separately to map memory first */ device_initialize(&ms7724se_ceu_devices[0]->dev); arch_setup_pdev_archdata(ms7724se_ceu_devices[0]); dma_declare_coherent_memory(&ms7724se_ceu_devices[0]->dev, ceu0_dma_membase, ceu0_dma_membase, ceu0_dma_membase + CEU_BUFFER_MEMORY_SIZE - 1); platform_device_add(ms7724se_ceu_devices[0]); device_initialize(&ms7724se_ceu_devices[1]->dev); arch_setup_pdev_archdata(ms7724se_ceu_devices[1]); dma_declare_coherent_memory(&ms7724se_ceu_devices[1]->dev, ceu1_dma_membase, ceu1_dma_membase, ceu1_dma_membase + CEU_BUFFER_MEMORY_SIZE - 1); platform_device_add(ms7724se_ceu_devices[1]); return platform_add_devices(ms7724se_devices, ARRAY_SIZE(ms7724se_devices)); }